CN114695283A - Chip packaging structure and manufacturing method thereof - Google Patents
Chip packaging structure and manufacturing method thereof Download PDFInfo
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- CN114695283A CN114695283A CN202011584370.6A CN202011584370A CN114695283A CN 114695283 A CN114695283 A CN 114695283A CN 202011584370 A CN202011584370 A CN 202011584370A CN 114695283 A CN114695283 A CN 114695283A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 22
- 230000002093 peripheral effect Effects 0.000 claims abstract description 49
- 229910000679 solder Inorganic materials 0.000 claims abstract description 28
- 239000010410 layer Substances 0.000 claims description 272
- 239000000463 material Substances 0.000 claims description 45
- 238000000034 method Methods 0.000 claims description 29
- 239000002335 surface treatment layer Substances 0.000 claims description 20
- 229920002379 silicone rubber Polymers 0.000 claims description 10
- 239000004945 silicone rubber Substances 0.000 claims description 10
- 239000006087 Silane Coupling Agent Substances 0.000 claims description 8
- 239000012790 adhesive layer Substances 0.000 claims description 7
- 229920000642 polymer Polymers 0.000 claims description 7
- 239000003989 dielectric material Substances 0.000 claims description 6
- 239000003822 epoxy resin Substances 0.000 claims description 6
- 229920000647 polyepoxide Polymers 0.000 claims description 6
- 238000005538 encapsulation Methods 0.000 claims 2
- 239000000178 monomer Substances 0.000 claims 1
- 238000003466 welding Methods 0.000 abstract description 2
- 238000007654 immersion Methods 0.000 description 5
- 239000004593 Epoxy Substances 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 239000000084 colloidal system Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 239000013013 elastic material Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 description 2
- 239000005022 packaging material Substances 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 239000002318 adhesion promoter Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention provides a chip packaging structure and a manufacturing method thereof. The chip packaging structure comprises a chip, a stress buffer layer, a first insulating layer, a reconfiguration circuit layer, a second insulating layer and a welding ball. The chip has an active surface, a back surface and a peripheral surface. The stress buffer layer covers the active surface and the peripheral surface, and the first insulating layer is configured on the back surface of the chip. The bottom surface of the stress buffer layer is aligned with the back surface of the chip. The reconfiguration circuit layer is electrically connected with the chip through the opening of the stress buffer layer. The second insulating layer covers the stress buffer layer and the reconfiguration line layer. The solder balls are arranged in the blind holes of the second insulating layer and are electrically connected with the redistributing circuit layer. The top surface of the solder ball protrudes from the upper surface of the second insulating layer. The chip packaging structure can effectively protect the edge of the chip and increase the overall structural strength and structural reliability.
Description
Technical Field
The present disclosure relates to chip packaging structures and, particularly, to a chip packaging structure and a method for fabricating the same.
Background
In the prior art, an overhang structure under an elastic material, a packaging material or a bare die can be used as an anchor to protect the edge of a chip or enhance the mechanical strength of a packaging colloid. At present, in products, the elastic material or the packaging material only protects the wafer back and the spherical surface, but cannot effectively protect the chip edge. Or, in another product, the package material is used to protect the chip edge, and although the chip failure caused by chip crack (crack) can be avoided in the reliability experiment, the reliability times and the product use time are shortened due to the difference of the thermal expansion coefficients between the package colloid and the chip.
Disclosure of Invention
The invention is directed to a chip packaging structure, which can effectively protect the edge of a chip and increase the overall structural strength and structural reliability.
The invention also relates to a manufacturing method of the chip packaging structure, which is used for manufacturing the chip packaging structure.
According to an embodiment of the invention, the chip packaging structure comprises a chip, a stress buffer layer, a first insulating layer, a reconfiguration line layer, a second insulating layer and a welding ball. The chip has an active surface and a back surface opposite to each other and a peripheral surface connecting the active surface and the back surface. The stress buffer layer covers the active surface and the peripheral surface of the chip and is provided with an opening exposing part of the active surface of the chip. The first insulating layer is configured on the back surface of the chip. The stress buffer layer is arranged on the first insulating layer in an extending mode, and the bottom surface of the stress buffer layer is aligned with the back surface of the chip in a cutting mode. The redistribution layer is configured on the active surface of the chip and extends into the opening of the stress buffer layer. The redistribution layer is electrically connected with the chip through the opening. The second insulating layer covers the stress buffer layer and the reconfiguration line layer and is provided with a blind hole exposing part of the reconfiguration line layer. The solder balls are arranged in the blind holes of the second insulating layer and are electrically connected with the redistributing circuit layer. The top surface of the solder ball protrudes from the upper surface of the second insulating layer.
In the chip package structure according to the embodiment of the invention, the redistribution layer includes a circuit layer and a conductive via. The conductive through hole is positioned between the circuit layer and the active surface of the chip. The chip is electrically connected with the circuit layer through the conductive through hole.
In the chip package structure according to the embodiment of the invention, the first insulating layer has a first peripheral surface, the second insulating layer has a second peripheral surface, and the stress buffer layer has a third peripheral surface. The second peripheral surface is aligned with the third peripheral surface and the first peripheral surface.
In the chip package structure according to the embodiment of the invention, the chip package structure further includes a surface treatment layer disposed on the redistribution layer exposed by the blind via of the second insulating layer. The solder balls are electrically connected with the reconfiguration circuit layer through the surface treatment layer.
In the chip package structure according to the embodiment of the invention, the thickness of the stress buffer layer is greater than 0 and less than or equal to 1 micrometer.
In the chip package structure according to the embodiment of the invention, the material of the stress buffer layer is different from the material of the first insulating layer and the material of the second insulating layer.
In the chip package structure according to the embodiment of the invention, the material of the stress buffer layer includes a Silane coupling agent polymer (Silane adhesion promoter), a silicone rubber (silicone rubber), an Epoxy resin (Epoxy), or a photosensitive dielectric material (for example, PI, PBO, BCB, or PID), but is not limited thereto.
In the chip package structure according to an embodiment of the invention, the first insulating layer includes an Ajinomoto Build up Film (ABF) or an encapsulating adhesive layer.
In the chip package structure according to the embodiment of the invention, the material of the first insulating layer is the same as the material of the second insulating layer.
In the chip package structure according to the embodiment of the invention, a material of the first insulating layer is different from a material of the second insulating layer.
According to an embodiment of the invention, a method for manufacturing a chip packaging structure comprises the following steps. A plurality of chips separated from each other are disposed on the first insulating layer. Each chip has an active surface and a back surface opposite to each other and a peripheral surface connecting the active surface and the back surface. The back surface of each chip directly contacts the first insulating layer. A stress buffer layer is formed on the first insulating layer. The stress buffer layer extends to cover the active surface and the peripheral surface of each chip, and the bottom surface of the stress buffer layer is aligned with the back surface of each chip. A second insulating layer is formed to cover the stress buffer layer. Forming a redistribution layer in the second insulating layer. The stress buffer layer is provided with an opening exposing part of the active surface of the chip, and the reconfiguration line layer is electrically connected with the chip through the opening. Forming a plurality of blind holes separated from each other in the second insulating layer, wherein the blind holes expose a portion of the redistribution layer. And forming a plurality of solder balls in the blind holes respectively, wherein the solder balls are electrically connected with the reconfiguration circuit layer exposed by the blind holes. The top surface of each solder ball protrudes out of the upper surface of the second insulating layer. And performing a singulation process to cut the second insulating layer, the stress buffer layer and the first insulating layer to form a plurality of chip packaging structures separated from each other.
In the manufacturing method of the chip package structure according to the embodiment of the invention, the redistribution layer includes a circuit layer and a conductive via. The conductive through hole is positioned between the circuit layer and the active surface of the chip. The chip is electrically connected with the circuit layer through the conductive through hole.
In the method for manufacturing a chip package structure according to an embodiment of the invention, the first insulating layer of each chip package structure has a first peripheral surface, the second insulating layer has a second peripheral surface, and the stress buffer layer has a third peripheral surface. The second peripheral surface is aligned with the third peripheral surface and the first peripheral surface.
In the manufacturing method of the chip package structure according to the embodiment of the invention, the manufacturing method of the chip package structure further includes: before forming solder balls in the blind holes respectively, a surface treatment layer is formed in the blind holes. The surface treatment layer is arranged on the reconfiguration circuit layer exposed by the blind holes, and the solder balls are electrically connected with the reconfiguration circuit layer through the surface treatment layer.
In the method for manufacturing the chip package structure according to the embodiment of the invention, the thickness of the stress buffer layer is greater than 0 and less than or equal to 1 micrometer.
In the method for manufacturing the chip package structure according to the embodiment of the invention, the material of the stress buffer layer is different from the material of the first insulating layer and the material of the second insulating layer.
In the method for manufacturing a chip package structure according to an embodiment of the invention, the material of the stress buffer layer includes a Silane coupling agent polymer (Silane coupling agent), a silicone rubber (silicone rubber), an Epoxy resin (Epoxy), or a photosensitive dielectric material (for example, PI, PBO, BCB, or PID), but is not limited thereto.
In the method for manufacturing a chip package structure according to an embodiment of the present invention, the first insulating layer includes an ajinomoto increasing film or a packaging adhesive layer.
In the method for manufacturing a chip package structure according to an embodiment of the present invention, a material of the first insulating layer is the same as a material of the second insulating layer.
In the method for manufacturing a chip package structure according to an embodiment of the present invention, a material of the first insulating layer is different from a material of the second insulating layer.
In the manufacturing method of the chip package structure according to the embodiment of the invention, the manufacturing method of the chip package structure further includes: before the chips separated from each other are arranged on the first insulating layer, a carrier plate and a release film positioned on the carrier plate are provided. The release film is located between the first insulating layer and the carrier plate. After the singulation process, the release film and the carrier are removed to expose the lower surface of the first insulating layer.
Based on the above, in the chip package structure of the invention, the stress buffer layer covers the active surface and the peripheral surface of the chip, and the first insulating layer covers the back surface of the chip. That is, the chip is directly wrapped between the stress buffer layer and the first insulating layer. Therefore, the edge of the chip is protected by the stress buffer layer, and the structural strength of the whole chip packaging structure is enhanced by the arrangement of the first insulating layer and the second insulating layer. Therefore, the chip packaging structure of the invention has better structure reliability.
Drawings
Fig. 1A to fig. 1G are schematic cross-sectional views illustrating a method for manufacturing a chip package structure according to an embodiment of the invention;
fig. 1H is a schematic cross-sectional view of a chip package structure according to an embodiment of the invention.
Description of the reference numerals
10, a carrier plate;
20, release film;
100, a chip packaging structure;
110, a chip;
112, an active surface;
114, a back side;
116, a peripheral surface;
120, stress buffer layer;
121, an opening;
124, a bottom surface;
132 a first insulating layer;
133 lower surface;
134 a second insulating layer;
135, the upper surface;
140 reconfiguration line layer;
142, a circuit layer;
144, conductive vias;
150, surface treatment layer;
160, solder balls;
162 a top surface;
b, blind holes;
s1, a first peripheral surface;
s2, a second perimetral surface;
s3, a third peripheral surface;
t is the thickness.
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Fig. 1A to fig. 1G are schematic cross-sectional views illustrating a method for manufacturing a chip package structure according to an embodiment of the invention. Fig. 1H is a schematic cross-sectional view of a chip package structure according to an embodiment of the invention.
Referring to fig. 1A, a carrier 10 and a release film 20 on the carrier 10 are provided. The release film 20 completely covers the surface of the carrier 10, wherein the release film 20 is, for example, a thermal release film (thermal release film), but not limited thereto.
Next, referring to fig. 1A, a first insulating layer 132 is formed on the release film 20, wherein the first insulating layer 132 completely covers the surface of the release film 20, and the release film 20 is sandwiched between the first insulating layer 132 and the carrier 10. Here, the first insulating layer is, for example, an ajinomoto increasing film (ABF) or an encapsulating adhesive layer, but not limited thereto.
Next, referring to fig. 1B, a plurality of chips 110 separated from each other are disposed on the first insulating layer 132. Each chip 110 has an active surface 112 and a back surface 114 opposite to each other and a peripheral surface 116 connecting the active surface 112 and the back surface 114. Here, the back surface 114 of each chip 110 directly contacts the first insulating layer 132.
Next, referring to fig. 1C, a stress buffer layer 120 is formed on the first insulating layer 132. The stress buffer layer 120 extends to cover the active surface 112 and the peripheral surface 116 of each chip 110, and a bottom surface 124 of the stress buffer layer 120 is aligned with the back surface 114 of the chip 110. That is, the chip 110 of the present embodiment is directly wrapped between the stress buffer layer 120 and the first insulating layer 132.
Here, the thickness T of the stress buffer layer 120 is, for example, greater than 0 and less than or equal to 1 micrometer, wherein the method for forming the stress buffer layer 120 is, for example, evaporation or immersion, but not limited thereto. In addition, in the present embodiment, the material of the stress buffer layer 120 is different from that of the first insulating layer 132, and preferably, the material of the stress buffer layer 120 is, for example, Silane coupling agent polymer (Silane coupling polymer), silicone rubber (silicone rubber), Epoxy resin (Epoxy), or photosensitive dielectric material (for example, PI, PBO, BCB, or PID), but not limited thereto.
Next, referring to fig. 1D, a second insulating layer 134 is formed to cover the stress buffer layer 120. Here, the material of the second insulating layer 134 may be the same as the material of the first insulating layer 132, that is, the material of the second insulating layer 134 is an ajinomoto enhanced film (ABF) or an encapsulating adhesive layer. In another embodiment, the material of the second insulating layer 134 may be different from the material of the first insulating layer 132. In other words, the material of the stress buffer layer 120 of the present embodiment is different from the material of the first insulating layer 132 and the material of the second insulating layer 134. Preferably, the thickness of the second insulating layer 134 is greater than the thickness of the first insulating layer 132, wherein the thickness of the second insulating layer 134 is at least 150 μm.
Next, referring to fig. 1E, a redistribution layer 140 is formed in the second insulating layer 134. The stress buffer layer 120 has an opening 121 exposing a portion of the active surface 112 of the chip 110, and the redistribution layer 140 is electrically connected to the chip 110 through the opening 121. Here, the redistribution layer 140 includes a circuit layer 142 and a conductive via 144, wherein the circuit layer 142 is embodied as a patterned circuit layer. The conductive via 144 is located between the circuit layer 142 and the active surface 112 of the chip 110, wherein the chip 110 is electrically connected to the circuit layer 142 through the conductive via 144.
Next, referring to fig. 1E, a plurality of blind holes B separated from each other are formed in the second insulating layer 134, wherein the blind holes B expose a portion of the redistribution layer 140. As shown in fig. 1E, a portion of the redistribution layer 142 of the redistribution layer 140 is exposed by the blind via B. Next, a surface treatment layer 150 is formed in the blind via B, wherein the surface treatment layer 150 is disposed on the redistribution layer 140 exposed by the blind via B. That is, the surface treatment layer 150 is disposed on the circuit layer 142 exposed by the blind via B. Here, the surface treatment layer 150 is, for example, Nickel palladium Immersion Gold (ENEPIG), organic solder resist (OSP) layer, or Electroless Nickel Immersion Gold (ENIG), but is not limited thereto.
Next, referring to fig. 1F, a plurality of solder balls 160 are formed in the blind vias B, respectively, wherein the solder balls 160 are electrically connected to the redistribution layer 140 exposed by the blind vias B. More specifically, the solder balls 160 are electrically connected to the redistribution layer 140 through the surface treatment layer 150. Here, the top surface 162 of each solder ball 160 protrudes from the upper surface 135 of the second insulating layer 134 for electrical connection with an external circuit.
Then, referring to fig. 1F and fig. 1G, a singulation process is performed to cut the second insulating layer 134, the stress buffer layer 120, and the first insulating layer 132, so as to form a plurality of chip package structures 100 separated from each other. Then, the release film 20 and the carrier 10 are removed to expose the lower surface 133 of the first insulating layer 132. Thus, the chip package structure 100 is completed.
In brief, in the present embodiment, the wafer level package technology is utilized, after the chip 110 is placed on the carrier 10, the stress buffer layer 120 is coated, the redistribution layer 140 and the surface treatment layer 150 are fabricated and the ball-mounting process is performed, and finally, the chip package structure 100 of the present embodiment is completed by cutting and board-detaching.
Structurally, referring to fig. 1H, the chip package structure 100 includes a chip 110, a stress buffer layer 120, a first insulating layer 132, a redistribution layer 140, a second insulating layer 134, and solder balls 160. The chip 110 has an active surface 112 and a back surface 114 opposite to each other and a peripheral surface 116 connecting the active surface 112 and the back surface 114. The stress buffer layer 120 covers the active surface 112 and the peripheral surface 116 of the chip 110, and has an opening 121 exposing a portion of the active surface 112 of the chip 110. Here, the thickness T of the stress buffer layer 120 is, for example, greater than 0 and 1 μm or less. Preferably, the material of the stress buffer layer 120 is, for example, a Silane coupling agent polymer (Silane coupling agent), a silicone rubber (silicone rubber), an Epoxy resin (Epoxy), or a photosensitive dielectric material (for example, PI, PBO, BCB, or PID), but not limited thereto.
Furthermore, the first insulating layer 132 of the present embodiment is disposed on the back surface 114 of the chip 110. The stress buffer layer 120 extends over the first insulating layer 132, and the bottom surface 124 of the stress buffer layer 120 is aligned with the back surface 114 of the chip 110. The redistribution layer 140 is disposed on the active surface 112 of the chip 110 and extends into the opening 121 of the stress buffer layer 120, wherein the redistribution layer 140 is electrically connected to the chip 110 through the opening 121. More specifically, the redistribution layer 140 includes a circuit layer 142 and a conductive via 144. The conductive via 144 is located between the circuit layer 142 and the active surface 112 of the chip 110, and the chip 110 is electrically connected to the circuit layer 142 through the conductive via 144. The second insulating layer 134 covers the stress buffer layer 120 and the redistribution layer 140, and has a blind via B exposing a portion of the redistribution layer 140.
More specifically, the first insulating layer 132 has a first peripheral surface S1, the second insulating layer 134 has a second peripheral surface S2, and the stress buffer layer 120 has a third peripheral surface S3. Preferably, the second peripheral surface S2 is aligned with the third peripheral surface S3 and the first peripheral surface S1. Here, the material of the first insulating layer 132 and the material of the second insulating layer 134 may be the same or different, wherein the first insulating layer 132 is, for example, an ajinomoto increasing film (ABF) or an encapsulating adhesive layer. The material of the stress buffer layer 120 is different from the material of the first insulating layer 132 and the material of the second insulating layer 134.
In addition, the solder balls 160 of the present embodiment are disposed in the blind vias B of the second insulating layer 134 and electrically connected to the redistribution layer 140, wherein the top surfaces 162 of the solder balls 160 protrude from the upper surface 135 of the second insulating layer 134 for electrical connection with an external circuit. In addition, the chip package structure 100 of the present embodiment further includes a surface treatment layer 150 disposed on the redistribution layer 140 exposed by the blind via B of the second insulating layer 134. The solder balls 160 are electrically connected to the redistribution layer 140 through the surface treatment layer 150. The surface treatment layer 150 is, for example, Nickel palladium Immersion Gold (ENEPIG), Organic Solderability Preservations (OSP), or Electroless Nickel Immersion Gold (ENIG), but is not limited thereto.
In short, the chip 110 of the present embodiment is directly wrapped between the stress buffer layer 120 and the first insulating layer 132. Therefore, the edge of the chip is protected by the stress buffer layer 120, and the structural strength of the entire chip package structure 100 is enhanced by the arrangement of the first insulating layer 132 and the second insulating layer 134. Therefore, the chip package structure 100 of the present embodiment has better structural reliability.
In summary, in the chip package structure of the invention, the stress buffer layer covers the active surface and the peripheral surface of the chip, and the first insulating layer covers the back surface of the chip. That is, the chip is directly wrapped between the stress buffer layer and the first insulating layer. Therefore, the edge of the chip is protected by the stress buffer layer, and the structural strength of the whole chip packaging structure is enhanced by the arrangement of the first insulating layer and the second insulating layer. Therefore, the chip packaging structure of the invention has better structure reliability.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (21)
1. A chip package structure, comprising:
a chip having an active surface and a back surface opposite to each other and a peripheral surface connecting the active surface and the back surface;
the stress buffer layer covers the active surface and the peripheral surface of the chip and is provided with an opening for exposing part of the active surface of the chip;
a first insulating layer disposed on the back surface of the chip, wherein the stress buffer layer extends over the first insulating layer and has a bottom surface aligned with the back surface of the chip;
the reconfiguration line layer is configured on the active surface of the chip and extends into the opening of the stress buffer layer, and the reconfiguration line layer is electrically connected with the chip through the opening;
a second insulating layer covering the stress buffer layer and the redistribution layer and having a blind via exposing a portion of the redistribution layer; and
and the solder balls are arranged in the blind holes of the second insulating layer and are electrically connected with the reconfiguration circuit layer, and the top surfaces of the solder balls protrude out of the upper surface of the second insulating layer.
2. The chip package structure according to claim 1, wherein the redistribution layer comprises a wiring layer and a conductive via between the wiring layer and the active surface of the chip, and the chip is electrically connected to the wiring layer through the conductive via.
3. The chip package structure according to claim 1, wherein the first insulating layer has a first peripheral surface, the second insulating layer has a second peripheral surface, and the stress buffer layer has a third peripheral surface, and the second peripheral surface is aligned with the third peripheral surface and the first peripheral surface.
4. The chip package structure according to claim 1, further comprising:
and the surface treatment layer is configured on the reconfiguration circuit layer exposed by the blind holes of the second insulating layer, and the solder balls are electrically connected with the reconfiguration circuit layer through the surface treatment layer.
5. The chip package structure according to claim 1, wherein the stress buffer layer has a thickness greater than 0 and equal to or less than 1 μm.
6. The chip package structure according to claim 1, wherein a material of the stress buffer layer is different from a material of the first insulating layer and a material of the second insulating layer.
7. The chip package structure according to claim 6, wherein the stress buffer layer is made of a silane coupling agent polymer, silicone rubber, epoxy resin or photosensitive dielectric material.
8. The chip package structure according to claim 1, wherein the first insulating layer comprises an ajinomoto enhanced film or an encapsulation adhesive layer.
9. The chip package structure according to claim 8, wherein the first insulating layer is made of the same material as the second insulating layer.
10. The chip package structure according to claim 8, wherein a material of the first insulating layer is different from a material of the second insulating layer.
11. A method for manufacturing a chip packaging structure is characterized by comprising the following steps:
disposing a plurality of chips separated from each other on a first insulating layer, wherein each of the plurality of chips has an active surface and a back surface opposite to each other and a peripheral surface connecting the active surface and the back surface, the back surface of each of the plurality of chips directly contacting the first insulating layer;
forming a stress buffer layer on the first insulating layer, wherein the stress buffer layer extends to cover the active surface and the peripheral surface of each of the plurality of chips, and the bottom surface of the stress buffer layer is aligned with the back surface of the chip;
forming a second insulating layer to cover the stress buffer layer;
forming a redistribution layer in the second insulating layer, wherein the stress buffer layer has an opening exposing a part of the active surface of the chip, and the redistribution layer is electrically connected with the chip through the opening;
forming a plurality of blind holes separated from each other in the second insulating layer, wherein the plurality of blind holes expose a portion of the redistribution layer;
forming a plurality of solder balls in the plurality of blind holes respectively, wherein the plurality of solder balls are electrically connected with the redistribution circuit layer exposed by the plurality of blind holes, and the top surface of each of the plurality of solder balls protrudes out of the upper surface of the second insulating layer; and
and carrying out a monomer process to cut the second insulating layer, the stress buffer layer and the first insulating layer to form a plurality of chip packaging structures separated from each other.
12. The method of claim 11, wherein the redistribution layer comprises a trace layer and a conductive via, the conductive via is located between the trace layer and the active surface of the chip, and the chip is electrically connected to the trace layer through the conductive via.
13. The method of claim 11, wherein the first insulating layer of each of the plurality of chip package structures has a first peripheral surface, the second insulating layer has a second peripheral surface, the stress buffer layer has a third peripheral surface, and the second peripheral surface is aligned with the third peripheral surface and the first peripheral surface.
14. The method for manufacturing the chip package structure according to claim 11, further comprising:
before forming the solder balls in the blind holes respectively, forming a surface treatment layer in the blind holes, wherein the surface treatment layer is configured on the reconfiguration circuit layer exposed by the blind holes, and the solder balls are electrically connected with the reconfiguration circuit layer through the surface treatment layer.
15. The method of claim 11, wherein the stress buffer layer has a thickness greater than 0 and less than or equal to 1 μm.
16. The method of claim 11, wherein a material of the stress buffer layer is different from a material of the first insulating layer and a material of the second insulating layer.
17. The method of claim 16, wherein the stress buffer layer is made of a silane coupling agent polymer, silicone rubber, epoxy resin, or photosensitive dielectric material.
18. The method of claim 11, wherein the first insulating layer comprises an ajinomoto enhancement film or an encapsulation adhesive layer.
19. The method of claim 18, wherein the first insulating layer is made of the same material as the second insulating layer.
20. The method of claim 18, wherein a material of the first insulating layer is different from a material of the second insulating layer.
21. The method for manufacturing the chip package structure according to claim 11, further comprising:
before the chips which are separated from each other are configured on the first insulating layer, a carrier plate and a release film positioned on the carrier plate are provided, wherein the release film is positioned between the first insulating layer and the carrier plate; and
after the singulation process, the release film and the carrier plate are removed to expose the lower surface of the first insulating layer.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114839716A (en) * | 2022-07-05 | 2022-08-02 | 天津华慧芯科技集团有限公司 | Optical modulator structure capable of realizing low roughness of end face and preparation method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114839716A (en) * | 2022-07-05 | 2022-08-02 | 天津华慧芯科技集团有限公司 | Optical modulator structure capable of realizing low roughness of end face and preparation method |
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