CN114695263A - 晶体管、晶体管中的栅极结构及栅极结构的形成方法 - Google Patents

晶体管、晶体管中的栅极结构及栅极结构的形成方法 Download PDF

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CN114695263A
CN114695263A CN202110921222.7A CN202110921222A CN114695263A CN 114695263 A CN114695263 A CN 114695263A CN 202110921222 A CN202110921222 A CN 202110921222A CN 114695263 A CN114695263 A CN 114695263A
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layer
conductive material
dielectric layer
nanostructures
nanostructure
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李欣怡
洪正隆
徐志安
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种晶体管、晶体管中的栅极结构及栅极结构的形成方法，在一些实施例中，一种形成栅极结构的方法包括：在一基板上方形成多个纳米结构；蚀刻该些纳米结构以形成第一凹槽；在该些第一凹槽中形成源极/漏极区；移除该些纳米结构中的第一纳米结构，从而留下该些纳米结构中的第二纳米结构；在该些第二纳米结构上方且周围沉积一栅极介电层；对该栅极介电层执行一铝处置；在该栅极介电层上方且周围沉积一第一导电材料；对该第一导电材料执行一氟处置；及在该第一导电材料上方且周围沉积一第二导电材料。

Description

晶体管、晶体管中的栅极结构及栅极结构的形成方法
技术领域
本揭露关于一种晶体管、晶体管中的栅极结构及栅极结构的形成方法。
背景技术
半导体装置用于多种电子应用，诸如例如个人计算机、手机、数字摄影机及其他电子装备中。半导体装置通常通过以下操作来制造：在半导体基板上方依序沉积绝缘或介电层、导电层及半导体材料层，及使用光微影来使各种材料层图案化以在基板上形成电路组件及元件。
半导体行业通过最小特征大小上的连续减小而继续改良各种电子组件(例如，晶体管、二极体、电阻器、电容器等)的整合密度，此情形允许更多组件整合至给定区域中。然而，随着最小特征大小被减小，应解决的额外问题出现。
发明内容
根据本揭露的一些实施例中，一种形成栅极结构的方法包括：在一基板上方形成多个纳米结构；蚀刻该些纳米结构以形成第一凹槽；在该些第一凹槽中形成源极/漏极区；移除该些纳米结构中的第一纳米结构，从而留下该些纳米结构中的第二纳米结构；在该些第二纳米结构上方且周围沉积一栅极介电层；对该栅极介电层执行一铝处置；在该栅极介电层上方且周围沉积一第一导电材料；对该第一导电材料执行一氟处置；及在该第一导电材料上方且周围沉积一第二导电材料。
根据本揭露的一些实施例中，一种栅极结构包括：一第一纳米结构，该第一纳米结构在一源极区与一漏极区之间延伸；该第一纳米结构上方的一第二纳米结构；一栅极介电层，该栅极介电层是在该第一纳米结构及该第二纳米结构上方且周围；该栅极介电层上方的一铝残余物；该栅极介电层及该铝残余物上方的一功函数金属(WFM)层，该WFM层包含氟，该WFM层的一第一部分安置于该第一纳米结构周围，该WFM层的一第二部分安置于该第二纳米结构周围；及一导电层，该导电层安置于该WFM层上方，该导电层的一第一部分安置于该第一纳米结构周围，该导电层的一第二部分安置于该第二纳米结构周围。
根据本揭露的一些实施例中，一种晶体管包括：一第一介电材料，该第一介电材料安置于一第一纳米结构上方；一第一金属残余物，该第一金属残余物安置于该第一介电材料上方；一第一导电材料，该第一导电材料安置于该第一介电材料上方；一第二导电材料，该第二导电材料安置于该第一导电材料上方；一第三导电材料，该第三导电材料安置于该第二导电材料上方，该第三导电材料具有与该第一导电材料相同的组合物；一第二金属残余物，该第二金属残余物安置于该第三导电材料上方，该第二金属残余物具有与该第一金属残余物相同的组合物；一第二介电材料，该第二介电材料安置于该第二金属残余物上方，该第二介电材料具有与该第一介电材料相同的组合物；及一第二纳米结构，该第二纳米结构安置于该第二介电材料上方。
附图说明
本揭露的态样在与随附附图一起研读时自以下详细描述内容来最佳地理解。应注意，根据行业中的标准惯例，各种特征未按比例绘制。实际上，各种特征的尺寸可为了论述清楚经任意地增大或减小。
图1图示根据一些实施例的三维视图中纳米结构场效晶体管(nanostructurefield-effect transistor，nano-FET)的实例；
图2、图3、图4、图5、图6A、图6B、图7A、图7B、图8A、图8B、图9A、图9B、图10A、图10B、图11A、图11B、图11C、图12A、图12B、图12C、图12D、图13A、图13B、图13C、图14A、图14B、图15A、图15B、图16A、图16B、图17A、图17B、图18A、图18B、图19A、图19B、图20A、图20B、图21A、图21B、图22A、图22B、图23A、图23B、图23C、图23D、图24A、图24B、图25A、图25B、图25C、图26A、图26B、图26C、图27A、图27B及图27C为根据一些实施例的制造纳米FET中中间阶段的横截面图；
图28A、图28B及图28C为根据一些实施例的纳米FET的横截面图；
图29A、图29B、图29C、图29D及图29E为根据一些实施例的纳米FET的横截面图。
【符号说明】
20:分隔器
50:基板
50I:区
50N:N型区
50P:P型区
51:第一半导体层
51A:第一半导体层
51B:第一半导体层
51C:第一半导体层
52:第一纳米结构
52A:第一纳米结构
52B:第一纳米结构
52C:第一纳米结构
53:第二半导体层
53A:第二半导体层
53B:第二半导体层
53C:第二半导体层
54:第二纳米结构
54A:第二纳米结构
54B:第二纳米结构
54C:第二纳米结构
55:纳米结构
64:多层堆叠
66:鳍片
68:浅沟槽隔离区(STI)区
70:虚设介电层
71:虚设栅极介电层
72:虚设栅极层/虚设栅极
74:遮罩层
76:虚设栅极
78:遮罩
80:第一间隔物层
81:第一间隔物
82:第二间隔物层
83:第二间隔物
86:第一凹槽
88:侧壁凹槽
90:第一内部间隔物
92:磊晶源极/漏极区
92A:第一半导体材料层
92B:第二半导体材料层
92C:第三半导体材料层
94:触点蚀刻终止层(CESL)
96:第一层间介电质(ILD)
98:第二凹槽
100:栅极介电层
101:第一栅极介电层/界面层
102:栅极电极
103:第二栅极介电层
104:栅极遮罩
105:第一导电材料
106:第二层间介电质(ILD)
107:第二导电材料
107A:第一部分/导电材料
107B:第二部分/导电材料
107S:界面
108:第三凹槽
109:铝处置
110:硅化物区
111:铝的第一残余物
112:触点
113:氟处置
114:触点
115:金属的第二残余物
117:粘着层
119:下伏填充金属
121:导电材料
123:阻障层
125:填充金属
127:栅极电极
130:开口
A-A’:横截面
B-B’:横截面
C-C’:横截面
具体实施方式
以下揭示内容提供用于实施本揭露的不同特征的许多不同实施例或实例。下文描述组件及配置的特定实例以简化本揭露。当然，这些组件及配置仅为实例且并非意欲为限制性的。举例而言，在以下描述中第一特征于第二特征上方或上的形成可包括第一及第二特征直接接触地形成的实施例，且亦可包括额外特征可形成于第一特征与第二特征之间使得第一特征及第二特征可不直接接触的实施例。此外，本揭露在各种实例中可重复参考数字及/或字母。此重复是出于简单及清楚的目的，且本身并不指明所论述的各种实施例及/或组态之间的关系。
另外，空间相对术语，诸如“……下面”、“下方”、“下部”、“……上方”、“上部”及类似者本文中可出于易于描述而使用以描述如诸图中图示的一个元素或特征与另一(些)元素或特征的关系。空间相对术语意欲涵盖装置的使用或操作中除了诸图中描绘的定向外的不同定向。设备可以其他方式定向(旋转90度或处于其他定向)，且本文中使用的空间相对描述词可同样经因此解译。
各种实施例提供栅极堆叠，该些栅极堆叠具有经铝处置的栅极介电层(例如，高k栅极介电层)及经氟处置的功函数金属(work function metal，WFM)层。举例而言，铝处置可包括对栅极介电层执行铝浸泡。在沉积WFM层之后，氟处置可包括对WFM层执行氟浸泡，该氟浸泡亦可使氟扩散至下伏栅极介电层(例如，高k栅极介电层)中。在无铝处置情况下，WFM层中的氟将具有在形成后续层之前自WFM层游离的倾向。然而，在铝处置期间沉积的铝吸收来自氟处置的氟以改良WFM层中氟的保持。此外，此吸收改良氟中的一些至栅极介电层中的其他移动或扩散。因此，所得晶体管的平带电压(VFB)可朝向WFM层的金属的带边缘增大，所得晶体管的临限电压可减低，且装置效能可得以改良。
图1图示根据一些实施例的三维视图中的纳米FET(例如，纳米导线FET、纳米片材FET、纳米结构FET或类似者)的实例。纳米FET包含基板50(例如，半导体基板)上的鳍片66上方的纳米结构55(例如，纳米片材、纳米导线或类似者)，其中纳米结构55充当纳米FET的通道区。纳米结构55可包括p型纳米结构、n型纳米结构或其组合。隔离区68安置于相邻鳍片66之间，该些相邻鳍片可在相邻隔离区68上方且自相邻隔离区68之间突出。尽管隔离区68描述/图示为与基板50分离，但如本文中所使用，术语“基板”可单独指半导体基板或指半导体基板与隔离区的组合。另外，尽管鳍片66的底部部分图示为与基板50的单独连续材料，但鳍片66及/或基板50的底部部分可包含单一材料或多种材料。在此情形下，鳍片66指在相邻隔离区68之间延伸的部分。
栅极介电层100是在鳍片66的顶表面上方且沿着纳米结构55的顶表面、侧壁及底表面。栅极电极102是在栅极介电层100上方。磊晶源极/漏极区92在栅极介电层100及栅极电极102的相对侧上安置于鳍片66上。
图1进一步图示用于后续诸图中的参考横截面。横截面A-A’是沿着栅极电极102的纵向轴线且在例如垂直于纳米FET的磊晶源极/漏极区92之间的电流流动方向的方向上。横截面B-B’垂直于横截面A-A’且平行于纳米FET的鳍片66的纵向轴线，且是在例如纳米FET的磊晶源极/漏极区92之间的电流流动的方向上。横截面C-C’平行于横截面A-A’且延伸穿过纳米FET的磊晶源极/漏极区。为了清楚，后续诸图指这些参考横截面。
本文中所论述的一些实施例在使用后栅极制程形成的纳米FET的情形下予以论述。在其他实施例中，可使用先栅极制程。又，一些实施例预期到用于平面装置，诸如平面FET或鳍片场效晶体管(fin field-effect transistor，FinFET)中的态样。
图2至图29C为根据一些实施例的纳米FET的制造中中间阶段的横截面图。图2至图5、图6A、图13A、图14A、图15A、图16A、图17A、图18A、图19A、图20A、图21A、图22A、图23A、图24A、图25A、图26A、图27A、图28A及图29A图示在图1中图示的参考横截面A-A’。图6B、图7B、图8B、图9B、图10B、图11B、图11C、图12B、图12D、图13B、图14B、图15B、图16B、图17B、图18B、图19B、图20B、图21B、图22B、图23B、图24B、图25B、图26B、图27B、图28B及图29B图示在图1中图示的参考横截面B-B’。图7A、图8A、图9A、图10A、图11A、图12A、图12C、图13C、图25C、图26C、图27C、图28C及图29E图示在图1中图示的参考横截面C-C’。
在图2中，设置基板50。基板50可为半导体基板，诸如块体基板、绝缘体上半导体(semiconductor-on-insulator，SOI)基板或类似者，该基板可经掺杂(例如，运用p型或n型掺杂剂)或未经掺杂。基板50可为晶圆，诸如硅晶圆。具体而言，SOI基板为形成于绝缘体层上的半导体材料层。举例而言，绝缘体层可为嵌埋氧化物(buried oxide，BOX)层、氧化硅层或类似者。绝缘体层设置于基板，通常硅或玻璃基板上。亦可使用诸如多层或梯度基板的其他基板。在一些实施例中，基板50的半导体材料可包括：硅；锗；包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟及/或锑化铟的化合物半导体；合金半导体，包括硅锗、磷化砷化镓、砷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟，及/或磷化砷化镓铟；或其组合。
基板50具有n型区50N及p型区50P。n型区50N可是用于形成n型装置，诸如NMOS晶体管(例如，n型纳米FET)；且p型区50P可是用于形成p型装置，诸如PMOS晶体管(例如，p型纳米FET)。n型区50N可与p型区50P实体分离(如通过分隔器20图示)，且任何数目个装置特征(例如，其他主动装置、经掺杂区、隔离结构等)可安置于n型区50N与p型区50P之间。尽管一个n型区50N及一个p型区50P予以图示，但可提供任何数目个n型区50N及p型区50P。在一些实施例中，一或多个井及/或反穿透(anti-punch through，APT)层可经由一或多个合适布植步骤形成于基板50中。
另外，在图2中，多层堆叠64形成于基板50上方。多层堆叠64包括第一半导体层51A至51C的交替层(统称为第一半导体层51)及第二半导体层53A至53C(统称为第二半导体层53)。出于图示的目的且如下文更详细地论述，第二半导体层53将被移除，且第一半导体层51将经图案化以在p型区50P中形成纳米FET的通道区。此外，第一半导体层51将被移除，且第二半导体层53将经图案化以在n型区50N中形成纳米FET的通道区。尽管如此，在一些实施例中，第一半导体层51可被移除，且第二半导体层53可经图案化以在n型区50N中形成纳米FET的通道区，且第二半导体层53可经移除且第一半导体层51可经图案化以在p型区50P中形成纳米FET的通道区。
在又其他实施例中，第一半导体层51可被移除，且第二半导体层53可经图案化以在n型区50N中及p型区50P两者中形成纳米FET的通道区。在其他实施例中，第二半导体层53可被移除，且第一半导体层51可经图案化以在n型区50N及p型区50P两者中形成纳米FET的通道区。在此类实施例中，n型区50N及p型区50P两者中的通道区可具有相同材料组合物(例如，硅或类似者)，且同时地形成。举例而言，图27A、图27B及图28C图示由如下此类实施例产生的结构：p型区50P及n型区50N两者中的通道区包含硅。
出于图示性目的，多层堆叠64图示为包括第一半导体层51及第二半导体层53中每一者的三个层。在一些实施例中，多层堆叠64可包括任何数目个第一半导体层51及第二半导体层53。多层堆叠64的数个层中的每一者可使用诸如以下各者的制程来磊晶生长：化学气相沉积(chemical vapor deposition，CVD)、原子层沉积(atomic layer deposition，ALD)、气相磊晶生长(vapor phase epitaxy，VPE)、分子束磊晶生长(molecular beamepitaxy，MBE)或类似者。在各种实施例中，第一半导体层51可由适合于p型纳米FET的第一半导体材料，诸如硅锗或类似者形成，且第二半导体层53可由适合于n型纳米FET的第二半导体材料，诸如硅、碳化硅或类似者形成。出于图示性目的，多层堆叠64图示为具有适合于p型纳米FET的最底半导体层。在一些实施例中，多层堆叠64可经形成，使得最底层位为适合于n型纳米FET的半导体层。
第一半导体材料及第二半导体材料可为相对于彼此具有高蚀刻选择性的材料。因此，第一半导体材料的第一半导体层51可在不显著移除n型区50N中第二半导体材料的第二半导体层53的情况下被移除，借此允许第二半导体层53被图案化以形成n型纳米FET的通道区。类似地，第二半导体材料的第二半导体层53可在不显著移除p型区50P中第一半导体材料的第一半导体层51的情况下被移除，借此允许第一半导体层51被图案化以形成p型纳米FET的通道区。在其他实施例中，n型区50N及p型区50P中的通道区可经同时形成，且具有相同材料组合物，诸如硅、硅锗或类似者。举例而言，图28A、图28B及图28C图示由如下此类实施例产生的结构：p型区50P及n型区50N两者中的通道区包含硅。
现参看图3，根据一些实施例，鳍片66形成于基板50中，且纳米结构55形成于多层堆叠64中。在一些实施例中，纳米结构55及鳍片66可分别通过在多层堆叠64及基板50中蚀刻出沟槽而形成于多层堆叠64及基板50中。蚀刻可为任何可接受蚀刻制程，诸如反应性离子蚀刻(reactive ion etch，RIE)、中性射束蚀刻(neutral beam etch，NBE)、类似者或其组合。蚀刻可为各向异性的。通过蚀刻多层堆叠64形成纳米结构55可进一步自第一半导体层51界定第一纳米结构52A至52C(统称为第一纳米结构52)，且自第二半导体层53界定第二纳米结构54A至54C(统称为第二纳米结构54)。第一纳米结构52及第二纳米结构54可进一步被统称为纳米结构55。
鳍片66及纳米结构55可通过任何合适方法来图案化。举例而言，鳍片66及纳米结构55可使用一或多种光学微影制程，包括双重图案化或多重图案化制程来图案化。具体而言，双重图案化或多重图案化制程组合光学微影及自对准制程，从而允许图案被产生，该些图案相较于使用单一直接光学微影制程以其他方式可获得的图案具有例如较小间距。举例而言，在一个实施例中，牺牲层形成于基板上方，且使用光学微影制程来图案化。间隔物使用自对准制程沿着经图案化的牺牲层来形成。牺牲层接着经移除，且剩余间隔物可接着用于使鳍片66图案化。
图3出于图示性目的图示n型区50N及p型区50P中的鳍片66为具有大致上相等的宽度。在一些实施例中，n型区50N中的鳍片66的宽度相较于p型区50P中的鳍片66可较大或较小。另外，虽然鳍片66及纳米结构55中的每一者图示为始终具有一致宽度，但在其他实施例中，鳍片66及/或纳米结构55可具有渐缩侧壁，使得鳍片66及/或纳米结构55中每一者的宽度在朝向基板50的方向上连续地增大。在此类实施例中，纳米结构55中的每一者可具有不同宽度且形状为梯形。
在图4中，浅沟槽隔离区(shallow trench isolation，STI)区68相邻于鳍片66形成。STI区68可通过在基板50、鳍片66及纳米结构55上方且相邻鳍片66之间沉积绝缘材料来形成。绝缘材料可为诸如氧化硅的氧化物、氮化物、类似者或其组合，且可通过高密度电浆CVD(high-density plasma CVD，HDP-CVD)、流动性CVD(flowable CVD，FCVD)、类似者或其组合来形成。可使用通过任何可接受制程形成的其他绝缘材料。在所图示实施例中，绝缘材料为通过FCVD制程形成的氧化硅。一旦形成了绝缘材料，退火制程便可予以执行。在实施例中，绝缘材料经形成，使得过量绝缘材料覆盖纳米结构55。尽管绝缘材料图示为单一层，一些实施例可利用多个层。举例而言，在一些实施例中，衬里(并未分离地图示)可首先沿着基板50、鳍片66及纳米结构55的表面形成。其后，诸如上文论述的那些的填充材料可形成于衬里上方。
移除制程接着应用至绝缘材料以移除纳米结构55上方的过量绝缘材料。在一些实施例中，可利用诸如化学机械研磨(chemical mechanical polish，CMP)、回蚀制程、其组合或类似者的平坦化制程。平坦化制程暴露纳米结构55，使得纳米结构55及绝缘材料的顶表面在平坦化制程完成之后为平齐的。
绝缘材料接着经凹入以形成STI区68。绝缘材料经凹入，使得区50N及区50P中鳍片66的上部部分自相邻STI区68之间突出。另外，STI区68的顶表面可具有如所图示的平坦表面、凸起表面、凹入表面(诸如，碟形)，或其组合。STI区68的顶表面可通过适当蚀刻形成为平坦的、凸起及/或凹入的。STI区68可使用可接受蚀刻制程，诸如对于绝缘材料的材料为选择性的制程凹入(例如，相较于鳍片66及纳米结构55的材料以更快速度蚀刻绝缘材料的材料)。举例而言，使用例如稀释氢氟(dilute hydrofluoric，dHF)酸的氧化物移除可予以使用。
上文关于图2至图4描述的制程仅为鳍片66及纳米结构55可如何形成的一个实例。在一些实施例中，鳍片66及/或纳米结构55可使用遮罩及磊晶生长制程来形成。举例而言，介电层可形成于基板50的顶表面上方，且沟槽可蚀刻穿过介电层以暴露下伏基板50。磊晶结构可磊晶生长于沟槽中，且介电层可经凹入，使得磊晶结构自介电层突出以形成鳍片66及/或纳米结构55。磊晶结构可包含上文论述的交替半导体材料，诸如第一半导体材料及第二半导体材料。在磊晶结构经磊晶生长的一些实施例中，磊晶生长材料可在生长期间原位进行掺杂，此情形可消除先前及/或后续布植，尽管原位且布植掺杂可一起使用。
另外，仅出于图示性目的，第一半导体层51(及所得第一纳米结构52)及第二半导体层53(及所得第二纳米结构54)本文中图示且论述为在p型区50P及n型区50N中包含相同材料。因此，在一些实施例中，第一半导体层51及第二半导体层53中的一或两者可为不同材料，或以不同次序形成于p型区50P及n型区50N中。
另外，在图4中，适当井(并未分离地图示)可形成于鳍片66、纳米结构55及/或STI区68中。在具有不同井类型的实施例中，针对n型区50N及p型区50P的不同布植步骤可使用光阻剂或其他遮罩(并未分离地图示)来达成。举例而言，光阻剂可形成于n型区50N及p型区50P中的鳍片66及STI区68上方。光阻剂经图案化以暴露p型区50P。光阻剂可通过使用旋涂技术来形成，且可使用可接受的光微影技术来图案化。一旦光阻剂经图案化，n型杂质布植在p型区50P中执行，且光阻剂可充当遮罩以实质上防止n型杂质布植至n型区50N中。n型杂质可为布植于区中达在自约1013原子/cm3至约1014原子/cm3的范围内的浓度的磷、砷、锑或类似者。在布植之后，光阻剂诸如通过可接受灰化制程来移除。
在对p型区50P进行布植之后或之前，光阻剂或其他遮罩(并未分离地图示)形成于p型区50P及n型区50N中的鳍片66、纳米结构55及STI区68上方。光阻剂经图案化以暴露n型区50N。光阻剂可通过使用旋涂技术来形成，且可使用可接受的光微影技术来图案化。一旦光阻剂经图案化，p型杂质布植便可在n型区50N中执行，且光阻剂可充当遮罩以实质上防止p型杂质布植至p型区50P中。p型杂质可为布植于区中达在自约1013原子/cm3至约1014原子/cm3的范围内的浓度的硼、氟化硼、铟或类似者。在布植之后，光阻剂可诸如通过可接受灰化制程来移除。
在n型区50N及p型区50P的布植之后，退火可经执行以修复布植损害且使经布植的p型及/或n型杂质活化。在一些实施例中，磊晶鳍片的生长材料可在生长期间原位进行掺杂，此情形可消除布植，尽管原位且布植掺杂可一起使用。
在图5中，虚设介电层70形成于鳍片66及/或纳米结构55上。虚设介电层70可例如为氧化硅、氮化硅、其组合或类似者，且可根据可接受技术来沉积或热生长。虚设栅极层72形成于虚设介电层70上方，且遮罩层74形成于虚设栅极层72上方。虚设栅极层72可沉积于虚设介电层70上方，且接着诸如通过CMP来平坦化。遮罩层74可沉积于虚设栅极层72上方。虚设栅极层72可为导电或非导电材料，且可选自包括以下各者的群组：非晶硅、多晶硅(polycrystalline-silicon、polysilicon)、多晶硅锗(poly-crystalline silicon-germanium、poly-SiGe)、金属氮化物、金属硅化物、金属氧化物及金属。虚设栅极层72可通过物理气相沉积(physical vapor deposition，PVD)、CVD、溅射沉积或用于沉积所选择材料的其他技术来沉积。虚设栅极层72可由自隔离区的蚀刻具有高蚀刻选择性的其他材料制成。遮罩层74可包括例如氮化硅、氧氮化硅或类似者。在此实例中，单一虚设栅极层72及单一遮罩层74越过n型区50N及p型区50P形成。请注意，仅出于图示性目的，虚设介电层70展示为覆盖仅鳍片66及纳米结构55。在一些实施例中，虚设介电层70可经沉积，使得虚设介电层70覆盖STI区68，使得虚设介电层70在虚设栅极层72与STI区68之间延伸。
图6A至图15B图示制造实施例装置中的各种额外步骤。图6A、图7A、图8A、图9A、图10A、图11A、图12A、图12C、图13A、图13C、图14A及图15A图示区50N或区50P中的特征。在图6A及图6B中，遮罩层74(参见图5)可使用可接受光微影及蚀刻技术来图案化以形成遮罩78。遮罩78的图案接着可传送至虚设栅极层72及虚设介电层70以分别形成虚设栅极76及虚设栅极介电层71。虚设栅极76覆盖鳍片66的各别通道区。遮罩78的图案可用以实体分离虚设栅极76中的每一者与相邻虚设栅极76。虚设栅极76亦可具有大致上垂直于各别鳍片66的纵向方向的纵向方向。
在图7A及图7B中，第一间隔物层80及第二间隔物层82分别形成于图示于图6A及图6B中的结构上方。第一间隔物层80及第二间隔物层82将随后经图案化以充当用于形成自对准源极/漏极区的间隔物。在图7A及图7B中，第一间隔物层80形成于STI区68的顶表面；鳍片66、纳米结构55及遮罩78的顶表面及侧壁；及虚设栅极76及虚设栅极介电层71的侧壁上。第二间隔物层82沉积于第一间隔物层80上方。第一间隔物层80可使用诸如热氧化的技术由氧化硅、氮化硅、氧氮化硅或类似者来形成，或通过CVD、ALD或类似者来沉积。第二间隔物层82可由相较于第一间隔物层80的材料具有不同蚀刻速度的材料，诸如氧化硅、氮化硅、氮氧化物或类似者形成，且可通过CVD、ALD或类似者沉积。
在形成第一间隔物层80之后且在形成第二间隔物层82之前，经轻度掺杂的源极/漏极(lightly doped source/drain，LDD)区(并未分离地图示)的布植可予以执行。在具有不同装置类型的实施例中，类似于上文在图4中论述的布植，诸如光阻剂的遮罩可形成于n型区50N上方，同时暴露p型区50P，且适当类型(例如，p型)杂质可布植至p型区50P中的暴露鳍片66及纳米结构55中。可接着移除遮罩。随后，诸如光阻剂的遮罩可形成于p型区50P上方，同时暴露n型区50N，且适当类型杂质(例如，n型)可布植至n型区50N中的暴露鳍片66及纳米结构55中。可接着移除遮罩。n型杂质可为先前论述的n型杂质中的任一者，且p型杂质可为先前论述的p型杂质中的任一者。轻度掺杂源极/漏极区可具有在自约1×1015原子/cm3至约1×1019原子/cm3的范围内的杂质浓度。退火可用以修复布植损害且使经布植杂质活化。
在图8A及图8B中，第一间隔物层80及第二间隔物层82经蚀刻以形成第一间隔物81及第二间隔物83。如下文将更详细地论述，在后续处理期间，第一间隔物81及第二间隔物83用以自对准随后形成的源极漏极区以及保护鳍片66及/或纳米结构55的侧壁。第一间隔物层80及第二间隔物层82可使用合适蚀刻制程，诸如各向同性蚀刻制程(例如，湿式蚀刻制程)、各向异性蚀刻制程(例如，干式蚀刻制程)、每一者的组合或类似者来蚀刻。在一些实施例中，第二间隔物层82的材料相较于第一间隔物层80的材料具有不同蚀刻速度，使得第一间隔物层80在图案化第二间隔物层82时可充当蚀刻终止层，且使得第二间隔物层82在图案化第一间隔物层80时可充当遮罩。举例而言，第二间隔物层82可使用各向异性蚀刻制程来蚀刻，其中第一间隔物层80充当蚀刻终止层，其中第二间隔物层82的剩余部分形成第二间隔物83，如图8A中所图示。其后，第二间隔物83充当遮罩，同时蚀刻第一间隔物层80的暴露部分，借此形成第一间隔物81，如图8A中所图示。
如图8A中所图示，第一间隔物81及第二间隔物83安置于鳍片66及/或纳米结构55的侧壁上。如图8B中所图示，在一些实施例中，第二间隔物层82可自相邻于遮罩78、虚设栅极76及虚设栅极介电层71的第一间隔物层80上方移除，且第一间隔物81安置于遮罩78、虚设栅极76及虚设介电层60的侧壁上。在其他实施例中，第二间隔物层82的一部分可保持于相邻于遮罩78、虚设栅极76及虚设栅极介电层71的第一间隔物层80上方。
请注意，以上揭示内容大致上描述形成间隔物及LDD区的制程。可使用其他制程及序列。举例而言，可利用较少或额外间隔物，可利用不同序列的步骤(例如，第一间隔物81可在沉积第二间隔物82之前经图案化)，额外间隔物可经形成且移除，及/或类似者。此外，n型及p型装置可使用不同结构及步骤来形成。
在图9A及图9B中，根据一些实施例，第一凹槽86形成于鳍片66、纳米结构55及基板50中。磊晶源极/漏极区将随后形成于第一凹槽86中。第一凹槽86可延伸穿过第一纳米结构52及第二纳米结构54且延伸至基板50中。如图9A中所图示，STI区68的顶表面可与第一凹槽86的底表面平齐。在各种实施例中，鳍片66可经蚀刻，使得第一凹槽86的底表面安置于STI区68的顶表面下方；或类似者。第一凹槽86可通过使用各向异性蚀刻制程，诸如RIE、NBE或类似者蚀刻鳍片66、纳米结构55及基板50来形成。第一间隔物81、第二间隔物83及遮罩78在用以形成第一凹槽86的蚀刻制程期间遮蔽鳍片66、纳米结构55及基板50的数个部分。单一蚀刻制程或多个蚀刻制程可用以蚀刻纳米结构55及/或鳍片66的每一层。定时蚀刻制程可用以在第一凹槽86达到所要深度之后停止第一凹槽86的蚀刻。
在图10A及图10B中，由第一半导体材料形成的多层堆叠64(例如，第一纳米结构52)的数个层的侧壁的通过第一凹槽86暴露的数个部分经蚀刻以在n型区50N中形成侧壁凹槽88，且由第二半导体材料形成的多层堆叠64(例如，第二纳米结构54)的数个层的侧壁的通过第一凹槽86暴露的数个部分经蚀刻以在p型区50P中形成侧壁凹槽88。尽管第一纳米结构52及第二纳米结构54在侧壁凹槽88中的侧壁在图10B中图示为笔直的，但侧壁可为凹入或凸起的。侧壁可使用各向同性蚀刻制程，诸如湿式蚀刻或类似者来蚀刻。p型区50P可使用遮罩(图中未示)保护，而对于第一半导体材料为选择性的蚀刻剂用以蚀刻第一纳米结构52，使得第二纳米结构54及基板50相较于n型区50N中的第一纳米结构52保持相对未经蚀刻。类似地，n型区50N可使用遮罩(图中未示)保护，而对于第二半导体材料为选择性的蚀刻剂用以蚀刻第二纳米结构54，使得第一纳米结构52及基板50相较于p型区50P中的第二纳米结构54保持相对未经蚀刻。在第一纳米结构52包括例如SiGe且第二纳米结构54包括例如Si或SiC的实施例中，运用氢氧化四甲铵(tetramethylammonium hydroxide，TMAH)、氢氧化铵(ammonium hydroxide，NH4OH)或类似者的干式蚀刻制程可用以蚀刻n型区50N中第一纳米结构52的侧壁，且运用氟化氢、另一氟类气体或类似者的干式蚀刻制程可用以蚀刻p型区50P中第二纳米结构54的侧壁。
在图11A至图11C中，第一内部间隔物90形成于侧壁凹槽88中。第一内部间隔物90可通过将内部间隔物层(未分离地图示)沉积于图示于图10A及图10B中的结构上方来形成。第一内部间隔物90充当随后形成的源极/漏极区与栅极结构之间的隔离特征。如下文将更详细地论述，源极/漏极区将形成于第一凹槽86中，而n型区50N中的第一纳米结构52及p型区50P中的第二纳米结构54将运用对应栅极结构替换。
内部间隔物层可通过保形沉积制程，诸如CVD、ALD或类似者来沉积。内部间隔物层可包含诸如氮化硅或氧氮化硅的材料，尽管可利用具有小于约3.5的k值的低介电常数(低k)材料的任何合适材料。内部间隔物层可接着经各向异性蚀刻以形成第一内部间隔物90。尽管第一内部间隔物90的外部侧壁图示为与n型区50N中第二纳米结构54的侧壁平齐且与p型区50P中第一纳米结构52的侧壁平齐，但第一内部间隔物90的外部侧壁可分别延伸超出第二纳米结构54及/或第一纳米结构52的侧壁，或自该些侧壁凹入。
此外，尽管第一内部间隔物90的外部侧壁在图11B中图示为笔直的，但第一内部间隔物90的外部侧壁可为凹入或凸起的。作为实例，图11C图示如下实施例：第一纳米结构52的侧壁为凹入的，第一内部间隔物90的外部侧壁为凹入的，且第一内部间隔物自n型区50N中的第二纳米结构54的侧壁凹入。又图示如下实施例：第二纳米结构54的侧壁为凹入的，第一内部间隔物90的外部侧壁为凹入的，且第一内部间隔物自p型区50P中的第一纳米结构52的侧壁凹入。内部间隔物层可通过各向异性蚀刻制程，诸如RIE、NBE或类似者来蚀刻。第一内部间隔物90可通过后续蚀刻制程，诸如用以形成栅极结构的蚀刻制程来防止对随后形成的源极/漏极区(诸如下文关于图12A至图12C所论述的磊晶源极/漏极区92)的损害。
在图12A至图12C中，在第一凹槽86中形成磊晶源极/漏极区92。在一些实施例中，源极/漏极区92可施加应力于n型区50N中的第二纳米结构54及p型区50P中的第一纳米结构52上，借此改良效能。如图12B中所图示，磊晶源极/漏极区92形成于第一凹槽86中，使得每一虚设栅极76安置于各别相邻对的磊晶源极/漏极区92之间。在一些实施例中，第一间隔物81用以分离磊晶源极/漏极区92与虚设栅极72，且第一内部间隔物90用以使磊晶源极/漏极区92与纳米结构55分离开适当侧向距离，使得磊晶源极/漏极区92并不与所得纳米FET的随后形成的栅极短路连接。
n型区50N中的磊晶源极/漏极区92(例如，NMOS区)可通过遮蔽p型区50P(例如，PMOS区)来形成。接着，磊晶源极/漏极区92磊晶生长于n型区50N中的第一凹槽86中。磊晶源极/漏极区92可包括适合于n型纳米FET的任何可接受材料。举例而言，若第二纳米结构54为硅，则磊晶源极/漏极区92可包括施加张应力于第二纳米结构54上的材料，诸如硅、碳化硅、经磷掺杂碳化硅、磷化硅或类似者。磊晶源极/漏极区92可具有自纳米结构55的各别上表面提升的表面，且可具有小面。
p型区50P中的磊晶源极/漏极区92(例如，PMOS区)可通过遮蔽n型区50N(例如，NMOS区)来形成。接着，磊晶源极/漏极区92磊晶生长于p型区50P中的第一凹槽86中。磊晶源极/漏极区92可包括适合于p型纳米FET的任何可接受材料。举例而言，若第一纳米结构52为硅锗，则磊晶源极/漏极区92可包含施加压缩应力于第一纳米结构52上的材料，诸如硅锗、经硼掺杂的硅锗、锗、锗锡或类似者。磊晶源极/漏极区92亦可具有自多层堆叠64的各别表面提升的表面，且可具有小面。
类似于针对形成轻度掺杂源极/漏极区继之以退火先前论述的制程，磊晶源极/漏极区92、第一纳米结构52、第二纳米结构54及/或基板50可运用掺杂剂进行布植以形成源极/漏极区。源极/漏极区可具有在约1×1019原子/cm3与约1×1021原子/cm3之间的杂质浓度。源极/漏极区的n型及/或p型杂质可为先前论述的杂质中的任一者。在一些实施例中，磊晶源极/漏极区92可在生长期间经原位掺杂。
由于用以在n型区50N及p型区50P中形成磊晶源极/漏极区92的磊晶制程的结果，磊晶源极/漏极区92的上表面具有侧向向外扩展超出纳米结构55的侧壁的小面。在一些实施例中，这些小面使得相同NSFET的相邻磊晶源极/漏极区92合并，如通过图12A所图示。在其他实施例中，相邻磊晶源极/漏极区92在磊晶制程完成之后保持分离，如通过图12C所图示。在图示于图12A及图12C中的实施例中，第一间隔物81可经形成达STI区68的顶表面，借此阻断磊晶生长。在一些其他实施例中，第一间隔物81可覆盖纳米结构55的侧壁的数个部分，从而进一步阻断磊晶生长。在一些其他实施例中，用以形成第一间隔物81的间隔物蚀刻可经调整以移除间隔物材料以允许磊晶生长区延伸至STI区68的表面。
磊晶源极/漏极区92可包含一或多个半导体材料层。举例而言，磊晶源极/漏极区92可包含第一半导体材料层92A、第二半导体材料层92B及第三半导体材料层92C。任何数目个半导体材料层可用于磊晶源极/漏极区92。第一半导体材料层92A、第二半导体材料层92B及第三半导体材料层92C中的每一者可由不同半导体材料形成，且可经掺杂达不同掺杂剂浓度。在一些实施例中，第一半导体材料层92A可具有小于第二半导体材料层92B且大于第三半导体材料层92C的掺杂剂浓度。在磊晶源极/漏极区92包含三个半导体材料层的实施例中，第一半导体材料层92A可经沉积，第二半导体材料层92B可经沉积于第一半导体材料层92A上方，且第三半导体材料层92C可沉积于第二半导体材料层92B上方。
图12D图示如下实施例：n型区50N中的第一纳米结构52的侧壁及p型区50P中第二纳米结构54的侧壁为凹入的，第一内部间隔物90的外部侧壁为凹入的，且第一内部间隔物90分别自第二纳米结构54及第一纳米结构52的侧壁凹入。如图12D中所图示，磊晶源极/漏极区92可与第一内部间隔物90接触地形成，且可延伸越过n型区50N中的第二纳米结构54的侧壁及p型区50P中第一纳米结构52的侧壁。另外，在第一内部间隔物90自第二纳米结构54及/或第一纳米结构52的侧壁凹入的实施例中，磊晶源极/漏极区92可分别形成于第二纳米结构54及/或第一纳米结构52之间。
在图13A至图13C中，第一层间介电质(interlayer dielectric，ILD)96沉积于图示于图6A、图12B及图12A中的结构上方(图7A至图12D的制程并不变更图6A中图示的横截面)。第一ILD 96可由介电材料形成，且可通过任何合适方法，诸如CVD、电浆增强型CVD(plasma-enhanced CVD，PECVD)或FCVD沉积。介电材料可包括磷硅玻璃(phospho-silicateglass，PSG)、硼硅玻璃(boro-silicate glass，BSG)、硼磷硅玻璃(boron-doped phospho-silicate glass，BPSG)、无掺杂硅玻璃(undoped silicate glass，USG)或类似者。可使用通过任何可接受制程形成的其他绝缘材料。在一些实施例中，触点蚀刻终止层(contactetch stop layer，CESL)94安置于第一ILD 96与磊晶源极/漏极区92、遮罩78及第一间隔物81之间。CESL 94可包含具有不同于上覆第一ILD 96的材料的蚀刻速度的介电材料，诸如氮化硅、氧化硅、氧氮化硅或类似者。
在图14A至图14B中，诸如CMP的平坦化制程可经执行以使第一ILD 96的顶表面与虚设栅极76或遮罩78的顶表面平齐。平坦化制程亦可移除虚设栅极76上的遮罩78，及第一间隔物81沿着遮罩78的侧壁的数个部分。在平坦化制程之后，虚设栅极76、第一间隔物81及第一ILD 96的顶表面在制程变化内为平齐的。因此，虚设栅极72的顶表面经由第一ILD 96暴露。在一些实施例中，遮罩78在平坦化制程使第一ILD 96的顶表面与遮罩78及第一间隔物81的顶表面平齐的状况下可保持。
在图15A及图15B中，虚设栅极72及遮罩78(若存在)在一或多个蚀刻步骤中被移除，使得第二凹槽98被形成。第二凹槽98中虚设介电层60的数个部分亦可被移除。在一些实施例中，虚设栅极72及虚设介电层60通过各向异性干式蚀刻制程来移除。举例而言，蚀刻制程可包括使用反应气体的干式蚀刻制程，反应气体以快于第一ILD 96或第一间隔物81的速度选择性地蚀刻虚设栅极72。每一第二凹槽98暴露及/或上覆纳米结构55的数个部分，该些部分充当后续完成纳米FET的通道区。纳米结构55的充当通道区的数个部分安置于相邻数对磊晶源极/漏极区92之间。在移除期间，当虚设栅极72经蚀刻时，虚设介电层60可用作蚀刻终止层。虚设介电层60可接着在移除虚设栅极72之后被移除。
在图16A及图16B中，为了形成开口130，p型区50P中的第二纳米结构54可通过在n型区50N上方形成遮罩(图中未示)及执行诸如湿式蚀刻的各向同性蚀刻制程或类似者使用对于第二纳米结构54的材料为选择性的蚀刻剂来移除，而第一纳米结构52、基板50、STI区68相较于第二纳米结构54保持相对未蚀刻。在第二纳米结构54包括例如SiGe且第一纳米结构52包括例如Si或SiC的实施例中，氟化氢、另一氟类气体或类似者可用以移除p型区50P中的第二纳米结构54。在移除制程之后，开口130包含第一纳米结构52中每一者之间的区50I。
在其他实施例中，n型区50N及p型区50P中的通道区可例如通过移除n型区50N及p型区50P两者中的第一纳米结构52或通过移除n型区50N及p型区50P两者中的第二纳米结构54而同时形成。在此类实施例中，n型纳米FET及p型纳米FET的通道区可具有相同材料组合物，诸如硅、硅锗或类似者。举例而言，图28A、图28B及图28C图示由如下此类实施例产生的结构：p型区50P及n型区50N两者中的通道区通过第二纳米结构54提供，且包含硅。
在图17A至图24B中，根据一些实施例，栅极介电层100及栅极电极102经形成用于第二凹槽98中的替换栅极结构。栅极介电层100(例如，高k栅极介电层)及栅极电极102(例如，WFM层)分别运用铝及氟进行处置。由于下文更详细论述的铝浸泡及氟浸泡，所得晶体管的平带电压(VFB)可朝向WFM层的金属的带边缘增大，所得晶体管的临限电压可减低，且装置效能可得以改良。
栅极介电层在n型区50N及p型区50P中的形成可同时发生，使得每一区中的栅极介电层由相同材料形成，且栅极电极的形成可同时发生使得每一区中的栅极电极由相同材料形成。在一些实施例中，每一区中的栅极介电层可通过独特制程形成，使得栅极介电层可为不同材料及/或具有不同数目个层，及/或每一区中的栅极电极可通过独特制程形成，使得栅极电极可为不同材料及/或具有不同数目个层。各种遮蔽步骤在使用独特制程时可用以遮蔽且暴露适当区。在以下描述内容中，n型区50N的栅极电极及p型区50P的栅极电极经分离地形成。
图17A至图23D图示在p型区50P中形成栅极介电层100及栅极电极102，且n型区50N至少于在p型区50P中形成栅极电极102同时可经遮蔽。
在图17A及图17B中，栅极介电层100在p型区50P中保形沉积于第二凹槽98中。栅极介电层100包含一或多个介电层，诸如氧化物、金属氧化物、类似者或其组合。举例而言，在一些实施例中，栅极介电层100可包含第一栅极介电层101(例如，包含氧化硅或类似者)及第一栅极介电层101上方的第二栅极介电层103(例如，包含金属氧化物或类似者)。在一些实施例中，第二栅极介电层103括高k介电材料，且在这些实施例中，第二栅极介电层103可具有大于约7.0的k值，且可包括金属氧化物，或铪、铝、锆、镧、锰、钡、钛、铅的硅酸盐及其组合。在一些实施例中，第一栅极介电层101可被称作界面层，且第二栅极介电层103可被称作高k栅极介电层。在一些实施例中，栅极介电层100的形成，诸如第二栅极介电层103的形成可包括在材料中形成孔隙。举例而言，孔隙可为氧化物在沉积之前或之后并不经充分密集的微型孔隙。
栅极介电层100的结构在n型区50N及p型区50P中相同或不同。举例而言，n型区50N可经遮蔽或暴露，同时在p型区50P中形成栅极介电层100。在n型区50N经暴露的实施例中，栅极介电层100可同时形成于n型区50N中。栅极介电层100的形成方法可包括分子束沉积(molecular-beam deposition，MBD)、ALD、PECVD，及类似者。
图18A至图23D图示栅极电极102的一部分(例如，第一导电材料105)运用沉积前处置及沉积后处置在栅极介电层100上方的形成。处置的此组合用来调谐第一导电材料105且改良功能装置的可靠性。
在图18A及图18B中，铝处置109(例如，针对栅极电极102的沉积前处置)施加至第二栅极介电层103。在一些实施例中，铝处置109为使含铝前驱物流动以在第二栅极介电层103的表面上方形成铝的第一残余物111的沉积制程(例如，ALD制程、CVD制程或类似者)。第一残余物111用以经由第一导电材料105(参见图19A及图19B)自后续氟处置(参见图20A及图20B)吸收氟且将氟吸收至栅极介电层100中。第一残余物111大致上保持于栅极介电层100的表面处，使得铝经吸收或通过栅极介电层100的分子部分氧化(例如，第二栅极介电层103)。第一残余物111的铝能够随后通过非氧化或仅部分氧化而吸收氟。
在一些实施例中，在铝处置109期间施加的含铝前驱物可为三乙基铝(triethylaluminum，TEA)(Al2(C2H5)6)、三甲基铝(trimethylaluminum，TMA)(Al(CH3)6)、其组合，或类似者。铝处置109可在范围为约250℃至约550℃的范围内的温度下且历时在约0.5秒至约5分钟或约15秒至约30秒的范围内的持续时间执行。高于550℃的温度及/或长于5分钟的持续时间可导致铝扩散至第二栅极介电层103中且在第二栅极介电层内氧化。低于250℃的温度及/或小于0.5秒的持续时间可导致不足量的铝(例如，不足量的低于残余物111)随后经由第一导电材料105吸收氟且吸收至第二栅极介电层103中。
通过以上述方式执行铝处置109来避免触发还原-氧化反应(或使此反应最小化)，铝处置109并不将连续膜沉积于栅极介电层100上。然而，铝的第一残余物111的离散凹坑可形成于第二栅极介电层103的顶表面上。第一残余物111的每一凹坑可与第一残余物111的其他凹坑断开，且无连续膜形成于栅极介电层100上。第一残余物111可形成于栅极介电层100(例如，第二栅极介电层103)的暴露表面上，包括第一纳米结构52之间的区50I中。在第二栅极介电层103包含高k介电质，诸如HfO2的一些实施例中，区50I中铝与铪的比率可小于0.1，诸如在约0.005与约0.1的范围内，或小于0.005。
在图19A及图19B中，第一导电材料105保形地沉积于p型区50P中的栅极介电层100及第一残余物111上方。在一些实施例中，第一导电材料105为p型WFM，包含氮化钛、氮化钽、氮硅化钛(TiSiN)或类似者。第一导电材料105可通过CVD、ALD、PECVD、PVD或类似者来沉积。在一些实施例中，第一导电材料105运用铝处置109经原位沉积。因此，相同沉积工具可用于两个制程而不需要在不同工具或腔室之间传送。第一导电材料105的原位及迅速沉积的优势为，第一导电材料105的存在防止或大大减小第一残余物111中铝运用栅极介电层100(例如，第二栅极介电层103)的氧化(或其他氧化)。
第一导电材料105可经沉积以包围第一纳米结构52中的每一者。第一导电材料105可仅部分填充区50I。因此，在沉积第一导电材料105之后，开口130可保持于第一纳米结构52之间的区50I中。第一导电材料105具有运用第一残余物的铝的吸收，此情形有助于防止铝扩散至第二栅极介电层103中。因此，运用第二栅极介电层103防止第一残余物氧化或进一步氧化。此外，在形成第一导电材料105之后，在第二栅极介电层103的沉积期间形成于栅极介电层103中的孔隙(例如，微型孔隙)保持未被填充，且无铝。因此，第一残余物111在第二栅极介电层103与第一导电材料105之间的区内保持于铝的断开凹坑中。
在图20A及图20B中，氟处置113施加至第一导电材料105。在一些实施例中，氟处置113为使含氟前驱物在第一导电材料105的表面上方流动的沉积制程(例如，ALD制程、CVD制程或类似者)。在一些实施中，含氟前驱物可为WFx、NFx、TiFx、TaFx、HfFx或类似者，其中x为在1至6的范围内的整数。举例而言，在一些实施例中，含氟前驱物可为WF6及/或NF3。当含氟前驱物到达第一导电材料105时，氟中的一些扩散通过第一导电材料105。第一残余物111通过朝向第一导电材料105、第一残余物111与栅极介电层100(例如，第二栅极介电层103)之间的界面抽汲氟来改良此扩散。一些数量的氟将进一步扩散至栅极介电层100中。如上文所论述，因为防止第一残余物111的铝到达第二栅极介电层103中的孔隙，所以氟能够扩散越过第一残余物111且填充第二栅极介电层103中那些孔隙中的一些。
氟处置113可在约250℃至约475℃的范围内的温度下执行。已观测到，当氟处置113的温度低于250℃时，含氟前驱物并不恰当使第一导电材料105及/或其下伏层游离并影响前述两者之间的所要改变。已观测到，当氟处置113的温度大于475℃时，自含氟前驱物游离的氟的量可能过大而不能精准地控制。在一些实施例中，氟处置113可经执行历时约1秒至约15分钟的范围内，诸如约30秒的持续时间。已观测到，当氟处置113经执行历时小于1秒时，处置制程可能并不足以调谐所得晶体管的临限电压。已观测到，当氟处置113经执行历时大于15分钟时，过量的氟可引入至装置中，从而导致电容等效厚度(capacitanceequivalent thickness，CET)惩罚(例如，界面层101的再生长)。
施加如上文所描述的铝处置109及氟处置113两者可致使第一导电材料105包含约10.8％至约13％以上的氟，诸如在约5％至约25％的范围内的浓度的氟。此外，在第一残余物111的深度处(例如，在第二栅极介电层103与第一导电材料105之间的界面处)，可包含在约0.3％至约10％的范围内的铝。低于约0.3％的铝浓度可不足以吸收足够氟至第二栅极介电层103且保持于第一导电材料105中，借此致使替换栅极结构接收不足电压调谐。高于约10％的铝浓度可引起以下问题中的一或多者。举例而言，高铝浓度可产生禁止氟扩散或移动越过第一残余物111且至第二栅极介电层103中的阻障。此外，高铝浓度可进一步致使例如第二栅极介电层103情况下的增大的铝氧化，其中一些铝可填充第二栅极介电层103中的孔隙(例如，微型孔隙)中的一些或大部分，借此导致如上文所描述的CET惩罚。另外，沿着第一导电材料105的高铝浓度可破坏本文中所描述的替换栅极结构的临限电压的调谐的精度。
在一些实施例中，为了避免触发还原-氧化反应，氟处置113为使用单一化学物质(例如，WF6、NF3或类似者)而无另一化学物质情况下的沉积制程。因此，氟处置113并不将连续膜沉积于第一导电材料105上。然而，在含氟前驱物亦包含金属的实施例中，金属的第二残余物115的离散凹坑可形成于第一导电材料105的顶表面上。可使第二残余物115的每一凹坑自第二残余物115的其他凹坑断开，且无连续膜形成于第一导电材料105上。于在氟处置113期间使用的含氟前驱物为WF6的实施例中，第二前驱物115可为形成于第一导电材料105上的钨残余物。第二残余物115可形成于第一导电材料105的暴露表面上，包括第一纳米结构52之间的区50I中。在第二残余物115为钨残余物且高k栅极介电层103包含HfO2的一些实施例中，区50I中钨与铪的比率可是在约0.001至约0.3的范围内，或小于0.1，诸如小于0.001。已观测到，当区50I中钨与铪的比率大于0.3时，所得装置可能不具有所要临限电压(例如，临限电压可过高)。
在含氟前驱物并不包含金属(例如，含氟前驱物为NF3)的其他实施例中，第二残余物115可能并不形成于第一导电材料105上。举例而言，图29A至图29C图示并不形成第二残余物115且在氟处置113期间使用的含氟前驱物为NF3的实施例。
在一些实施例中，氟处置113可进一步导致至下伏栅极介电层100，诸如高k栅极介电层103中的氟扩散，且氟可运用X射线光电子能谱法分析在高k栅极介电层103中观测到。举例而言，在高k栅极介电层103包含氧化铪的实施例中，高k栅极介电层103中氟与铪的比率由于氟处置113可是在约0.07至约0.4的范围内。已观测到，当高k栅极介电层103中氟与铪的比率小于0.07时，氟的量可能并不足以调谐所得晶体管的临限电压。已观测到，当高k栅极介电层103中氟与铪的比率大于0.4时，过量氟可能已引入至高k栅极介电层103中，从而导致CET惩罚(例如，界面层101的再生长)。在一些实施例中，高k栅极介电层103中氟的量可是在约2.5％至约6％的范围内。
因此，如上文所描述，在对第一导电材料105执行氟处置113的各种实施例中，亦可使氟扩散至下伏栅极介电层(例如，高k栅极介电层)中。因此，所得晶体管的VFB可朝向WFM层的金属的带边缘增大，所得装置的临限电压可减低，且装置效能可得以改良。举例而言，在实验资料中，应用WF6浸泡的实施例氟处置在形成气体退火之后已导致10mV至30mV的金属-氧化物-半导体电容器(metal-oxide-semiconductor capacitor，MOSC)的正有效功函数(effective work function，EFW)移位。
在图21A及图21B中，第二导电材料107保形地沉积于第一导电材料105及第二残余物115(若存在)上。在一些实施例中，第二导电材料107为p型WFM，包含氮化钛、氮化钽、氮化钨、氮化钼或类似者。第二导电材料107可通过CVD、ALD、PECVD、PVD或类似者来沉积。因为第二导电材料107在氟处置113之后沉积，所以第二导电材料107可无氟，或相较于第一导电材料105具有较低氟浓度。
第二导电材料107可填充第一纳米结构52之间的区50I的剩余部分(例如，填充开口130，参见图19A及图19B)。举例而言，第二导电材料107可沉积于第一导电材料105上，直至其合并且缝合在一起，且在一些实施例中，界面107S可通过使第二导电材料107的第一部分107A(例如，导电材料107A)触碰区50I中第二导电材料107的第二部分107B(例如，导电材料107B)形成。
在图22A及图22B中，粘着层117保形沉积于第二导电材料107上方。在一些实施例中，粘着层117保形沉积于p型区50P中的第二导电材料107上。在一些实施例中，粘着层117包含氮化钛、氮化钽或类似者。粘着层117可通过CVD、ALD、PECVD、PVD或类似者来沉积。举例而言，粘着层117可替代地被称作胶层，且改良第二导电材料107与下伏填充金属119之间的粘着。
在图23A、图23B、图23C及图23D中，栅极电极102的剩余部分经沉积以填充第二凹槽98的剩余部分。举例而言，填充金属119可沉积于粘着层117上方。在一些实施例中，填充金属119包含钴、钌、铝、钨、其组合或类似者，该填充金属119通过CVD、ALD、PECVD、PVD或类似者来沉积。所得栅极电极102形成为替换栅极，且可包含第一残余物111、第一导电材料105、第二残余物115(若存在)、第二导电材料107、粘着层117及填充金属119。图23C图示沿着图23B的线X-X’的俯视图(例如，在区50I中)，而图23D图示沿着图23B的线Y-Y’的俯视图(例如，通过第一纳米结构52中的一者)。
在p型区50P中，栅极介电层100、第一导电材料105、第二导电材料107、粘着层117及填充金属119可各自形成于第一纳米结构52的顶表面、侧壁及底表面上。第一残余物111(例如，铝)可在第二栅极介电层103与第一导电材料105之间的界面处形成。第二残余物115可形成于第一导电材料105与第二导电材料107之间的界面处(包括例如氟至一者或两者中的某扩散)，且残余物115的金属元素可不同于第一导电材料105及/或第二导电材料107的金属元素。栅极介电层100、第一导电材料105、残余物115、第二导电材料107、粘着层117及填充金属119亦可沉积于第一ILD 96、CESL 94、第一间隔物81及STI区68的顶表面上。在填充第二凹槽98之后，平坦化制程，诸如CMP可经执行以移除栅极介电层100、第一导电材料105、残余物115、第二导电材料107、粘着层117及填充金属119的过量部分，该些过量部分是在第一ILD 96的顶表面上方。栅极电极102及栅极介电层100的材料的剩余部分因此形成所得纳米FET的替换栅极结构。栅极电极102及栅极介电层100可统称为“栅极结构”。
图24A及图24B图示n型区50N中的栅极堆叠。在n型区50N中形成栅极堆叠可包括首先移除n型区50N中的第一纳米结构52。第一纳米结构52可通过在p型区50P上方形成遮罩(图中未示)及执行诸如湿式蚀刻的各向同性蚀刻制程或类似者使用对于第一纳米结构52的材料为选择性的蚀刻剂来移除，而第二纳米结构54、基板50及STI区68相较于第一纳米结构52保持相对未蚀刻。在第一纳米结构52A至52C包括例如SiGe且第二纳米结构54A至54C包括例如Si或SiC的实施例中，氢氧化四甲铵(tetramethylammonium hydroxide，TMAH)、氢氧化铵(ammonium hydroxide，NH4OH)或类似者可用以移除n型区50N中的第一纳米结构52。
栅极堆叠接着形成于n型区50N中的第二纳米结构54上方且周围。栅极堆叠包括栅极介电层100及栅极电极127。在一些实施例中，n型区50N及p型区50P中的栅极介电层100可同时形成。另外，栅极电极127的至少数个部分可在形成栅极电极102(参见图23A至图23D)之前或之后形成，且栅极电极127的至少数个部分可经形成，同时p型区50P被遮蔽。因此，栅极电极127可包含与栅极电极102不同的材料。举例而言，栅极电极127可包含导电材料121、阻障层123及填充金属125。导电材料121可为n型功函数金属(work function metal，WFM)层，该n型功函数金属层包含n型金属，诸如钛铝、碳化钛铝、钽铝、碳化钽、其组合或类似者。导电材料121可通过CVD、ALD、PECVD、PVD或类似者来沉积。阻障层123可包含氮化钛、氮化钽、碳化钨、其组合或类似者，且阻障层123可进一步充当粘着层。阻障层123可通过CVD、ALD、PECVD、PVD或类似者来沉积。填充金属125可包含钴、钌、铝、钨、其组合或类似者，该填充金属125通过CVD、ALD、PECVD、PVD或类似者来沉积。填充金属125可能或可能不具有相同材料组合物，且与填充金属119同时沉积。
在填充n型区50N中的第二凹槽98之后，平坦化制程，诸如CMP可经执行以移除栅极介电层100及栅极电极127的过量部分，该些过量部分是在第一ILD 96的顶表面上方。栅极电极127及栅极介电层100的材料的剩余部分因此形成n型区50N的所得纳米FET的替换栅极结构。用以移除p型区50P中的栅极电极102的过量材料且移除n型区50N中栅极电极127的过量材料的CMP制程可同时或分离地执行。
在图25A至图25C中，栅极结构(包括栅极介电层100、栅极电极102及栅极电极127)经凹入，使得凹槽直接形成于栅极结构上方且第一间隔物81的相对部分之间。包含介电材料，诸如氮化硅、氧氮化硅或类似者的一或多个层的栅极遮罩104填充于凹槽中，继之以平坦化制程以移除在第一ILD 96上方延伸的介电材料的过量部分。随后形成的栅极触点(诸如下文关于图27A、图27B及图27C论述的栅极触点114)穿透栅极遮罩104以接触经凹入栅极电极102的顶表面。
如通过图25A至图25C进一步图示，第二ILD 106沉积于第一ILD 96上方且栅极遮罩104上方。在一些实施例中，第二ILD 106为通过FCVD形成的可流动膜。在一些实施例中，第二ILD 106由诸如PSG、BSG、BPSG、USG或类似者的介电材料形成，且可通过诸如CVD、PECVD或类似者的任何合适方法来沉积。
在图26A至图26C中，第二ILD 106、第一ILD 96、CESL 94及栅极遮罩104经蚀刻以形成第三凹槽108，该些第三凹槽108暴露磊晶源极/漏极区92及/或栅极结构的表面。第三凹槽108可通过使用各向异性蚀刻制程，诸如RIE、NBE或类似者进行蚀刻来形成。在一些实施例中，第三凹槽108可使用第一蚀刻制程蚀刻穿过第二ILD 106及第一ILD 96；可使用第二蚀刻制程蚀刻穿过栅极遮罩104；且可接着使用第三蚀刻制程蚀刻穿过CESL 94。诸如光阻剂的遮罩可在第二ILD 106上方形成且图案化以遮蔽第二ILD 106的数个部分不受第一蚀刻制程及第二蚀刻制程影响。在一些实施例中，蚀刻制程可过度蚀刻，且因此第三凹槽108延伸至磊晶源极/漏极区92及/或栅极结构中，且第三凹槽108的底部可与磊晶源极/漏极区92及/或栅极结构的顶表面平齐(例如，处于同一位准，或距基板具有相同距离)，或低于该些顶表面(例如，更靠近于基板)。尽管图26B图示第三凹槽108为在同一横截面中暴露磊晶源极/漏极区92及/或栅极结构，但在各种实施例中，磊晶源极/漏极区92及/或栅极结构在不同横截面中可经暴露，借此减小使随后形成的触点短路连接的风险。
在形成了第三凹槽108之后，硅化物区110形成于磊晶源极/漏极区92上方。在一些实施例中，硅化物区110通过以下操作来形成：首先沉积能够与下伏磊晶源极/漏极区92的半导体材料(例如，硅、硅锗、锗)反应的金属(未图示)，诸如镍、钴、钛、钽、铂、钨、其他贵金属、其他耐火金属、稀土金属或其合金于磊晶源极/漏极区92的暴露部分上方，以形成硅化物或锗化物区；接着执行热退火制程以形成硅化物区110。所沉积金属的未经反应部分接着例如通过蚀刻制程来移除。尽管硅化物区110被称作硅化物区，但硅化物区110亦可为锗化物区或硅锗化物区(例如，包含硅化物及锗化物的区)。在实施例中，硅化物区110包含TiSi，且具有范围介于约2nm与约10nm之间的厚度。
接着，在图27A至图27C中，触点112及114(亦可被称作触点插头)形成于第三凹槽108中。触点112及114可各自包含一或多个层，诸如阻障层、扩散层及填充材料。举例而言，在一些实施例中，触点112及触点114各自包括阻障层及导电材料，且各自电耦接至下伏导电特征(例如，在所图示实施例中，栅极电极102、栅极电极127及/或硅化物区110)。触点114电耦接至栅极电极102及127，且可被称作栅极触点，且触点112电耦接至硅化物区110，且可被称作源极/漏极触点。阻障层可包括钛、氮化钛、钽、氮化钽，或类似者。导电材料可为铜、铜合金、银、金、钨、钴、铝、镍或类似者。诸如CMP的平坦化制程可经执行以自第二ILD 106的表面移除过量材料。
图28A、图28B及图28C图示根据一些其他实施例的装置的横截面图。图28A图示在图1中图示的参考横截面A-A’。图28B图示在图1中图示的参考横截面B-B’。图28C图示在图1中图示的参考横截面C-C’。在图28A至图28C中，类似参考数字指示与通过如以上实施例中论述的类似制程形成的元件类似的元件，诸如图27A至图27C的结构。然而，在图28A至图28C中，n型区50N及P型区50P中的通道区包含相同材料。举例而言，包含硅的第二纳米结构54提供n型区50P中p型纳米FET的通道区及n型区50N中n型纳米FET的通道区。图28A至图28C的结构可例如通过以下操作形成：自P型区50P及n型区50N两者移除第一纳米结构52；在p型区50P中的第二纳米结构54周围沉积栅极介电层100及栅极电极102；及在n型区50N中第二纳米结构54周围沉积栅极介电层100及栅极电极102。
图29A至图29E图示根据一些其他实施例的装置的横截面图。图29A图示在图1中图示的参考横截面A-A’。图29B图示在图1中图示的参考横截面B-B’。图29E图示在图1中图示的参考横截面C-C’。在图29A至图29E中，类似参考数字指示与通过如以上实施例中论述的类似制程形成的元件类似的元件，诸如图27A至图27C的结构。然而，在图29A至图29E中，第二残余物115并不形成于第一导电材料105与第二导电材料107之间。举例而言，当氟处置113(参见图20A至图20B)期间使用的含氟前驱物并不含有金属时，此情形可被达成。举例而言，在含氟前驱物为NF3的实施例中，第二残余物115可能并不形成。
各种实施例提供栅极堆叠，该些栅极堆叠具有经铝处置的栅极介电层及经氟处置的功函数金属层。举例而言，铝处置可包括对栅极介电层(例如，高k栅极介电层)执行铝浸泡，且氟处置可包括对WFM层执行氟浸泡。因此，来自氟处置的氟可扩散至WFM中且至下伏栅极介电层中。虽然单独氟处置(例如，在无铝处置情况下)将倾向于将氟抽汲至WFM层及栅极介电层中以达成本文中描述的益处，但铝处置改良这些层中氟的移动及固持。举例而言，铝处置形成铝残余物，该铝残余物经由后续处理通常保持插入于高k栅极介电层与WFM层之间。铝残余物经由WFM层自氟处置吸收氟，且该氟中的一些接着绕过铝残余物以填充高k栅极介电层中的孔隙。处置的组合致使那些层中所要量的氟，借此达成如下益处：所得晶体管的平带电压朝向WFM层的金属的带边缘增大，所得晶体管的临限电压减低，且装置效能得以改良。
在一些实施例中，一种形成栅极结构的方法包括：在一基板上方形成多个纳米结构；蚀刻该些纳米结构以形成第一凹槽；在该些第一凹槽中形成源极/漏极区；移除该些纳米结构中的第一纳米结构，从而留下该些纳米结构中的第二纳米结构；在该些第二纳米结构上方且周围沉积一栅极介电层；对该栅极介电层执行一铝处置；在该栅极介电层上方且周围沉积一第一导电材料；对该第一导电材料执行一氟处置；及在该第一导电材料上方且周围沉积一第二导电材料。在另一实施例中，该执行该铝处置的步骤包含在该栅极介电层上方形成一铝残余物的步骤。在另一实施例中，该执行该氟处置的步骤包含使氟扩散至该第一导电材料中的步骤。在另一实施例中，该执行该氟处置的步骤进一步包含使氟扩散至该栅极介电层中的步骤。在另一实施例中，该执行该氟处置的步骤进一步包含在该第一导电材料上方形成一金属残余物的步骤。在另一实施例中，该第一导电材料包含一p型功函数金属层。在另一实施例中，该执行该铝处置的步骤包含使包含三乙基铝或三甲基铝的一前驱物流动的步骤。在另一实施例中，该执行该氟处置的步骤包含使包含WFx、NFx、TiFx、TaFx或HfFx的一前驱物流动的步骤，且其中x为在1至6的一范围内的一整数。
在一些实施例中，一种栅极结构包括：一第一纳米结构，该第一纳米结构在一源极区与一漏极区之间延伸；该第一纳米结构上方的一第二纳米结构；一栅极介电层，该栅极介电层是在该第一纳米结构及该第二纳米结构上方且周围；该栅极介电层上方的一铝残余物；该栅极介电层及该铝残余物上方的一功函数金属(WFM)层，该WFM层包含氟，该WFM层的一第一部分安置于该第一纳米结构周围，该WFM层的一第二部分安置于该第二纳米结构周围；及一导电层，该导电层安置于该WFM层上方，该导电层的一第一部分安置于该第一纳米结构周围，该导电层的一第二部分安置于该第二纳米结构周围。在另一实施例中，该栅极结构进一步包括一金属残余物，该金属残余物直接插入于该WFM层与该导电层之间。在另一实施例中，该WFM层与该栅极介电层中的每一者包含氟。在另一实施例中，该导电层的该第一部分实体接触该导电层的该第二部分。在另一实施例中，该WFM层为一p型WFM层。在另一实施例中，该栅极介电层包含一第一栅极介电层及一第二栅极介电层。在另一实施例中，插入于该第二栅极介电层与该WFM层之间的一区包含自约0.3％至约10％的一范围内的一浓度的铝。
在一些实施例中，一种晶体管包括：一第一介电材料，该第一介电材料安置于一第一纳米结构上方；一第一金属残余物，该第一金属残余物安置于该第一介电材料上方；一第一导电材料，该第一导电材料安置于该第一介电材料上方；一第二导电材料，该第二导电材料安置于该第一导电材料上方；一第三导电材料，该第三导电材料安置于该第二导电材料上方，该第三导电材料具有与该第一导电材料相同的组合物；一第二金属残余物，该第二金属残余物安置于该第三导电材料上方，该第二金属残余物具有与该第一金属残余物相同的组合物；一第二介电材料，该第二介电材料安置于该第二金属残余物上方，该第二介电材料具有与该第一介电材料相同的组合物；及一第二纳米结构，该第二纳米结构安置于该第二介电材料上方。在另一实施例中，该晶体管进一步包括一第三金属残余物，该第三金属残余物插入于该第一导电材料与该第二导电材料之间；及一第四金属残余物，该第四金属残余物插入于该第二导电材料与该第三导电材料之间，该第四金属残余物具有与该第三金属残余物相同的组合物。在另一实施例中，该第三金属残余物包含钨。在另一实施例中，该第二介电材料、该第一导电材料、该第三导电材料及该第三介电材料中的每一者包含氟。在另一实施例中，该第一金属残余物包含铝。
前述内容概述若干实施例的特征，使得熟悉此项技术者可更佳地理解本揭露的态样。熟悉此项技术者应了解，其可易于使用本揭露作为用于设计或修改用于实施本文中引入的实施例的相同目的及/或达成相同优势的其他制程及结构的基础。熟悉此项技术者亦应认识到，此类等效构造并不偏离本揭露的精神及范畴，且此类等效构造可在本文中进行各种改变、取代及替代而不偏离本揭露的精神及范畴。

Claims (10)

1.一种形成栅极结构的方法，其特征在于，包含以下步骤：
在一基板上方形成多个纳米结构；
蚀刻该些纳米结构以形成第一凹槽；
在该些第一凹槽中形成源极/漏极区；
移除该些纳米结构中的第一纳米结构，从而留下该些纳米结构中的第二纳米结构；
在该些第二纳米结构上方且周围沉积一栅极介电层；
对该栅极介电层执行一铝处置；
在该栅极介电层上方且周围沉积一第一导电材料；
对该第一导电材料执行一氟处置；及
在该第一导电材料上方且周围沉积一第二导电材料。
2.根据权利要求1所述的方法，其特征在于，该执行该铝处置的步骤包含以下步骤：在该栅极介电层上方形成一铝残余物。
3.根据权利要求1所述的方法，其特征在于，该执行该氟处置的步骤包含以下步骤：使氟扩散至该第一导电材料中。
4.根据权利要求3所述的方法，其特征在于，该执行该氟处置的步骤进一步包含以下步骤：使氟扩散至该栅极介电层中。
5.根据权利要求3所述的方法，其特征在于，该执行该氟处置的步骤进一步包含以下步骤：在该第一导电材料上方形成一金属残余物。
6.根据权利要求1所述的方法，其特征在于，该执行该铝处置的步骤包含以下步骤：使包含三乙基铝或三甲基铝的一前驱物流动。
7.一种栅极结构，其特征在于，包含：
一第一纳米结构，该第一纳米结构在一源极区与一漏极区之间延伸；
该第一纳米结构上方的一第二纳米结构；
一栅极介电层，该栅极介电层是在该第一纳米结构及该第二纳米结构上方且周围；
该栅极介电层上方的一铝残余物；
该栅极介电层及该铝残余物上方的一功函数金属层，该功函数金属层包含氟，该功函数金属层的一第一部分安置于该第一纳米结构周围，该功函数金属层的一第二部分安置于该第二纳米结构周围；及
一导电层，该导电层安置于该功函数金属层上方，该导电层的一第一部分安置于该第一纳米结构周围，该导电层的一第二部分安置于该第二纳米结构周围。
8.根据权利要求7所述的栅极结构，其特征在于，进一步包含一金属残余物，该金属残余物直接插入于该功函数金属层与该导电层之间。
9.一种晶体管，其特征在于，包含：
一第一介电材料，该第一介电材料安置于一第一纳米结构上方；
一第一金属残余物，该第一金属残余物安置于该第一介电材料上方；
一第一导电材料，该第一导电材料安置于该第一介电材料上方；
一第二导电材料，该第二导电材料安置于该第一导电材料上方；
一第三导电材料，该第三导电材料安置于该第二导电材料上方，该第三导电材料具有与该第一导电材料相同的组合物；
一第二金属残余物，该第二金属残余物安置于该第三导电材料上方，该第二金属残余物具有与该第一金属残余物相同的组合物；
一第二介电材料，该第二介电材料安置于该第二金属残余物上方，该第二介电材料具有与该第一介电材料相同的组合物；及
一第二纳米结构，该第二纳米结构安置于该第二介电材料上方。
10.根据权利要求9所述的晶体管，其特征在于，进一步包含：
一第三金属残余物，该第三金属残余物插入于该第一导电材料与该第二导电材料之间；及
一第四金属残余物，该第四金属残余物插入于该第二导电材料与该第三导电材料之间，该第四金属残余物具有与该第三金属残余物相同的组合物。
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