CN114690841A - Reference current generating circuit and analog integrated circuit system - Google Patents

Reference current generating circuit and analog integrated circuit system Download PDF

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Publication number
CN114690841A
CN114690841A CN202011576427.8A CN202011576427A CN114690841A CN 114690841 A CN114690841 A CN 114690841A CN 202011576427 A CN202011576427 A CN 202011576427A CN 114690841 A CN114690841 A CN 114690841A
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transistor
circuit
coupled
reference current
pmos
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丁利强
蔡小五
曹硕
郝宁
高马利
夏瑞瑞
高悦欣
罗家俊
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

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Abstract

The invention discloses a reference current generating circuit, comprising: the circuit comprises a starting circuit and a core circuit, wherein the core circuit comprises a current mirror module and a reference current generation module with a cross-coupling structure; the reference current generation module with the cross-coupling structure comprises a first transistor, a second transistor, a third transistor, a fourth transistor and a first resistor, wherein the base of the first transistor is coupled with the collector of the second transistor and the emitter of the fourth transistor, the base of the second transistor is coupled with the collector of the first transistor and the emitter of the third transistor, the emitter of the first transistor is grounded, the emitter of the second transistor is grounded through the first resistor, the emitter areas of the first transistor and the fourth transistor are equal, and the emitter areas of the second transistor and the third transistor are equal.

Description

Reference current generating circuit and analog integrated circuit system
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a reference current generating circuit and an analog integrated circuit system.
Background
In analog integrated circuits, the reference current source is the reference source that provides high precision, low temperature coefficient bias current for other circuits, which is an essential part of many analog and digital-analog hybrid integrated circuits. In order to ensure that the system circuit works normally, the reference current source circuit needs to provide stable and accurate bias current for the whole system circuit, and the precision of the reference current source directly influences the characteristics of the circuit of the whole system, such as power consumption, PSRR (voltage rejection ratio), temperature and the like. High performance analog circuits must be supported by high quality, high stability current and voltage bias circuits. Therefore, designing a high-precision reference dianliu source in practical applications becomes a major concern for designers.
Disclosure of Invention
The embodiment of the application provides a reference current generating circuit and an analog integrated circuit system, and the cross-coupled transistor structure is adopted, so that the problem of current mismatch caused by asymmetry of a current mirror is solved, the output current is more accurate, and the temperature drift coefficient of a reference current source is greatly reduced.
In a first aspect, the present invention provides the following technical solutions through an embodiment of the present invention:
a reference current generating circuit comprising: the circuit comprises a starting circuit and a core circuit, wherein the core circuit comprises a current mirror module and a reference current generation module with a cross coupling structure, the current mirror module is coupled with the output end of the starting circuit, and the reference current generation module with the cross coupling structure is coupled with the output end of the current mirror module; the starting circuit is used for starting the core circuit to enable the core circuit to be separated from a zero-current working state and enter a normal working state; the current mirror module is used for outputting mirror current, and the reference current generating module with the cross-coupling structure is used for generating reference current; the reference current generation module with the cross-coupling structure comprises a first transistor, a second transistor, a third transistor, a fourth transistor and a first resistor, wherein the base of the first transistor is coupled with the collector of the second transistor and the emitter of the fourth transistor, the base of the second transistor is coupled with the collector of the first transistor and the emitter of the third transistor, the emitter of the first transistor is grounded, the emitter of the second transistor is grounded through the first resistor, and the base of the third transistor is coupled with the base of the fourth transistor and the collector of the fourth transistor, wherein the emitter areas of the first transistor and the fourth transistor are equal, and the emitter areas of the second transistor and the third transistor are equal.
Preferably, the first transistor, the second transistor, the third transistor, and the fourth transistor are all triodes.
Preferably, the core circuit further includes: the input end of the bias module is coupled with the starting circuit, the output end of the bias module is coupled with the collector electrode of the third transistor through the filter module, the bias module is used for providing a bias voltage for the current mirror module to normally work, and the filter module is used for filtering the voltage input to the collector electrode of the third transistor.
Preferably, the filtering module includes: the capacitor is connected with the resistor in series, the capacitor is grounded, and the resistor is coupled with the output end of the bias module.
Preferably, the emitter junction area of the second transistor is n times of the emitter junction area of the first transistor, and the emitter junction area of the third transistor is n times of the emitter junction area of the fourth transistor, where n is an integer greater than or equal to 1.
Preferably, the current mirror module includes a first PMOS transistor and a second PMOS transistor, gates of the first PMOS transistor and the second PMOS transistor are both coupled to the output terminal of the start-up circuit, sources of the first PMOS transistor and the second PMOS transistor are both coupled to a power supply voltage, a drain of the first PMOS transistor is coupled to a collector of the fourth transistor, and a drain of the second PMOS transistor is coupled to a collector of the third transistor.
Preferably, the start-up circuit includes: the source electrodes of the first NMOS tube, the second NMOS tube and the third NMOS tube are all grounded, the grid electrodes of the first NMOS tube and the second NMOS tube are coupled with the drain electrode of the second NMOS tube, the drain electrode of the fourth PMOS tube is coupled with the drain electrode of the second NMOS tube, the drain electrode of the first NMOS tube and the grid electrode of the third NMOS tube are coupled with the drain electrode of the fifth PMOS tube, the grid electrode of the fifth PMOS tube is coupled with an enabling end, the source electrodes of the fourth PMOS tube and the fifth PMOS tube are coupled with a power supply, the drain electrode of the third NMOS tube is coupled with the grid electrode of the fourth PMOS tube, and the grid electrode of the fourth PMOS tube is the output end of the starting circuit.
Preferably, when the first NMOS transistor is turned on, the third NMOS transistor will be in an off state.
Preferably, the reference current generating circuit is applied to an analog integrated circuit system of 3.3V or more.
In a second aspect, the present invention provides the following technical solutions through an embodiment of the present invention:
an analog integrated circuit system comprising the reference current generation circuit described in the first aspect.
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:
in the reference current generating circuit provided in an embodiment of the present invention, a core circuit is additionally provided with a reference current generating module with a cross-coupled structure, where the reference current generating module with a cross-coupled structure includes: the transistor comprises a first transistor, a second transistor, a third transistor, a fourth transistor and a first resistor; a base of the first transistor is coupled with a collector of the second transistor and an emitter of the fourth transistor; a base of the second transistor is coupled to a collector of the first transistor and an emitter of the third transistor; the emitter of the first transistor is grounded, the emitter of the second transistor is grounded through a first resistor, and the base of the third transistor is coupled with the base of the fourth transistor and the collector of the fourth transistor; wherein emitter areas of the first transistor and the fourth transistor are equal, and emitter areas of the second transistor and the third transistor are equal. The circuit can compensate mismatch caused by asymmetry of the current mirror module, so that the problem of current mismatch caused by asymmetry of the current mirror is solved, output current is more accurate, and the temperature drift coefficient of the reference current source is greatly reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
FIG. 1 is a circuit diagram of a reference current generating circuit according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a core circuit according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of a first exemplary reference current source according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of a second exemplary reference current source according to an embodiment of the present invention;
FIG. 5 is a circuit diagram of a third exemplary reference current source according to an embodiment of the present invention;
FIG. 6 is a block diagram of an analog integrated circuit system according to an embodiment of the present invention.
Detailed Description
The embodiment of the application provides a reference current generating circuit and an analog integrated circuit system, and the cross-coupled transistor structure is adopted, so that the problem of current mismatch caused by asymmetry of a current mirror is solved, the output current is more accurate, and the temperature drift coefficient of a reference current source is greatly reduced.
In the description of the present invention, it should also be noted that the term "coupled" means a connection relationship, such as: there may be an electrical connection of the two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a reference current generating circuit, as shown in fig. 1, including: the circuit comprises a starting circuit 10 and a core circuit 20, wherein the core circuit 20 comprises a reference current generating module and a current mirror module with a cross-coupling structure, and besides, the core circuit 20 also comprises a biasing module and a filtering module.
As an alternative embodiment, as shown in fig. 1, the core circuit 20 may include a reference current generating module with a cross-coupling structure and a current mirror module, where the current mirror module is coupled to the output terminal of the start-up circuit, and the reference current generating module with a cross-coupling structure is coupled to the output terminal of the current mirror module.
Specifically, the reference current generation module with the cross-coupled structure includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a first resistor. The base of the first transistor is coupled with the collector of the second transistor and the emitter of the fourth transistor, the base of the second transistor is coupled with the collector of the first transistor and the emitter of the third transistor, the emitter of the first transistor is grounded, the emitter of the second transistor is grounded through the first resistor, and the base of the third transistor is coupled with the base of the fourth transistor and the collector of the fourth transistor.
The transistor mentioned in the reference current generating module with the cross-coupled structure may be a triode, or may be a field effect transistor, such as a junction field effect transistor or a metal-oxide semiconductor field effect transistor, and the field effect transistor is referred to as a MOS transistor for short. That is, the bases, collectors, and emitters of the first transistor, the second transistor, the third transistor, and the fourth transistor mentioned above may represent the base, emitter, and collector of a triode, and may also correspond to the gate (base), drain (collector), and source (emitter) of a field effect transistor.
Specifically, when the transistors included in the reference current generating module with the cross-coupling structure are triodes, the reference current generating module with the cross-coupling structure includes a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4 and a first resistor R1, a base of the first transistor Q1 is coupled to a collector of the second transistor Q2 and an emitter of the fourth transistor Q4, a base of the second transistor Q2 is coupled to a collector of the first transistor Q1 and an emitter of the third transistor Q3, an emitter of the first transistor Q1 is grounded, an emitter of the second transistor Q2 is grounded via the first resistor R1, and a base of the third transistor Q3 is coupled to a base of the fourth transistor Q4 and a collector of the fourth transistor Q4. Therefore, through a cross coupling mode, mismatch is eliminated, and the voltage difference between the voltage flowing into the first resistor R1 from the second transistor Q2 and the voltage flowing into the first resistor R1 from the first transistor Q1 does not have the mismatch problem caused by asymmetry of the current mirror. In order to satisfy the situation that the emitter junction areas are not equal due to the fact that the number of transistors is different in different reference current generation circuits, the emitter areas of the first transistor Q1 and the fourth transistor Q4 are equal, and the emitter areas of the second transistor Q2 and the third transistor Q3 are equal.
The emitter areas of the first transistor Q1 and the fourth transistor Q4 are equal and the emitter areas of the second transistor Q2 and the third transistor Q3 are equal. It is understood that the emitter area of the second transistor Q2 is n times larger than the emitter areas of the first transistor Q1 and the fourth transistor Q4, and the emitter area of the third transistor Q3 is n times larger than the emitter areas of the first transistor Q1 and the fourth transistor Q4, where n is an integer greater than or equal to 1.
As an alternative embodiment, as shown in fig. 1, the current mirror module of the core circuit 20 may include a first PMOS transistor MP1 and a second PMOS transistor MP2, and the sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both coupled to the power supply voltage to provide the power supply voltage for the circuit. The gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both used as input terminals and coupled to the output terminal of the start-up circuit 10, wherein, in order to satisfy that the reference current output by the reference current generating circuit does not change with the change of the power supply voltage VDD, the first PMOS transistor MP1 and the second PMOS transistor MP2 form a current mirror, and the reference current generated by the first PMOS transistor MP1 and the output current generated by the second PMOS transistor MP2 are mirror currents, so that the current is not affected by the power supply voltage.
The drain of the first PMOS transistor MP1 is coupled to the collector of the fourth transistor Q4, and the drain of the second PMOS transistor MP2 is coupled to the collector of the third transistor Q3. When the current mirror module is controlled by the starting circuit 10, the mirror current with the same current is output, and the reference current is generated by the reference current generating module with the cross-coupling structure. The bases of the fourth transistor Q4 and the third transistor Q3 are coupled to the collector of the fourth transistor Q4. One end of the first resistor R1 is coupled to the emitter of the second transistor Q2, and the other end of the first resistor R1 is grounded. The reference current generation module with the cross-coupled structure includes a voltage difference between a voltage of a base-emitter of the third transistor Q3 and a voltage of a base-emitter of the fourth transistor Q4 as a voltage of the first resistor R1. When the core circuit 20 enters a normal operation state, the current flowing through the first resistor R1 is a reference current.
Further, in order to provide the current mirror module with a bias voltage for normal operation. As shown in fig. 2, the core circuit 20 may further include a bias module having an input coupled to the start-up circuit and an output coupled to the collector of the third transistor Q3 through a filter module. The filtering module is coupled to the base of the fifth transistor Q5 and to ground. For filtering the voltage inputted to the collector of the third transistor Q3.
Specifically, the bias module may include a fifth transistor Q5 and a third PMOS transistor MP3, wherein a gate of the third PMOS transistor MP3 is coupled to the output terminal of the start-up circuit, and a source of the third PMOS transistor MP3 is coupled to the power supply voltage. The collector of the fifth transistor Q5 and the drain of the third PMOS transistor MP3 are both coupled to the gate of the third PMOS transistor MP3, and the voltage at the collector of the fifth transistor Q5 will be used as the reference voltage. The emitter of the fifth transistor Q5 is grounded, and the base of the fifth transistor Q5 is coupled to the drain of the second PMOS transistor MP2 and the collector of the third transistor Q3, respectively.
Specifically, the filter circuit may be a capacitor C1 and a second resistor R2 connected in series, the capacitor C1 is grounded, and the second resistor R2 is coupled to the base of the fifth transistor Q5. The filter circuit can stabilize the voltage at the base of the fifth transistor Q5, and the change of the voltage at the collector will be small after the voltage at the collector and the base of the fifth transistor Q5 are stabilized. When the voltage at the collector of the fifth transistor Q5 stabilizes, the reference voltage in the core circuit 20 will stabilize, further stabilizing the bias current of the system.
It should be noted that the core circuit 20 provided in this embodiment is a reference current source with a three-branch structure, and a negative feedback loop can be formed by the third branch formed by the third PMOS transistor MP3 and the fifth transistor Q5, and the original branch. Specifically, when the power supply voltage VDD increases, the voltage V1 at the drain of the third PMOS transistor MP3 increases, and the first PMOS transistor is regarded as a common source, so that the voltage V2 at the collector of the second transistor Q2 decreases, the voltage V3 at the collector of the first transistor Q1 increases under the action of the first transistor Q1, and the voltage V1 decreases under the action of the fifth transistor Q5. Thus, a negative feedback loop from V1 to V2 to V3 to V1 is formed. Further, the voltage at the collector of the fifth transistor Q5 is stabilized, the power supply rejection ratio of the reference current is increased, and when the power supply rejection ratio of the entire system becomes high, the variation of the output reference current with the power supply voltage is reduced.
Of course, in other embodiments of the present invention, as shown in fig. 2, the core circuit 20 may include: a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a first resistor R1, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, and a filter circuit, wherein a gate of the first NMOS transistor MN1 is coupled to a drain of the second NMOS transistor MN2 and a source of the fourth NMOS transistor MN4, a gate of the second NMOS transistor MN2 is coupled to a drain of the first NMOS transistor MN2 and a source of the third NMOS transistor MN3, a source of the first NMOS transistor MN1 is grounded, a source of the second NMOS transistor MN1 is grounded via the first resistor R1, a gate of the third NMOS transistor MN1 is coupled to a gate of the fourth NMOS transistor MN1 and a source of the fourth NMOS transistor MN1, a drain of the third NMOS transistor MN1 is coupled to a drain of the first PMOS transistor MP1, a drain of the fourth NMOS transistor MN1 is coupled to a drain of the first PMOS transistor MN1, a drain of the fourth NMOS transistor MN1 is coupled to a drain of the second PMOS transistor MN1, a drain of the second NMOS transistor MP1 is coupled to a gate of the PMOS transistor MN1, and a gate of the second PMOS transistor MP1, and a gate of the second PMOS transistor MP1, and a gate of the PMOS transistor MP1 are coupled to the PMOS transistor MP 68510, and a start-up circuit.
The sources of the first PMOS transistor MP1, the second PMOS transistor MP2 and the third PMOS transistor MP3 are coupled to a power supply voltage VDD, the drain of the third PMOS transistor MP3 and the gate of the third PMOS transistor MP3 are coupled to the drain of a fifth NMOS transistor MN5, the gate of the fifth NMOS transistor MN5 and the drain of the third NMOS transistor MN3 are coupled, and the source of the fifth NMOS transistor MN5 is grounded. The filter circuit comprises a second resistor R2 and a capacitor C1 which are connected in series, wherein the second resistor R2 is coupled with the gate of the fifth NMOS transistor MN5, and the capacitor is coupled with the source of the fifth NMOS transistor MN 5.
It will be appreciated that in analog integrated circuits, the reference current source is the reference source that provides high precision, low temperature coefficient bias current for other circuits, which is an essential part of many analog and digital-analog hybrid integrated circuits. In order to ensure that the system circuit works normally, the reference current source circuit needs to provide stable and accurate bias current for the whole system circuit, and the precision of the reference current source directly affects the characteristics of the circuit of the whole system, such as power consumption, PSRR (current rejection ratio), temperature and the like. High performance analog circuits must be supported by high quality, high stability current and voltage bias circuits. Therefore, designing a high-precision reference source in practical applications becomes a major concern for designers.
The design of the current source is based on a "copy" of the reference current, provided that an accurate current source is available. This current source needs to have two characteristics:
1. the output current is less affected by supply voltage variations (i.e., there is a higher PSRR);
2. the output current is not affected by temperature changes (remains constant over a range of temperatures).
As shown in fig. 3, a conventional reference source circuit structure composed of BJT transistors (full-name: bipolar junction transistors) based on the thermodynamic temperature VT is disclosed, and the current generated on the resistor R by the difference between the base-emitter voltages of the two transistors Q1 and Q2 is used as the reference current. The expression of the reference current is:
Figure BDA0002864200070000091
wherein VT is about 28mV of voltage at thermodynamic temperature, and K is the ratio of Q2 to Q1. It can be seen from equation (1) that the current is substantially independent of temperature.
Fig. 4 is a conventional reference source circuit structure composed of BJT based on thermodynamic temperature VT. The reference current source is composed of MOS tubes, and uses the current generated on R by the difference between the gate-source voltages of MN1 and MN2 as the reference current. When MN1 and MN2 operate in the subthreshold region, the reference current expression is:
Figure BDA0002864200070000092
where ζ is the sub-threshold non-ideality factor and K is the number ratio of MN2 to MN 1.
When MN1 and MN2 operate in the saturation region, the reference current expression is:
Figure BDA0002864200070000101
wherein munFor the carrier mobility, it decreases with increasing temperature and is greatly influenced by temperatureCox is the capacitance of the gate oxide layer in unit area, and W/L is the width-to-length ratio of the MOS tube. The formulas (2) and (3) show that the current source formed by the MOS tube is adopted, and when MN1 and MN2 work in a saturation region, the reference current is greatly influenced by temperature; when the device is operated in a subthreshold interval, the reference current is basically independent of temperature. However, the two conventional structures have obvious defects that the reference current is greatly influenced by the change of the power supply voltage, namely, the power supply rejection ratio is relatively low, and the reference current formed by the MOS transistor is greatly influenced by the temperature when the MOS transistor works in a saturation region, and is not suitable for being applied to an actual circuit system.
In another reference current source circuit shown in fig. 5, although a branch is added, negative feedback is formed (collector of feedback loop Q2-collector of MP 2-collector of MP 1-collector of MP 3-collector of Q3), and the power supply rejection ratio of the reference current is further improved. However, the temperature drift coefficient of the reference current source is still large, and is still greatly influenced by temperature change, and the resistance with different temperature coefficients needs to be additionally added for compensation, so that a more appropriate temperature drift coefficient can be obtained. And thus do not meet the needs of high performance analog integrated circuit systems.
In view of the above, the present invention provides a reference current source circuit with high precision and high power supply rejection ratio.
Specifically, when the core circuit does not introduce a cross-coupling structure, the mismatch value I is due to a certain mismatch between the currents in the first and second asymmetric PMOS transistors MP1 and MP2 of the current mirror1＝I2(1+ Δ). Resulting in a difference Δ V between the voltages of the base-emitter voltage of the third transistor Q3 and the base-emitter voltage of the fourth transistor Q4BEWill no longer be VTln n is instead
Figure BDA0002864200070000102
The reference current becomes
Figure BDA0002864200070000103
Rather than to
Figure BDA0002864200070000104
The present embodiment is described in detailAnd a cross coupling structure is introduced, so that the mismatching of the quasi current in the mirror image process is reduced, the current copying precision is improved, and the precision of the reference current source can be improved.
For example, as shown in FIG. 1, assume that the currents in Q1, Q2, Q3, Q4 are IC1、IC2、IC3、IC4The emitter area is S1、S2、S3、S4And S is2＝nS1，S3＝nS4，S1＝S4Base-emitter voltages of VBE1、VBE2、VBE3、VBE4. Wherein, IC1＝IC3，IC2＝IC4The design reference current is as follows:
Figure BDA0002864200070000111
from equation (4), it is clear that the current mismatch due to the asymmetry of the current mirror is substantially eliminated, resulting in a more accurately controllable reference current source.
As an alternative embodiment, the starting circuit 10 is used to start the core circuit 20, so that the core circuit 20 is out of the zero-current operating state and enters the normal operating state. The start-up circuit 10 may include: a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth PMOS transistor MP4, and a fifth PMOS transistor MP 5. The sources of the first NMOS transistor MN1, the second NMOS transistor MN2, and the third NMOS transistor MN3 are all grounded. The sources of the fourth PMOS transistor MP4 and the fifth PMOS transistor MP5 are both coupled to a power supply voltage, the drain of the first NMOS transistor MN1 and the gate of the third NMOS transistor MN3 are both coupled to the drain of the fifth PMOS transistor MP5, and the gate of the fifth PMOS transistor MP5 is coupled to the enable terminal EN. After the circuit is powered on, the enable end EN is active at a low level, the fifth PMOS transistor MP5 connected to the enable end is turned on, so that the third NMOS transistor MP3 is turned on, and once the third NMOS transistor is turned on, the MP1, the MP2, the MP3, and the MP4 in the core circuit start to operate. The reference current source is separated from the zero current working state instantly and enters a normal and stable working state, and the current reference source starts to work.
The gates of the first and second NMOS transistors MN1 and MN2 and the drain of the fourth PMOS transistor MP4 are coupled to the drain of the second NMOS transistor MN 2. The fourth PMOS transistor MP4 copies the currents of the transistors MP1, MP2, MP3 and MP4, the current of the second transistor Q2 is equal to the current of the fourth PMOS transistor MP4, the first NMOS transistor MN1 copies the current of the second NMOS transistor MN2 and turns on, and once the first NMOS transistor MN1 turns on, the third NMOS transistor MN3 in the start-up circuit 10 turns off when the reference current source normally operates because the reference current source does not satisfy the turn-on voltage, so that the circuit does not generate extra power consumption. The drain of the third NMOS transistor MN3 is coupled to the gate of the fourth PMOS transistor MP4, and the gate of the fourth PMOS transistor MP4 is the output terminal of the start-up circuit 10. After the third NMOS transistor MN3 is turned on, the gate voltage of the fourth PMOS transistor MP4 is pulled low instantly, so that the MP1, the MP2, the MP3, and the MP4 are turned on due to the voltage difference between the drain and the gate, and the core circuit starts to supply power after the third NMOS transistor MN3 is turned on.
Of course, as another alternative embodiment, the starting circuit may have another circuit structure, and the circuit with the structure only needs to be capable of making the reference current source deviate from the zero-current operating state and enter the normal stable operating state.
The reference current generating circuit provided by the embodiment can be applied to an analog integrated circuit system with more than 3.3V, and can provide a reference current with higher precision for a system circuit.
In an exemplary embodiment, the reference current generating circuit provided by the present embodiment may include a start-up circuit and a core circuit, where the core circuit includes a reference current generating module and a current mirror module with a cross-coupled structure. VDD and GND are respectively a power supply terminal and a ground terminal, EN is an enabling terminal, and the enabling terminal EN is enabled to be effective in low level. MN1, MN2, MN3, MP4 and MP5 form a starting circuit of the reference current source; MP1, MP2, MP3, Q1, Q2, Q3, Q4, Q5, R1, R2, and C1 constitute a core circuit.
Specifically, after the circuit is powered on, the EN end is given a low level, at this time, the MP5 transistor is turned on to pull the drain voltage high, so that the MN3 transistor is turned on, and the MN3 transistor is turned on to pull the gate potentials of MP1, MP2, MP3, and MP4 low at the instant, so that the reference current source is instantaneously separated from the zero-current working state, and enters a normal and stable working state, and the current reference source starts to work. At this time, a stable reference current is generated at R1, since MP4 copies the reference current, the current in MN2 is equal to the current in MP4, MN1 copies the current in MN2 and turns on, and once MN1 turns on, the drain potential of MN1 will be pulled down to a low potential, which makes MN3 in the start-up circuit turn off when the reference current source is working normally, and no extra power consumption is generated.
The reference current generation circuit with the cross coupling structure is adopted, the problem of current mismatch in MP1 and MP2 tubes caused by asymmetry of a current mirror is solved, and output current is more accurate. Further, according to the principle that the stability of the reference current affects the temperature drift coefficient, the temperature drift coefficient of the reference current is relatively small, namely the reference current with good stability can keep relatively stable in a large temperature change range without adding a temperature compensation circuit, and has a low temperature drift coefficient.
Specifically, the formula of the temperature drift coefficient is as follows:
Figure BDA0002864200070000131
wherein, TCThe temperature drift coefficient of a reference current source is expressed in ppm/DEG C; i isMAXIs the maximum value of the reference current and has the unit of A; I.C. AMINIs the minimum value of the reference current and has the unit of A; i isMEANThe average value of the reference current is A; t isMAXIs the maximum temperature in units of ℃; t isMINIs the minimum temperature in degrees Celsius.
As can be seen from equation (5), the better the stability of the reference current, the smaller the value of the temperature drift coefficient will be.
In summary, the reference current generation circuit provided by the embodiment of the invention adopts the cross-coupled transistor structure, so that the current mismatch problem caused by the asymmetry of the current mirror is solved, the output current is more accurate, and the temperature drift coefficient of the reference current source is greatly reduced. The reference current circuit can be applied to an analog system circuit with large working temperature change, and can provide the reference current with high precision and good stability for the system circuit.
Based on the same inventive concept, the present embodiment provides an analog integrated circuit system 60, as shown in fig. 6, including: the bulk circuit 602 and the reference current generating circuit 601 provided in the foregoing embodiments. The reference current generating circuit 601 is connected to the body circuit 602, and is used for providing a reference current for the body circuit 602. The specific structure and implementation principle of the reference current generating circuit 601 have been described in the foregoing embodiments, and are not described herein again. The bulk circuit 602 may include various devices that need to provide a reference current, such as an operational amplifier, an a/D converter, etc., which are not described in detail herein.
The implementation principle and the generated technical effect of the analog integrated circuit system provided by the embodiment of the present invention are the same as those of the foregoing method embodiment, and for the sake of brief description, no mention is made in the system embodiment, and reference may be made to the corresponding contents in the foregoing circuit embodiment.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including the preferred embodiment and all changes and modifications that fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (10)

1. A reference current generating circuit, comprising: the circuit comprises a starting circuit and a core circuit, wherein the core circuit comprises a current mirror module and a reference current generation module with a cross coupling structure, the current mirror module is coupled with the output end of the starting circuit, and the reference current generation module with the cross coupling structure is coupled with the output end of the current mirror module;
the starting circuit is used for starting the core circuit, so that the core circuit is separated from a zero current working state and enters a normal working state;
the current mirror module is used for outputting mirror current, and the reference current generation module with the cross coupling structure is used for generating reference current;
the reference current generation module with the cross-coupled structure comprises a first transistor, a second transistor, a third transistor, a fourth transistor and a first resistor, wherein the base of the first transistor is coupled with the collector of the second transistor and the emitter of the fourth transistor, the base of the second transistor is coupled with the collector of the first transistor and the emitter of the third transistor, the emitter of the first transistor is grounded, the emitter of the second transistor is grounded through the first resistor, and the base of the third transistor is coupled with the base of the fourth transistor and the collector of the fourth transistor, wherein the emitter areas of the first transistor and the fourth transistor are equal, and the emitter areas of the second transistor and the third transistor are equal.
2. The circuit of claim 1, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are all triodes.
3. The circuit of claim 2, wherein the core circuit further comprises: the input end of the bias module is coupled with the starting circuit, the output end of the bias module is coupled with the collector electrode of the third transistor through the filter module, the bias module is used for providing a bias voltage for the current mirror module to normally work, and the filter module is used for filtering the voltage input to the collector electrode of the third transistor.
4. The circuit of claim 3, wherein the filtering module comprises: the capacitor is connected with the resistor in series, the capacitor is grounded, and the resistor is coupled with the output end of the bias module.
5. The circuit of claim 2, wherein the emitter area of the second transistor is n times the emitter area of the first transistor, wherein the emitter area of the third transistor is n times the emitter area of the fourth transistor, and wherein n is an integer greater than or equal to 1.
6. The circuit of claim 2, wherein the current mirror module comprises a first PMOS transistor and a second PMOS transistor, gates of the first PMOS transistor and the second PMOS transistor are both coupled to the output of the start-up circuit, sources of the first PMOS transistor and the second PMOS transistor are both coupled to a supply voltage, a drain of the first PMOS transistor is coupled to a collector of the fourth transistor, and a drain of the second PMOS transistor is coupled to a collector of the third transistor.
7. The circuit of claim 1, wherein the startup circuit comprises: the power supply circuit comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth PMOS tube and a fifth PMOS tube, wherein the source electrodes of the first NMOS tube, the second NMOS tube and the third NMOS tube are all grounded, the grid electrodes of the first NMOS tube and the second NMOS tube are coupled with the drain electrode of the second NMOS tube, the drain electrode of the fourth PMOS tube is coupled with the drain electrode of the second NMOS tube, the drain electrode of the first NMOS tube and the grid electrode of the third NMOS tube are coupled with the drain electrode of the fifth PMOS tube, the grid electrode of the fifth PMOS tube is coupled with an enabling end, the source electrodes of the fourth PMOS tube and the fifth PMOS tube are coupled with a power supply, the drain electrode of the third NMOS tube is coupled with the grid electrode of the fourth PMOS tube, and the grid electrode of the fourth PMOS tube is the output end of the starting circuit.
8. The circuit of claim 7, wherein when the first NMOS transistor is turned on, the third NMOS transistor is turned off.
9. The circuit of claim 1, wherein the reference current generating circuit is applied in an analog integrated circuit system of 3.3V or more.
10. An analog integrated circuit system comprising the reference current generating circuit of any one of claims 1 to 9.
CN202011576427.8A 2020-12-28 2020-12-28 Reference current generating circuit and analog integrated circuit system Pending CN114690841A (en)

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CN202011576427.8A CN114690841A (en) 2020-12-28 2020-12-28 Reference current generating circuit and analog integrated circuit system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011576427.8A CN114690841A (en) 2020-12-28 2020-12-28 Reference current generating circuit and analog integrated circuit system

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CN114690841A true CN114690841A (en) 2022-07-01

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