CN114690611A - Time-to-digital converter with low power consumption and conversion method - Google Patents
Time-to-digital converter with low power consumption and conversion method Download PDFInfo
- Publication number
- CN114690611A CN114690611A CN202210390526.XA CN202210390526A CN114690611A CN 114690611 A CN114690611 A CN 114690611A CN 202210390526 A CN202210390526 A CN 202210390526A CN 114690611 A CN114690611 A CN 114690611A
- Authority
- CN
- China
- Prior art keywords
- delay
- digital converter
- time
- signal
- stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
Abstract
The invention discloses a time-to-digital converter with low power consumption and a conversion method, wherein the time-to-digital converter comprises: the device comprises a power consumption management module, a two-stage time-to-digital converter and a decoder module. The power consumption management module is used for gating the input signals of the two-stage time-to-digital converter so as to reduce power consumption; the two-stage time converter measures the phase difference of the reference signal and the feedback signal; the decoder converts the sampling values of the two-stage time-to-digital converter into binary codes. The invention has simple structure and design, does not destroy the stability of the original system, and has the advantages of low power consumption, large dynamic range and high resolution.
Description
Technical Field
The present invention relates to integrated circuit design, and more particularly, to a time-to-digital converter with low power consumption and a conversion method thereof.
Background
A time-to-digital converter is a device that converts a time interval into a digital signal and can be used to measure the phase difference between two input signals. The core indicators of a time-to-digital converter are resolution, dynamic range and power consumption, and the traditional time-to-digital converter focuses on solving the contradiction that the resolution and the dynamic range cannot be completely satisfied.
Chinese patent: CN 113098482A, 2021.07.09 (reference 1) discloses a time-to-digital converter with low power consumption and a conversion method thereof, as shown in fig. 1, the conversion method of the time-to-digital converter is as follows: carrying out lead-lag judgment on input signals at two edges, firstly starting an annular slow delay chain, and counting the number of turns of one bit output SDx of the annular slow delay chain; then the ring-shaped fast delay chain is started, and one bit output FDx of the ring-shaped fast delay chain is counted; edge fdx (k) captures voltage state qx (k) of node edge sdx (k) by a D flip-flop. The data reading module sequentially and circularly captures data Qx (k) of each node, and when Qn (k) is not equal to Q1(1), cursor residual quantity (ts-tf) n NFlap + (ts-tf) Ddec + (1-Q1 (1)). 0.5n ts is obtained; outputting STOP signals to turn off two annular delay chains, and keeping the turn number information NSlap and NFlap at the moment by a turn number counting module; the structure doubles the traditional conversion speed of the vernier annular TDC and has high resolution, but the vernier annular TDC has too many delay units, large power consumption and large area, and a plurality of delay units with different delays are difficult to control.
Chinese patent: CN113949378A, 2020.07.15 (reference 2) discloses a time-to-digital converter with small area and low power consumption. This patent includes a ring oscillator and a margin generation circuit. Each stage of the headroom generation circuit is configured to operate on the output of two different stages of the ring oscillator. The patent also includes a counter for counting a number of times that the output of one of the stages of the ring oscillator switch is between the first signal level and the second signal level during the period of time that is converted to the digital value. The TDC includes a combiner for generating a digital value by combining a value indicating the number of times counted by the counter with an output of the margin generation circuit. Although this structure has the advantages of low power consumption and small area, it cannot guarantee high resolution and wide dynamic range.
Chinese patent: CN113917831A, 2022.01.11 (reference 3) discloses a low power consumption high resolution time-to-digital converter, which is a two-step n-level cascade structure, the first step structure includes a first level to an n/2 level cascade structure, the second step structure includes an n/2+1 level to an n level cascade structure, the first step structure and the second step structure are connected through an amplifier TA; each stage of cascade structure comprises 2 digital time converters DTC, namely a first digital time converter and a second digital time converter, and 1D trigger DFF; each digital-to-time converter includes an input terminal, an output terminal, and n/2 digital control start voltage input pins. The structure has the advantages of low power consumption and high resolution, but does not have wide dynamic range, and the structure needs full-custom design and has low reusability.
To overcome these problems, it is necessary to design a time-to-digital converter with low power consumption, wide dynamic range and high resolution.
Disclosure of Invention
The purpose of the invention is as follows: the invention provides a time-to-digital converter with low power consumption and a conversion method aiming at the problems in the prior art, in particular to the power consumption of the time-to-digital converter.
The technical scheme is as follows: the invention relates to a low-power-consumption time-to-digital converter, which comprises a power consumption management module, a two-stage time-to-digital converter and a decoder, wherein the two-stage time-to-digital converter is connected with the power consumption management module; the two-stage time-to-digital converter is respectively connected with the power consumption management module and the decoder;
the power consumption management module is used for generating gating delay signals of a first stage and a second stage of the two-stage time-to-digital converter, the two gating delay signals are input into the two-stage time-to-digital converter, the two-stage time-to-digital converter samples and outputs a phase difference between a first-stage gating delay signal Q1< m-1:0> and a reference signal, a phase difference between a second-stage gating delay signal and the reference signal Q2< n-1:0>, a signal CKD and a signal FREF _ D, and the signal CKD and the signal FREF _ D are input into the power consumption management module for generating the second-stage gating delay signal; the decoder converts the output phase difference of the two-stage time-to-digital converter into binary number as the final conversion output, generates a selection signal and inputs the selection signal to the two-stage time-to-digital converter.
Furthermore, the power consumption management module comprises a counter, a D trigger, an exclusive-OR gate and three AND gates; the concrete connection mode is as follows: the counter, the first AND gate, the D trigger and the second AND gate are connected in sequence; the output end of the exclusive-OR gate is connected with the third AND gate;
the feedback signal CKV is used as a clock signal of a counter and a D trigger, the FREF is used as a reset signal RST of the counter, output signals Q [1] and Q [3] of the counter output signals pass through a first AND GATE to output a signal GATE, the signal GATE is connected with an enable end EN of the counter and a D end of the D trigger, the GATE obtains a synchronous signal after sampling at a rising edge of the CKV, the synchronous signal passes through a second AND GATE to finally generate an output CKV _ G of a power consumption management module, and the CKV _ G is a first-level gating delay signal.
The reference signal FREF is connected with the reset of the counter and the input of the exclusive-OR gate, the FREF _ D and the FREF are output to a third AND gate through the exclusive-OR gate, the other end of the third AND gate inputs a signal CKD, finally the third AND gate generates a CKD _ G, and the CKD _ G is a second-stage gating delay signal
Further, the two-stage time-to-digital converter comprises a delay chain time-to-digital converter, a gating module and a vernier caliper time-to-digital converter. The time delay chain time-to-digital converter is connected with the gating module; CKV _ G and FREF are input into a time delay chain time-to-digital converter, a gating module selects CKD to a power consumption management module, CKD _ G generated by the power consumption management module is input into a vernier caliper time-to-digital converter, and the output Q1< m-1:0> and Q2< n-1:0> of the two-stage time-to-digital converter are input into a decoder.
The delay chain time-to-digital converter comprises a first delay chain and a sampling unit, wherein the first delay chain comprises m stages of delay units with the delay of tau 1 connected in series; the first-stage gating delay signal is input into a first delay chain time-to-digital converter, and a delay unit of the delay chain time-to-digital converter correspondingly outputs E [ i ] which serves as the input of an m-selected-1 selector, wherein i is 0, … and m-1; the output end of each delay unit is connected with one sampling unit, the reference signal FREF is connected with the other input end of the sampling unit, and the sampling unit outputs the phase difference Q1< m-1:0> between the first-level gating clock signal and the reference signal;
the gating module is an m-to-1 selector, the selection information output by the E [ i ] and decoder (300) is used as an input signal of the m-to-1 selector (202), and the m-to-1 selector outputs a signal CKD to a third AND gate of the power consumption management module;
the vernier caliper time-to-digital converter comprises a second delay chain, a third delay chain and a sampling unit, wherein the second delay chain comprises n stages of delay units with delay of tau which are connected in series, and the third delay chain comprises n stages of delay units with delay of tau 3 and a delay unit with delay of tau 4 which are connected in series; the sampling unit is connected between the delay unit with the delay time of tau 2 and the delay unit with the delay time of tau 3. The first-level gating clock signal CKD _ G is input into a second delay chain, the reference signal FREF is input into a third delay chain, and the sampling unit outputs the phase difference Q2 between the second-level gating delay signal and the reference signal, wherein the phase difference Q2 is m-1: 0%; the third delay chain outputs a signal FREF _ D to an exclusive or gate of the power management module.
Furthermore, the sampling unit is a double-ended input and single-ended output D trigger.
Further, the delay unit includes two inverters.
Further, the delay of the delay unit satisfies:
n*τ3+τ4＞n*τ2 (2)
furthermore, the decoder is a temperature decoder and comprises m stages of full adder circuits which are connected in sequence.
A low-power time-to-digital conversion method comprises the following steps:
specifically, the power consumption control module generates two window signals GATE and GATE _ F, the two window signals comprise a first-stage window signal and a second-stage window signal of the two-stage time-to-digital converter, and modulates a first-stage delay signal CKV and a second-stage delay signal CKD of the two-stage time-to-digital converter according to the two window signals to obtain a gated first-stage signal CKV _ G and a gated second-stage signal CKD _ G.
and 3, converting the sampling signal into a high-precision binary code by the decoder, and inputting the signal CKD into the power consumption management module for generating a second-level gating signal.
Has the beneficial effects that: compared with the prior art, the invention has the following remarkable advantages: on the basis of the two-stage time-to-digital converter, the power consumption management module is added, so that the power consumption of the two-stage time-to-digital converter is obviously reduced, the advantages of wide range and high resolution of the two-stage time-to-digital converter are still ensured, the two-stage time-to-digital converter is slightly changed and is simple to realize, and the power consumption management module can be comprehensively generated by codes, has better portability for different processes and is more beneficial to integration.
Drawings
Fig. 1 is a structural diagram of a time-to-digital converter proposed in reference 1;
FIG. 2 is a block diagram of a time-to-digital converter provided by the present invention;
FIG. 3 is a block diagram of a two-stage time-to-digital converter;
fig. 4 is a block diagram of a decoder.
The figure shows that: a power consumption management module 100, a two-stage time-to-digital converter 200, a decoder 300;
a counter 101, a first and gate 102, a D flip-flop 103, a second and gate 104, an exclusive or gate 105, and a third and gate 106;
a delay chain time-to-digital converter 201, an m-to-1 selector 202, a vernier caliper time-to-digital converter 203, a first delay chain 204, a second delay chain 205, and a third delay chain 206.
Detailed Description
The technical solution of the present invention will be described in detail with reference to examples.
The present example provides a time-to-digital converter with low power consumption, as shown in fig. 2, including a power management module 100, a two-stage time-to-digital converter 200, and a decoder 300.
The power consumption management module is composed of a counter 101, a first and gate 102, a D flip-flop 103, a second and gate 104, an exclusive or gate 105, and a third and gate 106. When the counter counts to M (10 is taken as an example in the present application), the GATE signal GATE is output through the first and GATE 102, and the GATE signal is synchronously output by the D flip-flop 103 to reduce the glitch of the logic circuit, and the output of the D flip-flop 103 and the CKV output the gated CKV _ G signal through the second and GATE 104. The outputs of FREF _ D and FREF from the two-stage time-to-digital converter are connected to the input of a third and gate 106 through the output of an xor gate 105, CKD is used as the input of the third and gate, and the output of the third and gate is a second gating clock CKD _ G.
Wherein, the value of M in the counter should satisfy:
m in the formula (1) is the maximum value of the counting required by the counter, TCKVIs the period of the clock signal CKV of the counter, TFREFIs the period of the reference signal FREF, TDL1Is the total delay, T, of the first stage delay chain DL1 in the two-stage time-to-digital convertersetupIs the setup time of the D flip-flop.
As shown in fig. 3, the two-stage time-to-digital converter is composed of a delay chain time-to-digital converter 201, an m-to-1 selector 202, and a vernier caliper time-to-digital converter 203. The delay chain time-to-digital converter 201 is composed of a first delay chain 204 and m sampling units, the first delay chain 204 is composed of m delay units with time delay of τ 1 connected in series, and the sampling units are double-end input single-end output D triggers. The vernier caliper time-to-digital converter 208 is composed of a second delay chain 205, a third delay chain 206 and n sampling units, the second delay chain 204 is composed of n delay units with time delay of τ 2 in series, the third delay chain 206 is composed of n-1 delay units with time delay of τ 3 and a D trigger with time delay of τ 4 in series, and the sampling units are double-end input and single-end output D triggers. In the first delay chain 204, E [ i ] (i ═ 0, …, m-1) is generated from the CKV _ G input as the input of the m-to-1 selector 202, and the output CKD of the selector 202 is input to the power consumption management module to generate the gated clock CKD _ G. CKD _ G is input to the second delay chain 205 and FREF is input to the third delay chain 206 to generate a delayed FREF _ D. Wherein the delay of the delay unit should satisfy:
n*τ3+τ4＞n*τ2 (2)
the value of τ 3 can be set by the above equation (2).
Wherein, as shown in fig. 4, the decoder 300 is composed of a cascade of full adders. The first-stage gating delay signal Q1< m-1:0> is used as the input of a decoder, Q1< m-1:0> is sequentially used as the input of a full adder, the summation result S and the carry result CO of the full adder are output, the full adder is connected according to the S and the CO to output the summation result S and the carry result CO of the second stage, and the multiple stages are sequentially analogized to finally output a selection signal SEL.
The invention also provides a low-power-consumption time-to-digital conversion method, which comprises the following steps:
(1) the power consumption management module is adopted to convert the signals of the two-stage time-to-digital converter into gating signals, so that the delay chain of the two-stage time-to-digital converter only works in a small range. The method specifically comprises the following steps:
(1.1) the CKV is used as a clock signal of the counter, the counting is stopped when the count reaches a specific value, the count is reset again when the rising edge of the FREF, the value of the counter is converted into a GATE signal GATE through the first AND GATE 102, when the GATE is at a high level, the counter locks a count value, the GATE is synchronized with the CKV through the D flip-flop 103, the method can eliminate the glitch of combinational logic, and the gated CKV _ G is generated by a signal synchronized with the D flip-flop and the CKV through the second AND GATE 104.
(1.2) the signal generated by the exclusive-or gate 105 passing the FREF and the FREF _ D signal passing through the third delay chain 206 and CKD pass through the third and gate to generate CKD _ G.
(2) The gated clock is sampled by two-stage time-to-digital converter to obtain Q1< m-1:0> and Q2< n-1:0>, and the final output of the whole time-to-digital converter is obtained through a decoder.
In the embodiment, on the basis of the two-stage time-to-digital converter, the power consumption management module is added, so that the power consumption of the two-stage time-to-digital converter is reduced. The advantages of wide range and high resolution of the two-stage time-to-digital converter are reserved, the power consumption of the two-stage time-to-digital converter is reduced, the two-stage time-to-digital converter is slightly changed, the implementation is simple, the power consumption management module can be comprehensively generated by codes, and the power consumption management module has better portability for different processes and is more beneficial to integration.
In conclusion, the invention not only has the advantages of high resolution and wide dynamic range of the two-stage time-to-digital converter, but also solves the problem of higher power consumption of the two-stage time-to-digital converter, and the power consumption management module can be comprehensively realized through codes, has higher reusability, has smaller influence on the stability of the whole system, and has good application prospect.
Claims (10)
1. A time-to-digital converter with low power consumption, characterized by comprising a power management module (100), a two-stage time-to-digital converter (200) and a decoder (300);
the two-stage time-to-digital converter (200) is respectively connected with the power consumption management module (100) and the decoder (300);
the power consumption management module (100) is used for generating first-level and second-level gating delay signals and inputting the first-level and second-level gating delay signals into a two-level time-to-digital converter, the two-level time-to-digital converter calculates and outputs a phase difference between a first-level gating clock signal and a reference signal, a phase difference between a second-level gating delay signal and the reference signal, a signal CKD and a signal FREF _ D, and the signal CKD and the signal FREF _ D are input into the power consumption management module (100) and used for generating the second-level gating delay signals;
the decoder converts the output phase difference of the two-stage time-to-digital converter into binary number as the final conversion output, generates a selection signal and inputs the selection signal to the two-stage time-to-digital converter.
2. A low-power consumption time-to-digital converter according to claim 1, characterized in that said power management module (100) comprises a counter (101), a D flip-flop (103), an exclusive or gate (105) and three and gates;
the concrete connection mode is as follows: the counter (101), the first AND gate (102), the D trigger (103) and the second AND gate (104) are connected in sequence; the output end of the exclusive-OR gate (105) is connected with a third AND gate (106);
CKV is used as clock signals of a counter (101) and a D flip-flop (103), signals Q [1] and Q [3] output by the counter (101) output a signal GATE through a first AND GATE (102), the signal GATE is connected with an enabling end of the counter (101) and a D end of the D flip-flop (103), and the output of the D flip-flop (103) and the CKV generate a first-stage gating delay signal CKV _ G through a second AND GATE (104);
the reference signal FREF is connected with the reset of the counter (101) and the input of the exclusive-OR gate, FREF _ D and FREF are output to a third AND gate (106) through the exclusive-OR gate (105), the other end of the third AND gate (106) is input with a signal CKD, and the third AND gate (106) generates a second-stage gating delay signal CKD _ G.
3. A low power consumption time-to-digital converter according to claim 1 or 2, characterized in that said two-stage time-to-digital converter (200) comprises a delay chain time-to-digital converter (201), a gating module (202) and a vernier caliper time-to-digital converter.
The time delay chain time-to-digital converter (201) is connected with the gating module;
the delay chain time-to-digital converter comprises a first delay chain (204) and a sampling unit, wherein the first delay chain comprises m stages of delay units with the delay of tau 1 connected in series; the first-stage gating delay signal is input into a first delay chain (204) of a first delay chain time-to-digital converter (201), and a delay unit corresponding to an output E [ i ] of the first delay chain (204) is used as an input of a gating module (202), wherein i is 0, …, m-1;
the output end of each delay unit is connected with one sampling unit, the reference signal FREF is connected with the other input end of the sampling unit, and the sampling unit outputs the phase difference Q1< m-1:0> between the first-level gating clock signal and the reference signal;
the gating module is an m-to-1 selector (202), selection information output by the E [ i ] and decoder (300) serves as an input signal of the m-to-1 selector (202), and the m-to-1 selector (202) outputs a signal CKD to a third AND gate (106) of the power consumption management module (100);
the vernier caliper time-to-digital converter (203) comprises a second delay chain (205), a third delay chain (206) and a sampling unit, wherein the second delay chain (205) comprises n stages of delay units with the delay of tau 2 connected in series, and the third delay chain comprises n stages of delay units with the delay of tau 3 connected in series with one delay unit with the delay of tau 4; the sampling unit is connected between the delay unit with the delay of tau 2 and the delay unit with the delay of tau 3;
the first-stage gating delay signal CKD _ G is input into a second delay chain (205), the reference signal FREFF is input into a third delay chain (206), and the sampling unit outputs the phase difference Q2< n-1:0> between the second-stage gating clock signal and the reference signal; the third delay chain (206) outputs a signal FREF _ D to an exclusive or gate (105) of the power management module.
4. A low power consumption time-to-digital converter as claimed in claim 3, wherein the value of M in the counter satisfies:
m in the formula (1) is the maximum value of the counting required by the counter, TCKVIs the period of the clock signal CKV of the counter, TFREFIs the period of the reference signal FREF, TDL1Is the total delay, T, of the first delay chain DL1 in the two-stage time-to-digital convertersetupIs the setup time of the D flip-flop.
5. The time-to-digital converter with low power consumption of claim 3, wherein the sampling unit is a double-ended input and single-ended output D flip-flop.
6. A low power consumption time-to-digital converter as claimed in claim 3, wherein the delay unit comprises two inverters.
7. A low-power consumption time-to-digital converter as claimed in claim 3, wherein the delay of the delay unit is such that:
n*τ3+τ4＞n*τ2 (2)
8. a low power consumption time-to-digital converter as claimed in claim 1, characterized in that said decoder (300) is a temperature decoder comprising m stages of sequentially connected full-adder circuits.
9. A time-to-digital conversion method with low power consumption, characterized in that it is based on a time-to-digital converter according to claim 1, comprising the following steps:
step 1, generating gating signals of a first stage and a second stage in a two-stage time-to-digital converter by adopting a power consumption management module;
step 2, respectively inputting the generated first-stage and second-stage gate control signals into two-stage delay chains of a two-stage time-to-digital converter, acquiring a sampling signal and a signal CKD by the two-stage time-to-digital converter through a reference signal and the gate control signals,
and 3, converting the sampling signal into a high-precision binary code by the decoder, and inputting the signal CKD into the power consumption management module for generating a second-level gating signal.
10. The method according to claim 9, wherein the step 1 comprises the power consumption control module generating two window signals GATE and GATE _ F including a first-stage window signal and a second-stage window signal of the two-stage time-to-digital converter, and modulating the first-stage delay signal CKV and the second-stage delay signal CKD of the two-stage time-to-digital converter according to the two window signals to obtain the gated first-stage signal CKV _ G and the gated second-stage signal CKD _ G.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210390526.XA CN114690611A (en) | 2022-04-14 | 2022-04-14 | Time-to-digital converter with low power consumption and conversion method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210390526.XA CN114690611A (en) | 2022-04-14 | 2022-04-14 | Time-to-digital converter with low power consumption and conversion method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114690611A true CN114690611A (en) | 2022-07-01 |
Family
ID=82142939
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210390526.XA Pending CN114690611A (en) | 2022-04-14 | 2022-04-14 | Time-to-digital converter with low power consumption and conversion method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114690611A (en) |
-
2022
- 2022-04-14 CN CN202210390526.XA patent/CN114690611A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Hwang et al. | A high-precision time-to-digital converter using a two-level conversion scheme | |
| CN109143832B (en) | High-precision multichannel time-to-digital converter | |
| US8325076B2 (en) | Time-to-digital converter | |
| CN207518571U (en) | Analog-digital converter | |
| US9007133B2 (en) | Oscillator, time-digital converter circuit and relating method of time-digital measure | |
| CN102082573A (en) | Analog to digital conversion circuit and method | |
| JP2011023887A (en) | A/d converter and solid-state imaging device with the same | |
| KR20170053990A (en) | Latch circuit, double data rate ring counter based the latch circuit, hybrid counting apparatus, analog-digital converting apparatus, and cmos image sensor | |
| KR101503732B1 (en) | Time to digital converter | |
| CN112838851A (en) | Residual time sampling circuit based on differential sampling and time-to-digital converter | |
| JP6594420B2 (en) | Time-to-digital converter and digital phase-locked loop | |
| CN102055476B (en) | Pipeline time digital converter | |
| CN113917830B (en) | Cyclic vernier delay chain circuit, time-to-digital converter and signal selection method | |
| CN110824889B (en) | Time-to-digital converter based on novel time amplifier | |
| CN114967411B (en) | Multi-stage time-to-digital converter with automatic reset mechanism | |
| CN114690611A (en) | Time-to-digital converter with low power consumption and conversion method | |
| US9793914B2 (en) | Analog-to-digital converter, electronic device, and method of controlling analog-to-digital converter | |
| CN114374809B (en) | Analog-to-digital conversion circuit of infrared focal plane reading circuit | |
| WO2019210642A1 (en) | Novel time-to-digital converter | |
| CN214480526U (en) | Residual time sampling circuit based on differential sampling and time-to-digital converter | |
| CN115933352A (en) | Low-power-consumption time-to-digital converter circuit based on delayed multi-sampling | |
| JP5273149B2 (en) | Digital phase comparator and method | |
| CN110212912A (en) | A kind of multiple delay phase-locked loop with High-precision time-to-digital converter | |
| Fathi et al. | A sar adc based time-to-digital converter in cmos technology | |
| Bezdenezhnykh et al. | Design and IC implementation of a fully digital power management delay-line ADC |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |