CN114679181A

CN114679181A - Digital-to-analog converter and comparison circuit for voltage superposition

Info

Publication number: CN114679181A
Application number: CN202210205003.3A
Authority: CN
Inventors: 袁冰; 薛晓磊
Original assignee: Tuoer Microelectronics Co ltd
Current assignee: Tuoer Microelectronics Co ltd
Priority date: 2022-03-02
Filing date: 2022-03-02
Publication date: 2022-06-28
Anticipated expiration: 2042-03-02
Also published as: CN114679181B

Abstract

The application is suitable for the power electronics field, provides a digital-to-analog converter and comparison circuit for voltage stack's digital-to-analog converter includes first current cell, second current cell and voltage stack unit, first current cell is used for being connected with first voltage source electricity, second current cell is used for ground connection, first current cell voltage stack unit with second current cell concatenates in proper order. The digital-to-analog converter for voltage superposition provided by the embodiment of the application can solve the problem that the existing digital-to-analog converter can not directly superpose the analog output voltage converted by binary coding with the known voltage.

Description

Digital-to-analog converter and comparison circuit for voltage superposition

Technical Field

The application belongs to the technical field of power electronics, and particularly relates to a digital-to-analog converter and a comparison circuit for voltage superposition.

Background

The existing digital-to-analog converter generally takes the ground in a circuit as a voltage reference point, the analog output voltage converted by the binary code is the voltage relative to the ground, and the analog output voltage converted by the binary code cannot be directly superposed with the known voltage.

Disclosure of Invention

The embodiment of the application provides a digital-to-analog converter for voltage superposition, which can solve the problem that the existing digital-to-analog converter cannot directly superpose the analog output voltage converted by binary coding with the known voltage.

In a first aspect, an embodiment of the present application provides a digital-to-analog converter for voltage superposition, including a first current unit, a second current unit, and a voltage superposition unit, where the first current unit is used to be electrically connected to a first voltage source, the second current unit is used to be grounded, and the first current unit, the voltage superposition unit, and the second current unit are sequentially connected in series;

the first current unit is used for receiving a target digital signal, providing a target current signal according to the target digital signal, and controlling the target current signal to be loaded at a first loading point or a second loading point in the voltage superposition unit;

the second current unit is used for receiving the target digital signal, providing the target current signal according to the target digital signal, and controlling the target current signal to be loaded at a second loading point or a first loading point in the voltage superposition unit;

When a target current signal provided by the first current unit is loaded at a first loading point in the voltage superposition unit and a target current signal provided by the second current unit is loaded at a second loading point in the voltage superposition unit, the flow direction of the target current signal in the voltage superposition unit is a first direction; when a target current signal provided by the first current unit is loaded at a second loading point in the voltage superposition unit and a target current signal provided by the second current unit is loaded at a first loading point in the voltage superposition unit, the flow direction of the target current signal in the voltage superposition unit is a second direction; the first direction and the second direction are opposite;

the voltage superposition unit is used for receiving a target voltage signal, superposing the target voltage signal and the first voltage signal and outputting an analog voltage signal; the first voltage signal is generated by the voltage superposition unit according to the target current signal.

In a possible implementation manner of the first aspect, the first current unit includes a first current input circuit, a first current source circuit, a first switch circuit, and a first commutation circuit; the first current source circuit and the first current input circuit are both used for being electrically connected with the first voltage source, the first current input circuit is electrically connected with the first current source circuit, the first switch circuit is respectively electrically connected with the first current source circuit and the first reversing circuit, and the first reversing circuit is respectively electrically connected with a first loading point and a second loading point on the voltage superposition unit;

The first current input circuit is used for providing a first input current for the first current source circuit;

the first current source circuit is used for providing N-1 reference current signals according to the first input current;

the first switch circuit is used for selecting M reference current signals from the N-1 reference current signals according to the target digital signal to form the target current signal; wherein N is an integer of 2 or more, M is more than or equal to 0 and less than or equal to N-1, and M is an integer;

the first commutation circuit is used for controlling the target current signal to be loaded on a first loading point or a second loading point in the voltage superposition unit according to the target digital signal.

In one possible implementation manner of the first aspect, the first current source circuit comprises N-1 first current sources, the first switch circuit comprises N-1 first switches, and the first commutation circuit comprises a first gating switch; the N-1 first current sources are electrically connected with the first current input circuit, the anodes of the N-1 first current sources are used for being electrically connected with the first voltage source, the cathodes of the N-1 first current sources are electrically connected with the first ends of the N-1 first switches in a one-to-one correspondence manner, the second ends of the N-1 first switches are electrically connected with the first end of the first gating switch, the second end of the first gating switch is electrically connected with a first loading point on the voltage superposition unit, and the third end of the first gating switch is electrically connected with a second loading point on the voltage superposition unit;

The reference currents provided by the N-1 first current sources are respectively 2^N-2I，2^N-3I, …, 2I, I, wherein N is an integer greater than or equal to 2, and I is the first current input powerA first input current provided by the circuit; the control end of the N-1 first switches is used for receiving N-1 data bits in the target digital signal, and the N-1 data bits are B in sequence_N-2，B_N-3，…，B₁，B₀The data bit is used for indicating that the corresponding first switch is switched on or off; the control end of the first gating switch is used for receiving a sign bit in the target digital signal, and the sign bit is B_N-1And the sign bit is used for indicating the first gating switch to load the target current signal on a first load point or a second load point in the voltage superposition unit.

In a possible implementation manner of the first aspect, the first current input circuit includes an operational amplifier, a first resistor, a second resistor, a first NMOS transistor, a first PMOS transistor, and a second PMOS transistor;

the non-inverting input end of the operational amplifier is used for receiving a reference voltage, the inverting input end of the operational amplifier is respectively and electrically connected with the first end of the first resistor and the source electrode of the first NMOS tube, the second end of the first resistor is grounded, and the output end of the operational amplifier is electrically connected with the grid electrode of the first NMOS tube; the drain electrode of the first NMOS tube is electrically connected with the first end of the second resistor, the grid electrode of the second PMOS tube and the N-1 first current sources respectively; the second end of the second resistor is electrically connected with the drain electrode of the second PMOS tube, the grid electrode of the first PMOS tube and the N-1 first current sources respectively; the source electrode of the second PMOS tube is electrically connected with the drain electrode of the first PMOS tube, and the source electrode of the first PMOS tube is used for being electrically connected with the first voltage source.

In a possible implementation manner of the first aspect, each of the first current sources includes a fifth PMOS transistor and a sixth PMOS transistor; each first switch comprises an eighth NMOS transistor;

the source electrode of the fifth PMOS tube is used for being electrically connected with the first voltage source, the gate electrode of the fifth PMOS tube is electrically connected with the second end of the second resistor, the drain electrode of the fifth PMOS tube is electrically connected with the source electrode of the sixth PMOS tube, the gate electrode of the sixth PMOS tube is electrically connected with the drain electrode of the first NMOS tube, the drain electrode of the sixth PMOS tube is electrically connected with the drain electrode of the eighth NMOS tube, the gate electrode of the eighth NMOS tube is used for receiving one data bit in the target digital signal, and the source electrode of the eighth NMOS tube is electrically connected with the first end of the first gating switch;

the branch circuit formed by the first PMOS tube and the second PMOS tube and the branch circuits formed by the N-1 fifth PMOS tubes and the sixth PMOS tubes form a cascode first current mirror, and the proportion of the first current mirror is 1: 2^N-2：2^N ^-3：……：2：1；

The first gating switch comprises an inverter, a fourth NMOS tube and a fifth NMOS tube;

the input end of the phase inverter is used for receiving a sign bit in the target digital signal, the input end of the phase inverter is electrically connected with the gate of the fifth NMOS transistor, the output end of the phase inverter is electrically connected with the gate of the fourth NMOS transistor, the drain of the fourth NMOS transistor is electrically connected with the drain of the fifth NMOS transistor and the source of the eighth NMOS transistor respectively, the source of the fourth NMOS transistor is electrically connected with the first loading point of the voltage superposition unit, and the source of the fifth NMOS transistor is electrically connected with the second loading point of the voltage superposition unit.

In a possible implementation manner of the first aspect, the second current unit includes a second current input circuit, a second current source circuit, a second switch circuit, and a second commutation circuit; the second current input circuit is used for being electrically connected with the first voltage source, and the second current source circuit is used for being grounded; the second current input circuit is electrically connected with the second current source circuit, the second switch circuit is electrically connected with the second current source circuit and the second reversing circuit respectively, and the second reversing circuit is electrically connected with a first load point and a second load point on the voltage superposition unit respectively;

the second current input circuit is used for providing a second input current for the second current source circuit;

the second current source circuit is used for providing N-1 reference current signals according to the second input current;

the second switch circuit is used for selecting M reference current signals from the N-1 reference current signals according to the target digital signal to form the target current signal; wherein N is an integer greater than or equal to 2, M is greater than or equal to 0 and less than or equal to N-1, and M is an integer;

the second commutation circuit is used for controlling the target current signal to be loaded on a second loading point or a first loading point in the voltage superposition unit according to the target digital signal.

In one possible implementation manner of the first aspect, the second current source circuit comprises N-1 second current sources, the second switch circuit comprises N-1 second switches, and the second commutation circuit comprises a second gating switch; the N-1 second current sources are electrically connected with the second current input circuit, anodes of the N-1 second current sources are electrically connected with first ends of the N-1 second switches in a one-to-one correspondence manner, cathodes of the N-1 second current sources are grounded, second ends of the N-1 second switches are electrically connected with first ends of the second gating switches, second ends of the second gating switches are electrically connected with a first loading point on the voltage superposition unit, and third ends of the second gating switches are electrically connected with a second loading point on the voltage superposition unit;

the reference currents of the N-1 second current sources are respectively 2^N-2I，2^N-3I, …, 2I, I, wherein N is an integer greater than or equal to 2, and I is a second input current provided by the second current input circuit;

the control ends of the N-1 second switches are used for receiving N-1 data bits in the target digital signal, and the data bits are used for indicating the corresponding second switches to be switched on or switched off; the control end of the second gating switch is used for receiving a sign bit in the target digital signal, and the sign bit is used for instructing the second gating switch to load the target current signal on a second load point or a first load point in the voltage superposition unit;

The second current input circuit comprises a third PMOS tube, a fourth PMOS tube, a third NMOS tube, a second NMOS tube and a third resistor;

the source electrode of the third PMOS tube is used for being electrically connected with the first voltage source, the grid electrode of the third PMOS tube is electrically connected with the second end of the second resistor, the drain electrode of the third PMOS tube is electrically connected with the source electrode of the fourth PMOS tube, the grid electrode of the fourth PMOS tube is electrically connected with the first end of the second resistor, the drain electrode of the fourth PMOS tube is electrically connected with the first end of the third resistor and the grid electrode of the third NMOS tube respectively, the second end of the third resistor is electrically connected with the drain electrode of the third NMOS tube and the grid electrode of the second NMOS tube respectively, the source electrode of the third NMOS tube is electrically connected with the drain electrode of the second NMOS tube, the source electrode of the second NMOS tube is grounded, and the grid electrode of the third NMOS tube and the grid electrode of the second NMOS tube are both electrically connected with the N-1 second current sources;

the branch composed of the third PMOS tube and the fourth PMOS tube and the branch composed of the first PMOS tube and the second PMOS tube form a cascode second current mirror, and the proportion of the second current mirror is 1: 1.

In a possible implementation manner of the first aspect, each second current source includes a tenth NMOS transistor and an eleventh NMOS transistor, and each second switch includes a ninth NMOS transistor;

the grid electrode of the ninth NMOS tube is used for receiving a data bit in the target digital signal, the drain electrode of the ninth NMOS tube is electrically connected with the first end of the second gating switch, the source electrode of the ninth NMOS tube is electrically connected with the drain electrode of the tenth NMOS tube, the grid electrode of the tenth NMOS tube is electrically connected with the grid electrode of the third NMOS tube, the source electrode of the tenth NMOS tube is electrically connected with the drain electrode of the eleventh NMOS tube, the grid electrode of the eleventh NMOS tube is electrically connected with the grid electrode of the second NMOS tube, and the source electrode of the eleventh NMOS tube is grounded;

a branch composed of the second NMOS transistor and the third NMOS transistor and N-1 branches composed of the tenth NMOS transistor and the eleventh NMOS transistor form a cascode third current mirror, where the third current mirror has a ratio of 1: 2^N-2：2^N ^-3：……：2：1；

The second gating switch comprises a sixth NMOS transistor and a seventh NMOS transistor;

a gate of the sixth NMOS transistor is electrically connected to an input terminal of the phase inverter, a gate of the seventh NMOS transistor is electrically connected to an output terminal of the phase inverter, a source of the sixth NMOS transistor is electrically connected to a source of the seventh NMOS transistor and a drain of the ninth NMOS transistor, respectively, a drain of the sixth NMOS transistor is electrically connected to the first loading point of the voltage superposition unit, and a drain of the seventh NMOS transistor is electrically connected to the second loading point of the voltage superposition unit.

In a possible implementation manner of the first aspect, the voltage superposition unit includes a first superposition resistor, a first end of the first superposition resistor is electrically connected to the source of the fourth NMOS transistor and the drain of the sixth NMOS transistor, respectively, a second end of the first superposition resistor is electrically connected to the source of the fifth NMOS transistor and the drain of the seventh NMOS transistor, respectively, and the first voltage signal is generated according to the first superposition resistor and the target current signal.

In a second aspect, an embodiment of the present application provides a comparison circuit, which includes an N-bit successive approximation register, a third switch, a fourth switch, a comparator, and the foregoing digital-to-analog converter for voltage superposition;

the N-bit successive approximation register is electrically connected with the digital-to-analog converter, a first end of the third switch is electrically connected with the digital-to-analog converter, an output end of the digital-to-analog converter is electrically connected with a reverse input end of the comparator, and a second end of the third switch is electrically connected with a first end of the fourth switch and a same-direction input end of the comparator respectively; a first terminal of the third switch is configured to receive a third voltage, and a second terminal of the fourth switch is configured to receive a fourth voltage; the output end of the comparator is electrically connected with the N-bit successive approximation register;

During calibration, the third switch is closed, the fourth switch is opened, the N-bit successive approximation register acquires a clock signal, determines the target digital signal according to the clock signal and a level signal output by the comparator, and outputs the target digital signal; the digital-to-analog converter is used for determining an output analog voltage signal according to the target digital signal so that the analog voltage signal output by the digital-to-analog converter can eliminate the offset voltage of the comparator.

Compared with the prior art, the embodiment of the application has the advantages that:

the embodiment of the application provides a digital-to-analog converter for voltage superposition, which comprises a first current unit, a second current unit and a voltage superposition unit, wherein the first current unit is electrically connected with a first voltage source, the second current unit is grounded, and the first current unit, the voltage superposition unit and the second current unit are sequentially connected in series. The existing digital-to-analog converter takes the ground in the circuit as a voltage reference point, and the analog output voltage converted by the binary code cannot be directly superposed with the known voltage. According to the embodiment of the application, the first current unit and the second current unit enable the analog voltage signal output by the digital-to-analog converter not to be the voltage relative to the ground, and the problem that the analog output voltage converted by the binary code cannot be directly superposed with the known voltage by the conventional digital-to-analog converter is solved. The specific process is as follows: the first current unit provides a target current signal according to the target digital signal and controls the target current signal to be loaded at a first loading point or a second loading point in the voltage superposition unit; the second current unit provides a target current signal according to the target digital signal and controls the target current signal to be loaded at a second loading point or a first loading point in the voltage superposition unit; the voltage superposition unit generates a first voltage signal according to the target current signal, and the first voltage signal can be directly superposed with the target voltage signal received by the voltage superposition unit and output an analog voltage signal.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the embodiments or the prior art description will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings may be obtained according to these drawings without inventive labor.

Fig. 1 is a schematic structural diagram of a digital-to-analog converter for voltage superposition according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a digital-to-analog converter for voltage superposition according to another embodiment of the present application;

fig. 3 is a schematic structural diagram of a digital-to-analog converter for voltage superposition according to another embodiment of the present application;

fig. 4 is a schematic structural diagram of a digital-to-analog converter for voltage superposition according to another embodiment of the present application;

fig. 5 is a schematic structural diagram of a digital-to-analog converter for voltage superposition according to another embodiment of the present application;

fig. 6 is a schematic structural diagram of a digital-to-analog converter for voltage superposition according to another embodiment of the present application;

fig. 7 is a schematic structural diagram of a digital-to-analog converter for voltage superposition according to another embodiment of the present application;

Fig. 8 is a schematic structural diagram of a comparison circuit according to another embodiment of the present application.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It should also be understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

As used in the specification of this application and the appended claims, the term "if" may be interpreted contextually as "when …" or "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".

Furthermore, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between descriptions and not necessarily for describing or implying relative importance.

Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise.

As shown in fig. 1, an embodiment of the present application provides a digital-to-analog converter for voltage superposition, which can solve a problem that an existing digital-to-analog converter cannot directly superimpose an analog output voltage converted from a binary code with a known voltage. Comprises a first current unit 10, a second current power supply 30 and a voltage superposition unit 20, wherein the first current unit 10 is used for connecting with a first voltage sourceV_CCAnd the second current unit 30 is electrically connected to ground, and the first current unit 10, the voltage superposition unit 20 and the second current unit 30 are sequentially connected in series.

Specifically, the first current unit 10 receives a target digital signal, provides a target current signal according to the target digital signal, and controls the target current signal to be loaded at a first load point or a second load point in the voltage superposition unit 20.

The second current unit 30 receives the target digital signal, provides the target current signal according to the target digital signal, and controls the target current signal to be loaded at the second load point or the first load point in the voltage superimposing unit 20.

When the target current signal provided by the first current unit 10 is loaded at the first loading point in the voltage superposition unit 20 and the target current signal provided by the second current unit 30 is loaded at the second loading point in the voltage superposition unit 20, the flow direction of the target current signal in the voltage superposition unit 20 is the first direction. When the target current signal provided by the first current unit 10 is loaded at the second loading point in the voltage superposition unit 20 and the target current signal provided by the second current unit 30 is loaded at the first loading point in the voltage superposition unit 20, the flow direction of the target current signal in the voltage superposition unit 20 is the second direction. The first direction is opposite to the second direction.

The voltage superposition unit 20 receives a target voltage signal V_INAnd a target voltage signal V is provided_INAfter being superposed with the first voltage signal, the analog voltage signal V is output_{OUT_DAC}(ii) a The first voltage signal is generated by the voltage superposition unit 20 according to the target current signal.

The target digital signal corresponds to the N-bit digital code, and the magnitude of the target current signal can be changed by changing the target digital signal, and the flow direction of the target current signal in the voltage superposition unit 20 can be changed, so that the polarity and magnitude of the first voltage signal can be changed, and the output analog voltage signal V can be further enabled to be changed_{OUT_DAC}Both polarity and magnitude of (a) may be varied.

It should be noted that the digital target signal is obtained by the prior art.

As shown in the figure2, the first current unit 10 includes a first current input circuit 101, a first current source circuit 102, a first switch circuit 103, and a first commutation circuit 104. The first current source circuit 102 and the first current input circuit 101 are used for connecting with a first voltage source V_CCThe first current input circuit 101 is electrically connected to the first current source circuit 102, the first switch circuit 103 is electrically connected to the first current source circuit 102 and the first commutation circuit 104, and the first commutation circuit 104 is electrically connected to the first load point and the second load point of the voltage superimposing unit 20.

Specifically, the first current input circuit 101 provides a first input current for the first current source circuit 102.

The first current source circuit 102 provides N-1 reference current signals based on the first input current.

The first switch circuit 103 selects M reference current signals from the N-1 reference current signals according to the target digital signal to form a target current signal; wherein N is an integer greater than or equal to 2, M is greater than or equal to 0 and less than or equal to N-1, and M is an integer.

The first commutation circuit 104 controls the target current signal to be loaded on the first load point or the second load point in the voltage superposition unit 20 according to the target digital signal.

As shown in fig. 3, the first current source circuit 102 includes N-1 first current sources. The first switch circuit 103 includes N-1 first switches. The first commutation circuit 104 comprises a first gating switch. N-1 first current sources are electrically connected with the first current input circuit 101, and the anodes of the N-1 first current sources are used for connecting with a first voltage source V_CCThe cathodes of the N-1 first current sources are electrically connected with the first ends of the N-1 first switches in a one-to-one correspondence manner, the second ends of the N-1 first switches are electrically connected with the first end of the first gating switch, the second end of the first gating switch is electrically connected with the first loading point on the voltage superposition unit 20, and the third end of the first gating switch is electrically connected with the second loading point on the voltage superposition unit 20.

Specifically, the reference currents provided by the N-1 first current sources are respectively 2^N-2I，2^N-3I, …, 2I, I, wherein N is an integer greater than or equal to 2, and I is the first current inputA first input current provided by circuit 101. The control end of the N-1 first switches receives N-1 data bits in the target digital signal, and the N-1 data bits are B in sequence_N-2，B_N-3，…，B₁，B₀The data bit indicates whether the corresponding first switch is turned on or off. The control end of the first gating switch receives a sign bit in the target digital signal, wherein the sign bit is B_N-1And the sign bit indicates that the first gating switch loads the target current signal on the first load point or the second load point in the voltage superposition unit.

As shown in fig. 4, the first current input circuit 101 includes an operational amplifier AMP, a first resistor R₁A second resistor R₂A first NMOS transistor MN₁The first PMOS transistor MP₁And a second PMOS transistor MP₂. The non-inverting input terminal of the operational amplifier AMP receives a reference voltage V_REFThe inverting input terminals of the operational amplifier AMP are connected to the first resistors R, respectively₁First end of (1) and first NMOS transistor MN₁Is electrically connected to the source electrode of the first resistor R₁Is grounded, the output end of the operational amplifier AMP and the first NMOS transistor MN₁Is electrically connected. First NMOS transistor MN₁Respectively with the second resistor R ₂First end of the PMOS transistor MP and a second PMOS transistor MP₂Is electrically connected to the N-1 first current sources. A second resistor R₂The second end of the first PMOS transistor MP is connected with the second PMOS transistor MP₂Drain electrode of (1), first PMOS tube MP₁Is electrically connected to the N-1 first current sources. Second PMOS transistor MP₂Source electrode of and first PMOS transistor MP₁Is electrically connected with the drain electrode of the first PMOS transistor MP₁Is used for being connected with a first voltage source V_CCAnd (6) electrically connecting.

Specifically, under deep negative feedback, the voltages of the non-inverting input terminal and the inverting input terminal of the operational amplifier AMP are approximately equal, and the error is negligible, so that the first resistor R₁Voltage on is reference voltage V_REFTherefore, the first input current I provided by the first current input circuit 101 is V_REF/R₁。

As shown in fig. 5, each first current source includes a fifth PMOS transistor and a sixth PMOS transistor. Each first switchThe switch comprises an eighth NMOS transistor. The source electrode of the fifth PMOS tube is used for being connected with a first voltage source V_CCElectrically connected with the gate of the fifth PMOS transistor and the second resistor R₂The second end of the fifth PMOS tube is electrically connected, and the drain electrode of the fifth PMOS tube is electrically connected with the source electrode of the sixth PMOS tube. Grid electrode of sixth PMOS tube and first NMOS tube MN₁The drain electrode of the sixth PMOS tube is electrically connected with the drain electrode of the eighth NMOS tube. The grid electrode of the eighth NMOS tube receives a data bit in the target digital signal, and the source electrode of the eighth NMOS tube is electrically connected with the first end of the first gating switch.

As shown in FIG. 5, in the first current source, the fifth PMOS transistor is denoted as PMOS transistor MP₁₀The sixth PMOS transistor is represented as PMOS transistor MP₂₀. In the second first current source, the fifth PMOS transistor is represented as PMOS transistor MP₁₁The sixth PMOS transistor is represented as PMOS transistor MP₂₁. In the N-1 first current source, the fifth PMOS transistor is represented as PMOS transistor MP_1N-2The sixth PMOS transistor is represented as PMOS transistor MP_2N-2. In the first switch, the eighth NMOS transistor is represented as NMOS transistor MN₃₀In the second first switch, the eighth NMOS transistor is represented as NMOS transistor MN₃₁In the N-1 st switch, the eighth NMOS transistor is represented as the NMOS transistor MN_3N-2。

Specifically, when the data bit received by the gate of the eighth NMOS transistor is 1, the eighth NMOS transistor is turned on, and the reference current signal provided by the first current source connected to the eighth NMOS transistor is selected. When the data bit received by the grid electrode of the eighth NMOS tube is 0, the eighth NMOS tube is turned off, and the reference current signal provided by the first current source connected with the eighth NMOS tube is not selected.

First PMOS transistor MP₁And a second PMOS transistor MP₂The branch circuit formed by the N-1 fifth PMOS tubes and the branch circuit formed by the sixth PMOS tube form a cascode first current mirror, and the proportion of the first current mirror is 1: 2^N-2：2^N-3：……：2：1。

As shown in FIG. 5, the first gate switch includes an inverter and a fourth NMOS transistor MN ₄And a fifth NMOS transistor MN₅. An input terminal of the inverter receives the sign bit in the target digital signal, the input terminal of the inverter and the fifth NMOS pipe MN₅Is electrically connected with the grid electrode of the phase inverter, and the output end of the phase inverter is connected with the fourth NMOS tube MN₄Is electrically connected. Fourth NMOS transistor MN₄Respectively connected with the fifth NMOS transistor MN₅The drain electrode of the second NMOS tube is electrically connected with the source electrode of the eighth NMOS tube, and the fourth NMOS tube MN₄Is electrically connected to the first load point of the voltage superimposing unit 20. Fifth NMOS transistor MN₅Is electrically connected to the second load point of the voltage superimposing unit 20.

Specifically, when the sign bit received by the inverter is 1, the fourth NMOS transistor MN is turned on₄Turn off, fifth NMOS transistor MN₅And is turned on, and the control target current signal is loaded on the second loading point in the voltage superposition unit 20. When the sign bit received by the phase inverter is 0, the fourth NMOS transistor MN₄Conducting the fifth NMOS transistor MN₅And is turned off, and the control target current signal is loaded on the first loading point in the voltage superposition unit 20.

As shown in fig. 5, the second current unit 30 includes a second current input circuit 301, a second current source circuit 304, a second switching circuit 303, and a second commutation circuit 302. The second current input circuit 301 is used for connecting with the first voltage source V _CCElectrically connected, the second current source circuit 304 is for ground. The second current input circuit 301 is electrically connected to a second current source circuit 304, the second switch circuit 303 is electrically connected to the second current source circuit 304 and a second commutation circuit 302, respectively, and the second commutation circuit 302 is electrically connected to a first load point and a second load point on the voltage superimposing unit 20, respectively.

Specifically, the second current input circuit 301 provides a second input current to the second current source circuit 304.

The second current source circuit 304 provides N-1 reference current signals based on the second input current.

The second switch circuit 303 selects M reference current signals from the N-1 reference current signals according to the target digital signal to form the target current signal; wherein N is an integer greater than or equal to 2, M is greater than or equal to 0 and less than or equal to N-1, and M is an integer.

The second commutation circuit controls the target current signal to be loaded on the second load point or the first load point in the voltage superposition unit 20 according to the target digital signal.

As shown in fig. 6, the second current source circuit 304 includes N-1 second current sources. The second switch circuit 303 includes N-1 second switches. The second commutation circuit 302 includes a second gating switch. The N-1 second current sources are electrically connected to the second current input circuit 301, the anodes of the N-1 second current sources are electrically connected to the first ends of the N-1 second switches in a one-to-one correspondence manner, the cathodes of the N-1 second current sources are grounded, the second ends of the N-1 second switches are electrically connected to the first ends of the second gating switches, the second ends of the second gating switches are electrically connected to the first load points on the voltage superimposing unit 20, and the third ends of the second gating switches are electrically connected to the second load points on the voltage superimposing unit 20.

Specifically, the reference currents of the N-1 second current sources are respectively 2^N-2I，2^N-3I, …, 2I, where N is an integer greater than or equal to 2, I is the second input current provided by the second current input circuit 301;

and the control ends of the N-1 second switches receive N-1 data bits in the target digital signal, and the data bits indicate that the corresponding second switches are switched on or off. The control terminal of the second gating switch receives a sign bit in the target digital signal, and the sign bit instructs the second gating switch to load the target current signal at the second load point or the first load point in the voltage superimposing unit 20.

As shown in fig. 7, the second current input circuit 301 includes a third PMOS transistor MP₃And the fourth PMOS transistor MP₄And a third NMOS transistor MN₃A second NMOS transistor MN₂And a third resistor R₃. Third PMOS transistor MP₃Is used for being connected with a first voltage source V_CCElectrically connected, third PMOS transistor MP₃And a second resistor R₂The second end of the third PMOS tube MP is electrically connected₃Drain electrode of and fourth PMOS transistor MP₄Is electrically connected. Fourth PMOS transistor MP₄And a second resistor R₂The first end of the fourth PMOS tube MP is electrically connected₄Respectively with the third resistor R₃First terminal and third NMOS transistor MN₃Is electrically connected. Third resistor R₃The second end of the NMOS transistor is respectively connected with the third NMOS transistor MN ₃Drain electrode of (1) and second NMOS tube MN₂Is electrically connected. Third NMOS transistor MN₃Source electrode of (1) and second NMOS transistor MN₂Is electrically connected with the drain electrode of the second NMOS tube MN₂The source electrode of the third NMOS transistor MN is grounded₃Gate of the transistor and the second NMOS transistor MN₂Are all electrically connected with N-1 second current sources.

Specifically, the third PMOS transistor MP₃And a fourth PMOS transistor MP₄The branch and the first PMOS transistor MP₁And a second PMOS transistor MP₂The formed branch circuit forms a cascode second current mirror, and the proportion of the second current mirror is 1: 1.

as shown in fig. 7, each second current source includes a tenth NMOS transistor and an eleventh NMOS transistor. Each second switch comprises a ninth NMOS transistor. The grid electrode of the ninth NMOS tube receives a data bit in the target digital signal, the drain electrode of the ninth NMOS tube is electrically connected with the first end of the second gating switch, and the source electrode of the ninth NMOS tube is electrically connected with the drain electrode of the tenth NMOS tube. Grid of tenth NMOS transistor and third NMOS transistor MN₃The source electrode of the tenth NMOS tube is electrically connected with the drain electrode of the eleventh NMOS tube. Grid electrode of eleventh NMOS (N-channel metal oxide semiconductor) transistor and second NMOS transistor MN₂The grid of the eleventh NMOS tube is electrically connected, and the source of the eleventh NMOS tube is grounded.

As shown in FIG. 7, in the first and second current sources, the tenth NMOS transistor is represented as NMOS transistor MN ₂₀And the eleventh NMOS transistor is represented as NMOS transistor MN₁₀. In the second current source, the tenth NMOS transistor is represented as NMOS transistor MN₂₁The eleventh NMOS transistor is represented as NMOS transistor MN₁₁. In the N-1 second current source, the tenth NMOS transistor is represented as NMOS transistor MN_2N-2The eleventh NMOS transistor is represented as NMOS transistor MN_1N-2. In the first and second switches, the ninth NMOS transistor is represented as NMOS transistor MN₄₀In the second switch, the ninth NMOS transistor is represented as NMOS transistor MN₄₁In the N-1 second switch, the ninth NMOS transistor is represented as the NMOS transistor MN_4N-2。

Specifically, when the data bit received by the gate of the ninth NMOS transistor is 1, the ninth NMOS transistor is turned on, and then the reference current signal provided by the second current source connected to the ninth NMOS transistor is selected. When the data bit received by the grid electrode of the ninth NMOS tube is 0, the ninth NMOS tube is turned off, and the reference current signal provided by the second current source connected with the ninth NMOS tube is not selected.

Second NMOS transistor MN₂And a third NMOS transistor MN₃The formed branch circuit and the branch circuit formed by the N-1 tenth NMOS tube and the eleventh NMOS tube form a cascode third current mirror, and the proportion of the third current mirror is 1: 2^N-2：2^N-3：……：2：1。

As shown in fig. 7, the second gate switch includes a sixth NMOS transistor MN₆And a seventh NMOS transistor MN₇. Sixth NMOS transistor MN ₆The grid of the NMOS transistor is electrically connected with the input end of the phase inverter, and the seventh NMOS transistor MN₇The grid of the NMOS transistor is electrically connected with the output end of the phase inverter, and the sixth NMOS transistor MN₆Respectively connected with a seventh NMOS transistor MN₇The source electrode of the NMOS transistor is electrically connected with the drain electrode of the ninth NMOS transistor, and the sixth NMOS transistor MN₆Is electrically connected to the first load point of the voltage superposition unit 20, and a seventh NMOS transistor MN₇Is electrically connected to the second load point 20 of the voltage superimposing unit.

Specifically, when the sign bit received by the inverter is 1, the sixth NMOS transistor MN is implemented₆Conducting the seventh NMOS transistor MN₇And is turned off, and the control target current signal is loaded on the first loading point in the voltage superposition unit 20. When the sign bit received by the phase inverter is 0, the sixth NMOS transistor MN₆Turn off, seventh NMOS transistor MN₇And is turned on, and the control target current signal is loaded on the second loading point in the voltage superposition unit 20.

As shown in fig. 7, the voltage superimposing unit 20 includes a first superimposing resistor R₀First superimposed resistance R₀Respectively connected with the fourth NMOS transistor MN₄Source electrode and sixth NMOS transistor MN₆Is electrically connected with the drain electrode of the first resistor R₀Second terminals of the NMOS transistors are connected with a fifth NMOS transistor MN respectively₅Source electrode and seventh NMOS transistor MN₇Is electrically connected. The first voltage signal is based on the first superposed resistor R ₀And target current signal generation.

For the sake of clarity, the operation of the digital-to-analog converter for voltage superposition is described in detail with reference to fig. 7.

Firstly, receiving a target digital signal, wherein the target digital signal corresponds to an N-bit digital code, the code is 1 to represent that a corresponding open tube is connected, and the code is 0 to represent that a corresponding switch is disconnected. When the sign bit B_N-1When 1, the fourth NMOS transistor MN₄Turn off, fifth NMOS transistor MN₅Conducting the sixth NMOS transistor MN₆Conducting the seventh NMOS transistor MN₇Turning off, controlling R of the target current signal from the first superposition resistance₀From the first overlap resistor, R₀The first voltage signal defines a positive value. Sign bit B_N-1When 0, the fourth NMOS transistor MN₄Conducting the fifth NMOS transistor MN₅Turn off, sixth NMOS transistor MN₆Turn off, seventh NMOS transistor MN₇Conducting to control the R of the target current signal from the first superposition resistor₀From the first end of the first overlap resistor, R₀The first voltage signal is defined as a negative value.

The first current source and the second current source are symmetrical, and the data bit is from B_N-2～B₀Respectively corresponding to different current weights, high bit weight, low bit weight, and data bit B_iCorresponding current magnitude of 2 ⁱAnd I. Then the formula for the analog voltage signal can be derived:

for the description of the formula: when B is present_N-1When 1, the second term is positive; b is_N-1At 0, the second term is negative. B is_iTo 1, the corresponding current value is added, B_iIf the current value is 0, the corresponding current value does not exist, and finally a target current signal is obtained and passes through the first superposed resistor R₀And converting the voltage into a first voltage signal, wherein the first voltage signal corresponds to a second term in the formula.

As shown in fig. 8, an embodiment of the present application further provides a comparison circuit, which includes an N-bit successive approximation register 50 and a third switchS₃And a fourth switch S₄A comparator 60 and the above-mentioned digital-to-analog converter 40 for voltage superposition. The N-bit successive approximation register 50 is electrically connected to the digital-to-analog converter 40, and the third switch S₃Is electrically connected to the digital-to-analog converter 40, the output terminal of the digital-to-analog converter 40 is electrically connected to the inverting input terminal of the comparator 60, and the third switch S₃Respectively with the fourth switch S₄Is electrically connected to the unidirectional input of comparator 60. Third switch S₃For receiving a third voltage V₃Fourth switch S₄For receiving a fourth voltage V₄. The output 60 of the comparator is electrically connected to the N-bit successive approximation register 50.

In particular, during calibration, the third switch S₃Closed, fourth switch S₄And when the circuit is disconnected, the N-bit successive approximation register 50 acquires a clock signal, determines a target digital signal according to the clock signal and the level signal output by the comparator 60, and outputs the target digital signal. The DAC 40 determines the output analog voltage signal V according to the target digital signal_{OUT_DAC}So that the analog voltage signal V outputted from the digital-to-analog converter 40_{OUT_DAC}Eliminating offset voltage V of comparator_OS。

The process of determining the target digital signal by the N-bit successive approximation register 50 is: when the first clock rising edge arrives, the sign bit B of the digital-to-analog converter 40 is first set_N-1Set 1, data bit B_N-2～B₀Set to 0, and if the comparator 60 output is high, the sign bit B_N-1Set to 1, and if the output of comparator 60 is low, the sign bit B_N-1Setting to 0; when the second rising edge comes, the data bit B of the DAC 40 is converted to_N-2Set 1, data bit B_N-3～B₀Set 0, if sign bit B_N-1Is 1, then data bit B_N-2Set to coincide with the output level of comparator 60 if the sign bit B_N-1Is 0, then data bit B_N-2Set to be opposite to the comparator 60 output level; when the third rising edge comes, the data bit B of the DAC 40 is converted to_N-3Set 1, data bit B_N-4～B₀Set 0, if sign bit B _N-1Set to 1, then data bit B_N-3Set to be consistent with the output level of the comparator 60 if the sign bit B_N-1Is 0, then data bit B_N-3Set to be opposite to the comparator 60 output level; by analogy, each bit of the digital-to-analog converter 40 is determined and kept unchanged, and finally a target digital signal is obtained, so that the offset voltage V of the comparator 60 is eliminated by the analog voltage signal output by the digital-to-analog converter 40_OS。

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims

1. A digital-to-analog converter for voltage superposition is characterized by comprising a first current unit, a second current unit and a voltage superposition unit, wherein the first current unit is electrically connected with a first voltage source, the second current unit is grounded, and the first current unit, the voltage superposition unit and the second current unit are sequentially connected in series;

when a target current signal provided by the first current unit is loaded at a first loading point in the voltage superposition unit and a target current signal provided by the second current unit is loaded at a second loading point in the voltage superposition unit, the flow direction of the target current signal in the voltage superposition unit is a first direction; when the target current signal provided by the first current unit is loaded at a second loading point in the voltage superposition unit and the target current signal provided by the second current unit is loaded at a first loading point in the voltage superposition unit, the flow direction of the target current signal in the voltage superposition unit is a second direction; the first direction and the second direction are opposite;

2. The digital-to-analog converter for voltage superposition according to claim 1, wherein the first current unit comprises a first current input circuit, a first current source circuit, a first switching circuit, and a first commutation circuit; the first current source circuit and the first current input circuit are both used for being electrically connected with the first voltage source, the first current input circuit is electrically connected with the first current source circuit, the first switch circuit is respectively electrically connected with the first current source circuit and the first reversing circuit, and the first reversing circuit is respectively electrically connected with a first loading point and a second loading point on the voltage superposition unit;

3. The digital-to-analog converter for voltage superposition according to claim 2, wherein the first current source circuit comprises N-1 first current sources, the first switching circuit comprises N-1 first switches, and the first commutation circuit comprises a first gating switch; the N-1 first current sources are electrically connected with the first current input circuit, the anodes of the N-1 first current sources are used for being electrically connected with the first voltage source, the cathodes of the N-1 first current sources are electrically connected with the first ends of the N-1 first switches in a one-to-one correspondence manner, the second ends of the N-1 first switches are electrically connected with the first end of the first gating switch, the second end of the first gating switch is electrically connected with a first loading point on the voltage superposition unit, and the third end of the first gating switch is electrically connected with a second loading point on the voltage superposition unit;

The reference currents provided by the N-1 first current sources are respectively 2^N-2I，2^N-3I, …, 2I, I, wherein N is an integer greater than or equal to 2, and I is a first input current provided by the first current input circuit; the control end of the N-1 first switches is used for receiving N-1 data bits in the target digital signal, and the N-1 data bits are B in sequence_N-2，B_N-3，…，B₁，B₀The data bit is used for indicating the corresponding first switch to be switched on or switched off; the control end of the first gating switch is used for receiving a sign bit in the target digital signal, and the sign bit is B_N-1And the sign bit is used for instructing the first gating switch to load the target current signal on a first load point or a second load point in the voltage superposition unit.

4. The digital-to-analog converter for voltage superposition of claim 3, wherein the first current input circuit comprises an operational amplifier, a first resistor, a second resistor, a first NMOS transistor, a first PMOS transistor and a second PMOS transistor;

5. The digital-to-analog converter for voltage superposition of claim 4, wherein each of said first current sources comprises a fifth PMOS transistor and a sixth PMOS transistor; each first switch comprises an eighth NMOS transistor;

a branch composed of the first PMOS tube and the second PMOS tube and branches composed of the N-1 fifth PMOS tubes and the sixth PMOS tubes form a cascode first current mirror, and the cascode first current mirror is formed by the first PMOS tube and the second PMOS tubeThe first current mirror proportion is 1: 2^N-2：2^N-3：……：2：1；

6. The digital-to-analog converter for voltage superposition according to claim 5, wherein the second current unit comprises a second current input circuit, a second current source circuit, a second switching circuit, and a second commutation circuit; the second current input circuit is used for being electrically connected with the first voltage source, and the second current source circuit is used for being grounded; the second current input circuit is electrically connected with the second current source circuit, the second switch circuit is electrically connected with the second current source circuit and the second reversing circuit respectively, and the second reversing circuit is electrically connected with a first loading point and a second loading point on the voltage superposition unit respectively;

7. The digital-to-analog converter for voltage superposition of claim 6, wherein the second current source circuit comprises N-1 second current sources, the second switching circuit comprises N-1 second switches, and the second commutation circuit comprises a second gating switch; the N-1 second current sources are electrically connected with the second current input circuit, anodes of the N-1 second current sources are electrically connected with first ends of the N-1 second switches in a one-to-one correspondence manner, cathodes of the N-1 second current sources are grounded, second ends of the N-1 second switches are electrically connected with first ends of the second gating switches, second ends of the second gating switches are electrically connected with a first loading point on the voltage superposition unit, and third ends of the second gating switches are electrically connected with a second loading point on the voltage superposition unit;

the source electrode of the third PMOS tube is used for being electrically connected with the first voltage source, the grid electrode of the third PMOS tube is electrically connected with the second end of the second resistor, the drain electrode of the third PMOS tube is electrically connected with the source electrode of the fourth PMOS tube, the grid electrode of the fourth PMOS tube is electrically connected with the first end of the second resistor, the drain electrode of the fourth PMOS tube is respectively electrically connected with the first end of the third resistor and the grid electrode of the third NMOS tube, the second end of the third resistor is respectively electrically connected with the drain electrode of the third NMOS tube and the grid electrode of the second NMOS tube, the source electrode of the third NMOS tube is electrically connected with the drain electrode of the second NMOS tube, the source electrode of the second NMOS tube is grounded, and the grid electrode of the third NMOS tube and the grid electrode of the second NMOS tube are both electrically connected with the N-1 second current sources;

the branch circuit formed by the third PMOS tube and the fourth PMOS tube and the branch circuit formed by the first PMOS tube and the second PMOS tube form a cascode second current mirror, and the proportion of the second current mirror is 1: 1.

8. The digital-to-analog converter for voltage superposition of claim 7, wherein each of said second current sources comprises a tenth NMOS transistor and an eleventh NMOS transistor, and each of said second switches comprises a ninth NMOS transistor;

a branch composed of the second NMOS transistor and the third NMOS transistor and branches composed of N-1 tenth NMOS transistors and eleventh NMOS transistors form a cascode third current mirror, where the ratio of the third current mirror is 1: 2^N-2：2^N ^-3：……：2：1；

the grid electrode of the sixth NMOS tube is electrically connected with the input end of the phase inverter, the grid electrode of the seventh NMOS tube is electrically connected with the output end of the phase inverter, the source electrode of the sixth NMOS tube is respectively electrically connected with the source electrode of the seventh NMOS tube and the drain electrode of the ninth NMOS tube, the drain electrode of the sixth NMOS tube is electrically connected with the first loading point of the voltage superposition unit, and the drain electrode of the seventh NMOS tube is electrically connected with the second loading point of the voltage superposition unit.

9. The digital-to-analog converter for voltage superposition according to claim 8, wherein the voltage superposition unit comprises a first superposition resistor, a first end of the first superposition resistor is electrically connected with the source of the fourth NMOS transistor and the drain of the sixth NMOS transistor, respectively, a second end of the first superposition resistor is electrically connected with the source of the fifth NMOS transistor and the drain of the seventh NMOS transistor, respectively, and the first voltage signal is generated according to the first superposition resistor and the target current signal.

10. A comparison circuit comprising an N-bit successive approximation register, a third switch, a fourth switch, a comparator and the digital-to-analog converter for voltage superposition of any one of claims 1 to 9;