CN114679157B - Programmable frequency generator and calibration method thereof - Google Patents

Programmable frequency generator and calibration method thereof Download PDF

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Publication number
CN114679157B
CN114679157B CN202210328245.1A CN202210328245A CN114679157B CN 114679157 B CN114679157 B CN 114679157B CN 202210328245 A CN202210328245 A CN 202210328245A CN 114679157 B CN114679157 B CN 114679157B
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nmos tube
tube
frequency modulation
frequency
nmos
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CN114679157A (en
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朱乐永
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Praran Semiconductor Shanghai Co ltd
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Praran Semiconductor Shanghai Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

The invention discloses a programmable frequency generator, which is characterized in that a calibration circuit is added in a circuit, the number of bits of the calibration circuit is k which is smaller than the number of bits n of a frequency modulation circuit, so that the number of bits of the frequency modulation circuit and the width-to-length ratio of a first mirror NMOS tube can be reduced, the area of the frequency modulation circuit can be greatly reduced, the frequency output by the programmable frequency generator is calibrated through the calibration circuit with fewer bits and the total width-to-length ratio, the range and the precision of the frequency output by the programmable frequency generator are ensured, the programmable frequency generator has a smaller chip area, and the cost of the calibrated programmable frequency generator is saved. The invention also discloses a calibration method of the programmable frequency generator.

Description

Programmable frequency generator and calibration method thereof
Technical Field
The present invention relates to semiconductor integrated circuit oscillator technology, and more particularly, to a programmable frequency generator and a calibration method thereof.
Background
The frequency of the output can be regulated by a Programmable Frequency Generator (PFG) through software control, and the frequency can be used for applications such as atomizers, and the more the frequency of an atomizing sheet of the atomizer is close to the output frequency of the PFG, the better the atomization effect is generated. Because the frequency of different atomizing sheets is different and the frequency of the atomizing sheets is changed due to the change of the working environment, the output frequency of the PFG needs to be adjustable within a certain range and step (step length) in frequency tracking can be uniformly changed, so that the atomizer can generate the optimal use effect.
As shown in fig. 1, the principle of a Programmable Frequency Generator (PFG) circuit, typically without calibration, is as follows: the input current I1=VGS/R0, VGS is the gate-source voltage of the zeroth NMOS tube on the left, R0 is the resistance value of the 0 th resistor R0 in figure 1, the input current I1 is mirrored and output to the third PMOS tube P3 after passing through the first FM NMOS tube N1M, the second FM NMOS tubes N2M, …, the mth FM NMOS tube NmM, the second NMOS tube N2 and the like, and then mirrored and output to the fourth PMOS tube P4-seventh PMOS tube P7, the third NMOS tube N3-sixth NMOS tube N6, the zeroth capacitor C0-second capacitor C2 and the like to generate oscillation, finally the output end VOUT of the Programmable Frequency Generator (PFG) outputs square waves, and the frequency of the square waves is proportional to that of the Programmable Frequency Generator (PFG) Wherein i is 1,2,3, …, m, IN2 is the drain current of the second NMOS transistor N2, iiM is the current flowing through the ith fm NMOS transistor NiM when it is turned on, bi is the weighting coefficient of IiM, bi is 1 when the ith enable signal Eni is high voltage, bi=0 when the ith enable signal Eni is 0V, and the capacitance values of the zeroth capacitor C0, the first capacitor C1, and the second capacitor C2 are equal, m is an integer greater than 1 (m may be 8 or 9 equivalent according to the application situation), and i is a positive integer less than or equal to m; Is the width-to-length ratio of the first frequency modulation NMOS tube N1M,/> Is the width-to-length ratio of the second frequency modulation NMOS tube N2M,/>Is the width-to-length ratio of the (M-1) th frequency modulation NMOS tube N (M-1) M,/>For the width to length ratio of the mth fm NMOS tube NmM, each fm NMOS tube is used to adjust the range of output frequencies of a Programmable Frequency Generator (PFG).
From the above formula, the frequency step (step) of the square wave is proportional toIn the circuit,/>This value is typically small. Taking a Programmable Frequency Generator (PFG) with an output frequency of 2.4MHz as an example, if the frequency step (step) is 1KHz, then/>This requires that the second NMOS transistor N2 has a large size to meet the MOS transistor mismatch requirement, which results in a large total area of the first to mth fm NMOS transistors N1M to NmM and the second NMOS transistor N2, which is not beneficial to chip cost savings.
Disclosure of Invention
The invention aims to solve the technical problem of providing a programmable frequency generator and a calibration method, which ensure the range and the precision of the frequency output by the programmable frequency generator, simultaneously ensure that the programmable frequency generator has a smaller chip area, and save the cost of the calibration programmable frequency generator.
In order to solve the technical problems, the programmable frequency generator provided by the invention comprises a current generating circuit, a mirror current circuit, a ring-shaped oscillating circuit and a calibration circuit;
The current generation circuit comprises a second PMOS tube P2 and a first NMOS tube N1;
The source end of the second PMOS tube P2 is connected with the working voltage VDD, and the drain end of the second PMOS tube P2 is connected with the drain end and the gate end of the first NMOS tube N1;
The source end of the first NMOS tube N1 is grounded;
The mirror current circuit comprises a frequency modulation circuit and a third PMOS tube P3;
The frequency modulation circuit comprises a first frequency modulation NMOS tube N1M, second frequency modulation NMOS tubes N2M and …, an nth frequency modulation NMOS tube NnM, a first mirror image NMOS tube N1MA, a first frequency modulation control NMOS tube N1MC, second frequency modulation control NMOS tubes N2MC and …, an nth frequency modulation control NMOS tube NnMC and a first mirror image control NMOS tube N1MAC;
the drain end of the ith frequency modulation NMOS tube NiM is connected with the source end of the ith frequency modulation control NMOS tube NiMC, n is an integer greater than 1, (i=1, 2, … …, n);
the drain end of the first mirror NMOS tube N1MA is connected with the source end of the first mirror control NMOS tube N1 MAC;
The gate of the ith frequency modulation control NMOS tube NiMC is connected with an ith enabling signal ENi, and the first mirror image control NMOS tube N1MAC is connected with a basic mirror image enabling signal EN1A;
the drain end of each frequency modulation control NMOS tube and the drain end of the first mirror image control NMOS tube N1MAC are connected with the drain end and the gate end of the third PMOS tube P3;
the source end of each frequency modulation NMOS tube and the source end of the first mirror NMOS tube N1MA are grounded;
The grid end of each frequency modulation NMOS tube and the grid end of the first mirror NMOS tube N1MA are connected with the source end of the second PMOS tube P2;
The source end of the third PMOS tube P3 is connected with the working voltage VDD;
The gate end of the third PMOS tube P3 outputs an oscillation control signal to the annular oscillation circuit;
The calibration circuit comprises a zeroth calibration NMOS tube NC0, a first calibration NMOS tube NC1, a (K-1) th calibration NMOS tube NC (K-1), a zeroth calibration control NMOS tube NC0C, a first calibration control NMOS tube NC1C, a (K-1) th calibration control NMOS tube NC (K-1) C, wherein K is a positive integer smaller than n;
The jth correction NMOS NCj has its drain connected to the source of the jth correction control NMOS NCjC, (j=1, 2, … …, k-1), its gate connected to the jth correction enable signal CALEN (j), and its drain connected to the drain and gate of the third PMOS P3;
the source end of each correction NMOS tube is grounded;
The gate end of each correction NMOS tube is connected with the source end of the second PMOS tube P2.
Preferably, the total width-to-length ratio of each of the FM NMOS transistors and the first mirror NMOS transistor N1MA in the mirror current circuit is designed asThe width to length ratio (W/L) n corresponding to the n-th FM NMOS tube NnM with the highest n is/>The (N-1) th frequency modulation NMOS tube N (N-1) M of the next highest order N-1 has a width to length ratio (W/L) n-1 of/>The width-to-length ratio of the rest low bits is 1/2 of the width-to-length ratio corresponding to the previous bit of the first frequency modulation NMOS tube until the width-to-length ratio (W/L) 1 of the first frequency modulation NMOS tube N1M at the lowest bit is/>In addition, the width-to-length ratio of the first mirror NMOS transistor N1MA is also/>
The width-to-length ratio of the zeroth correction NMOS tube NC0, the first correction NMOS tube NC1, the (K-1) th correction NMOS tube NC (K-1) is doubled in sequence.
Preferably, the sum of the width-to-length ratios of the zeroth correction NMOS tube NC0, the first correction NMOS tube NC1, the (K-1) th correction NMOS tube NC (K-1) is larger than the width-to-length ratio of the first NMOS tube N1 and smaller than
Preferably, the width-to-length ratio of the zeroth correction NMOS tube NC0 is smaller than that of the first frequency modulation NMOS tube N1M;
the width-to-length ratio of the (K-1) th correction NMOS tube NC (K-1) is smaller than
Preferably, the gate end of each correction control NMOS tube in the correction circuit is respectively connected with the output of an AND gate;
Each AND gate AND has one input terminal for receiving the correction enable signal CALEN AND another input terminal for receiving the correction select signal CAL (k-1:0).
Preferably, the current generating circuit further comprises a zeroth PMOS transistor P0, a first PMOS transistor P1, a zeroth NMOS transistor N0, a zeroth resistor R0, and an operational amplifier OP;
The source ends of the zeroth PMOS tube P0 and the first PMOS tube P1 are connected with the working voltage VDD;
the gates of the zeroth PMOS tube P0, the first PMOS tube P1 and the second PMOS tube P2 are connected with the output of the operational amplifier OP;
the drain end of the zeroth PMOS tube P0 is short-circuited with the drain end and the gate end of the zeroth NMOS tube N0, and the input of the operational amplifier OP is negative;
the drain end of the first PMOS tube P1 is connected with one ends of the input positive resistor R0 and the zero resistor R0 of the operational amplifier OP;
the source end of the zeroth NMOS tube N0 and the other end of the zeroth resistor R0 are grounded.
Preferably, the annular oscillating circuit includes a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a zeroth capacitor C0, a first capacitor C1, a second capacitor C2, and a buffer BUF;
the sources of the fourth PMOS tube P4, the fifth PMOS tube P5, the sixth PMOS tube P6 and the seventh PMOS tube P7 are connected with the working voltage VDD, and the gates are connected with the gate end of the third PMOS tube P3;
The gate of the third NMOS tube N3 is connected with the drain end of the sixth PMOS tube P6, the drain end of the fifth NMOS tube N5 and one end of the second capacitor C2;
the grid end of the fourth NMOS tube N4 is connected with the drain end of the fourth PMOS tube P4, the drain end of the third NMOS tube N3 and one end of a zeroth capacitor C0;
the gate of the fifth NMOS tube N5 is connected with the drain end of the fifth PMOS tube P5, the drain end of the fourth NMOS tube N4 and one end of the first capacitor C1;
the source ends of the third NMOS tube N3, the fourth NMOS tube N4, the fifth NMOS tube N5 and the sixth NMOS tube N6 are grounded, and the other ends of the zeroth capacitor C0, the first capacitor C1 and the second capacitor C2 are grounded;
the drain end of the seventh PMOS tube P7 and the drain end of the sixth NMOS tube N6 are connected with the input end of the buffer BUF,
The output of the buffer BUF serves as the programmable frequency generator output VOUT.
Preferably, the capacitance values of the zeroth capacitor C0, the first capacitor C1 and the second capacitor C2 are the same.
In order to solve the technical problem, the calibration method of the programmable frequency generator provided by the invention comprises the following steps:
S1, calibrating a programmable frequency generator before the programmable frequency generator works, and configuring a (k-1) th correction enabling signal CALEN (k-1) of a (k-1) th correction control NMOS tube NC (k-1) C of a calibration circuit to be high-level 1 before the programmable frequency generator calibrates, wherein correction enabling signals of gate ends of other correction control NMOS tubes are configured to be low-level 0;
s2, calibrating a programmable frequency generator, which comprises the following steps:
s21, measuring PFG frequency difference caused by mismatching of each frequency modulation NMOS tube:
Firstly, disconnecting the current of an N-th frequency modulation NMOS tube NnM corresponding to the highest bit N, conducting the current of each frequency modulation NMOS tube corresponding to the rest low bits and a first mirror NMOS tube N1MA, and recording the frequency f n of the square wave output by the output end VOUT of the programmable frequency generator at the moment; then, the current of an N-th frequency modulation NMOS tube NnM corresponding to the highest bit N is conducted, the currents of all frequency modulation NMOS tubes corresponding to the rest low bits and a first mirror NMOS tube N1MA are disconnected, the frequency f nT of the square wave output by the output end VOUT of the programmable frequency generator at the moment is recorded, and the frequency difference of f n-fnT is recorded as f Δn;
The current of the N-th frequency modulation NMOS tube NnM and the (N-1) th frequency modulation NMOS tube N (N-1) M corresponding to the highest N and the next highest N-1 is disconnected, the currents of the other frequency modulation NMOS tubes corresponding to the lower bits and the first mirror NMOS tube N1MA are conducted, and the frequency f n-1 of the square wave output by the output end VOUT of the programmable frequency generator at the moment is recorded; then keeping the current of an N-th frequency modulation NMOS tube NnM corresponding to the highest order N off, switching on the current of an N-1-th frequency modulation NMOS tube N (N-1) M corresponding to the next highest order N-1, switching off the currents of all the frequency modulation NMOS tubes corresponding to the rest low orders and a first mirror NMOS tube N1MA, recording the frequency f (n-1)T of the square wave output by the output end VOUT of the programmable frequency generator at the moment, and recording the frequency difference of f (n-1)-f(n-1)T as f Δ(n-1);
The measurement of the remaining bits is analogized in sequence until the measurement completes the frequency difference f Δi for each bit, (i=1, 2, … …, n);
S22, when the programmable frequency generator works, when a corresponding bit current mirror of at least one frequency modulation NMOS tube is used, a (k-1) th correction enabling signal CALEN (k-1) of a (k-1) th correction control NMOS tube NC (k-1) C gate end of the calibration circuit is configured to be low level 0, and correction enabling signals of gate ends of other correction control NMOS tubes are configured to be at least one high level 1, so that the calibration circuit is controlled to subtract corresponding frequency difference; the total frequency difference to be subtracted by the correction circuit is the sum of the frequencies to be subtracted of the corresponding bit current mirrors of all the frequency modulation NMOS tubes to be used;
When the highest n current mirror corresponding to the nth frequency modulation NMOS tube NnM is used, the calibration circuit needs to be controlled to enable the output frequency minus the frequency to be 1/2*f Δn; when the N-1 th FM NMOS tube N (N-1) M is used, the calibration circuit is controlled to make the subtracted frequency of the output frequency be 1/2 x (f Δ(n-1)-1/2*fΔn), and so on, and when the t-th FM NMOS tube NtM is used, the calibration circuit is controlled to make the subtracted frequency of the output frequency be
The Programmable Frequency Generator (PFG) is added with the calibration circuit, the bit number k of the calibration circuit is smaller than the bit number N of the frequency modulation circuit, so that the bit number of the frequency modulation circuit and the width-to-length ratio of the first mirror NMOS tube N1MA can be reduced, the area of the frequency modulation circuit can be greatly reduced, the frequency output by the Programmable Frequency Generator (PFG) is calibrated through the calibration circuit with smaller bit number and total width-to-length ratio, the range and the precision of the frequency output by the Programmable Frequency Generator (PFG) are ensured, the Programmable Frequency Generator (PFG) has smaller chip area, and the cost of the calibrated Programmable Frequency Generator (PFG) is saved.
Drawings
In order to more clearly illustrate the technical solutions of the present invention, the following brief description of the drawings is given for the purpose of the present invention, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without the need for inventive work for a person skilled in the art.
FIG. 1 is a circuit diagram of a prior art frequency programmable frequency generator without calibration;
FIG. 2 is a circuit diagram of an embodiment of a programmable frequency generator of the present invention;
FIG. 3 is a circuit diagram of a calibration circuit of an embodiment of the programmable frequency generator of the present invention;
FIG. 4 is a circuit diagram of a ring oscillator according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
As shown in fig. 2, the Programmable Frequency Generator (PFG) includes a current generating circuit, a mirror current circuit, a ring oscillator circuit, and a calibration circuit;
The current generation circuit comprises a second PMOS tube P2 and a first NMOS tube N1;
The source end of the second PMOS tube P2 is connected with the working voltage VDD, and the drain end of the second PMOS tube P2 is connected with the drain end and the gate end of the first NMOS tube N1;
The source end of the first NMOS tube N1 is grounded;
The mirror current circuit comprises a frequency modulation circuit and a third PMOS tube P3;
The frequency modulation circuit comprises a first frequency modulation NMOS tube N1M, second frequency modulation NMOS tubes N2M and …, an nth frequency modulation NMOS tube NnM, a first mirror image NMOS tube N1MA, a first frequency modulation control NMOS tube N1MC, second frequency modulation control NMOS tubes N2MC and …, an nth frequency modulation control NMOS tube NnMC and a first mirror image control NMOS tube N1MAC;
the drain end of the ith frequency modulation NMOS tube NiM is connected with the source end of the ith frequency modulation control NMOS tube NiMC, n is an integer greater than 1, (i=1, 2, … …, n);
the drain end of the first mirror NMOS tube N1MA is connected with the source end of the first mirror control NMOS tube N1 MAC;
The gate of the ith frequency modulation control NMOS tube NiMC is connected with an ith enabling signal ENi, and the first mirror image control NMOS tube N1MAC is connected with a basic mirror image enabling signal EN1A;
the drain end of each frequency modulation control NMOS tube and the drain end of the first mirror image control NMOS tube N1MAC are connected with the drain end and the gate end of the third PMOS tube P3;
the source end of each frequency modulation NMOS tube and the source end of the first mirror NMOS tube N1MA are grounded;
The grid end of each frequency modulation NMOS tube and the grid end of the first mirror NMOS tube N1MA are connected with the source end of the second PMOS tube P2;
The source end of the third PMOS tube P3 is connected with the working voltage VDD;
The gate end of the third PMOS tube P3 outputs an oscillation control signal to the annular oscillation circuit;
As shown in fig. 3, the calibration circuit includes a zeroth calibration NMOS tube NC0, a first calibration NMOS tube NC1, a (K-1) th calibration NMOS tube NC (K-1), a zeroth calibration control NMOS tube NC0C, a first calibration control NMOS tube NC1C, a (K-1) th calibration control NMOS tube NC (K-1) C, K being a positive integer less than n;
The jth correction NMOS NCj has its drain connected to the source of the jth correction control NMOS NCjC, (j=1, 2, … …, k-1), its gate connected to the jth correction enable signal CALEN (j), and its drain connected to the drain and gate of the third PMOS P3;
the source end of each correction NMOS tube is grounded;
The gate end of each correction NMOS tube is connected with the source end of the second PMOS tube P2.
The Programmable Frequency Generator (PFG) of the first embodiment is an image current circuit composed of a first fm NMOS tube N1M, a second fm NMOS tube N2M, …, an N-th fm NMOS tube NnM, a first image NMOS tube N1MA, a first fm control NMOS tube N1MC, a second fm control NMOS tube N2MC, …, an N-th fm control NMOS tube NnMC, a first image control NMOS tube N1MAC, etc., where the first fm control NMOS tube N1MC, the second fm control NMOS tube N2MC, …, the N-th fm control NMOS tube NnMC, and the first image control NMOS tube N1MAC are used to control on/off of the corresponding branch current; the calibration circuit is composed of a zeroth calibration NMOS tube NC0, a first calibration NMOS tube NC1, a (K-1) th calibration NMOS tube NC (K-1), a zeroth calibration control NMOS tube NC0C, a first calibration control NMOS tube NC1C, a (K-1) th calibration control NMOS tube NC (K-1) C and the like.
The Programmable Frequency Generator (PFG) of the first embodiment adds a calibration circuit in the circuit, where the number k of bits of the calibration circuit is smaller than the number N of bits of the frequency modulation circuit, so that the number of bits of the frequency modulation circuit and the width-to-length ratio of the first mirror NMOS N1MA can be reduced, the area of the frequency modulation circuit can be greatly reduced, and the frequency output by the Programmable Frequency Generator (PFG) can be calibrated by the calibration circuit with smaller number and the total width-to-length ratio, so that the Programmable Frequency Generator (PFG) has a smaller chip area while ensuring the range and accuracy of the frequency output by the Programmable Frequency Generator (PFG), and the cost of the calibrated Programmable Frequency Generator (PFG) can be saved.
Example two
Based on the Programmable Frequency Generator (PFG) of the first embodiment, the total width-to-length ratio of each of the frequency modulation NMOS transistors and the first mirror NMOS transistor N1MA in the mirror current circuit is designed asThe width to length ratio (W/L) n corresponding to the n-th FM NMOS tube NnM with the highest n is/>The (N-1) th frequency modulation NMOS tube N (N-1) M of the next highest order N-1 has a width to length ratio (W/L) n-1 ofThe width-to-length ratio of the rest low bits is 1/2 of the width-to-length ratio corresponding to the previous bit of the first frequency modulation NMOS tube until the width-to-length ratio (W/L) 1 of the first frequency modulation NMOS tube N1M at the lowest bit is/>In addition, the width-to-length ratio of the first mirror NMOS transistor N1MA is also
The width-to-length ratio of the zeroth correction NMOS tube NC0, the first correction NMOS tube NC1, the (K-1) th correction NMOS tube NC (K-1) is doubled in sequence.
Preferably, the sum of the width-to-length ratios of the zeroth correction NMOS tube NC0, the first correction NMOS tube NC1, the (K-1) th correction NMOS tube NC (K-1) is larger than the width-to-length ratio of the first NMOS tube N1 and smaller than
Preferably, the width-to-length ratio of the zeroth correction NMOS tube NC0 is smaller than that of the first frequency modulation NMOS tube N1M;
the width-to-length ratio of the (K-1) th correction NMOS tube NC (K-1) is smaller than
Preferably, the gate end of each correction control NMOS tube in the correction circuit is respectively connected with the output of an AND gate;
Each AND gate AND has one input terminal for receiving the correction enable signal CALEN AND another input terminal for receiving the correction select signal CAL (k-1:0).
The Programmable Frequency Generator (PFG) of the second embodiment can be determined by matching the resistance in the current generating circuit and the capacitance in the ring oscillator circuit in circuit designThe width-to-length ratio (W/L) 1 of the first frequency modulation NMOS transistor N1M at the lowest position is/>In addition, the width-to-length ratio of the first mirror NMOS transistor N1MA is also/>The same effect is that the width-to-length ratio W/L of the highest bit and the total W/L of all the lower bits can be the same in calibration.
Example III
Based on the Programmable Frequency Generator (PFG) of the first embodiment, the current generating circuit further includes a zeroth PMOS transistor P0, a first PMOS transistor P1, a zeroth NMOS transistor N0, a zeroth resistor R0, and an operational amplifier OP;
The source ends of the zeroth PMOS tube P0 and the first PMOS tube P1 are connected with the working voltage VDD;
the gates of the zeroth PMOS tube P0, the first PMOS tube P1 and the second PMOS tube P2 are connected with the output of the operational amplifier OP;
the drain end of the zeroth PMOS tube P0 is short-circuited with the drain end and the gate end of the zeroth NMOS tube N0, and the input of the operational amplifier OP is negative;
the drain end of the first PMOS tube P1 is connected with one ends of the input positive resistor R0 and the zero resistor R0 of the operational amplifier OP;
the source end of the zeroth NMOS tube N0 and the other end of the zeroth resistor R0 are grounded.
The Programmable Frequency Generator (PFG) of the third embodiment is a current generating circuit composed of a zeroth PMOS transistor P0, a first PMOS transistor P1, a second PMOS transistor P2, a zeroth NMOS transistor N0, a first NMOS transistor N1, a zeroth resistor R0, an operational amplifier OP, and the like.
Example IV
Based on the Programmable Frequency Generator (PFG) of the first embodiment, as shown in fig. 4, the ring oscillator circuit includes a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a zeroth capacitor C0, a first capacitor C1, a second capacitor C2, and a buffer BUF;
the sources of the fourth PMOS tube P4, the fifth PMOS tube P5, the sixth PMOS tube P6 and the seventh PMOS tube P7 are connected with the working voltage VDD, and the gates are connected with the gate end of the third PMOS tube P3;
The gate of the third NMOS tube N3 is connected with the drain end of the sixth PMOS tube P6, the drain end of the fifth NMOS tube N5 and one end of the second capacitor C2;
the grid end of the fourth NMOS tube N4 is connected with the drain end of the fourth PMOS tube P4, the drain end of the third NMOS tube N3 and one end of a zeroth capacitor C0;
the gate of the fifth NMOS tube N5 is connected with the drain end of the fifth PMOS tube P5, the drain end of the fourth NMOS tube N4 and one end of the first capacitor C1;
the source ends of the third NMOS tube N3, the fourth NMOS tube N4, the fifth NMOS tube N5 and the sixth NMOS tube N6 are grounded, and the other ends of the zeroth capacitor C0, the first capacitor C1 and the second capacitor C2 are grounded;
the drain end of the seventh PMOS tube P7 and the drain end of the sixth NMOS tube N6 are connected with the input end of the buffer BUF,
The output of the buffer BUF serves as the programmable frequency generator output VOUT.
Preferably, the capacitance values of the zeroth capacitor C0, the first capacitor C1 and the second capacitor C2 are the same.
Example five
A method of calibrating a Programmable Frequency Generator (PFG) of the second embodiment includes the steps of:
S1, calibrating a programmable frequency generator before the programmable frequency generator works, and configuring a (k-1) th correction enabling signal CALEN (k-1) of a (k-1) th correction control NMOS tube NC (k-1) C of a calibration circuit to be high-level 1 before the programmable frequency generator calibrates, wherein correction enabling signals of gate ends of other correction control NMOS tubes are configured to be low-level 0;
s2, calibrating a programmable frequency generator, which comprises the following steps:
s21, measuring PFG frequency difference caused by mismatching of each frequency modulation NMOS tube:
Firstly, disconnecting the current of an N-th frequency modulation NMOS tube NnM corresponding to the highest bit N, conducting the current of each frequency modulation NMOS tube corresponding to the rest low bits and a first mirror NMOS tube N1MA, and recording the frequency f n of the square wave output by the output end VOUT of the programmable frequency generator at the moment; then, the current of an N-th frequency modulation NMOS tube NnM corresponding to the highest bit N is conducted, the currents of all frequency modulation NMOS tubes corresponding to the rest low bits and a first mirror NMOS tube N1MA are disconnected, the frequency f nT of the square wave output by the output end VOUT of the programmable frequency generator at the moment is recorded, and the frequency difference of f n-fnT is recorded as f Δn;
The current of the N-th frequency modulation NMOS tube NnM and the (N-1) th frequency modulation NMOS tube N (N-1) M corresponding to the highest N and the next highest N-1 is disconnected, the currents of the other frequency modulation NMOS tubes corresponding to the lower bits and the first mirror NMOS tube N1MA are conducted, and the frequency f n-1 of the square wave output by the output end VOUT of the programmable frequency generator at the moment is recorded; then keeping the current of an N-th frequency modulation NMOS tube NnM corresponding to the highest order N off, switching on the current of an N-1-th frequency modulation NMOS tube N (N-1) M corresponding to the next highest order N-1, switching off the currents of all the frequency modulation NMOS tubes corresponding to the rest low orders and a first mirror NMOS tube N1MA, recording the frequency f (n-1)T of the square wave output by the output end VOUT of the programmable frequency generator at the moment, and recording the frequency difference of f (n-1)-f(n-1)T as f Δ(n-1);
The measurement of the remaining bits is analogized in sequence until the measurement completes the frequency difference f Δi for each bit, (i=1, 2, … …, n);
S22, when the programmable frequency generator works, when a corresponding bit current mirror of at least one frequency modulation NMOS tube is used, a (k-1) th correction enabling signal CALEN (k-1) of a (k-1) th correction control NMOS tube NC (k-1) C gate end of the calibration circuit is configured to be low level 0, and correction enabling signals of gate ends of other correction control NMOS tubes are configured to be at least one high level 1, so that the calibration circuit is controlled to subtract corresponding frequency difference; the total frequency difference to be subtracted by the correction circuit is the sum of the frequencies to be subtracted of the corresponding bit current mirrors of all the frequency modulation NMOS tubes to be used;
When the highest n current mirror corresponding to the nth frequency modulation NMOS tube NnM is used, the calibration circuit needs to be controlled to enable the output frequency minus the frequency to be 1/2*f Δn; when the N-1 th FM NMOS tube N (N-1) M is used, the calibration circuit is controlled to make the subtracted frequency of the output frequency be 1/2 x (f Δ(n-1)-1/2*fΔn), and so on, and when the t-th FM NMOS tube NtM is used, the calibration circuit is controlled to make the subtracted frequency of the output frequency be
Taking n=10 as an example, when the output of the Programmable Frequency Generator (PFG) corresponds to the input 11,1100,0011, the frequency error that the calibration circuit needs to subtract is as follows:
1/2*fΔ10
+1/2*(fΔ9 -1/2*fΔ10)
+1/2*(fΔ8 -1/2*fΔ9-1/4*fΔ10)
+1/2*(fΔ7 -1/2*fΔ8-1/4*fΔ9-1/8*fΔ10)
+1/2*(fΔ2 -1/2*fΔ3-1/4*fΔ4-1/8*fΔ5-1/16*fΔ6-1/32*fΔ7-1/64*fΔ8-1/128*fΔ9-1/256*fΔ10)
+1/2*(fΔ1 -1/2*fΔ2-1/4*fΔ3-1/8*fΔ4-1/16*fΔ5-1/32*fΔ6-1/64*fΔ7-1/128*fΔ8-1/256*fΔ9-1/512*fΔ10).
The calibration method of the Programmable Frequency Generator (PFG) can greatly reduce the total area of a circuit and save the cost of the circuit.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather to enable any modification, equivalent replacement, improvement or the like to be made within the spirit and principles of the invention.

Claims (9)

1. The programmable frequency generator is characterized by comprising a current generation circuit, a mirror current circuit, a ring-shaped oscillating circuit and a calibration circuit;
the current generation circuit comprises a second PMOS tube (P2) and a first NMOS tube (N1);
The source end of the second PMOS tube (P2) is connected with the working Voltage (VDD), and the drain end of the second PMOS tube is connected with the drain end and the gate end of the first NMOS tube (N1);
The source end of the first NMOS tube (N1) is grounded;
The mirror current circuit comprises a frequency modulation circuit and a third PMOS tube (P3);
The frequency modulation circuit comprises a first frequency modulation NMOS tube (N1M), a second frequency modulation NMOS tube (N2M), …, an N-th frequency modulation NMOS tube (NnM), a first mirror image NMOS tube (N1 MA), a first frequency modulation control NMOS tube (N1 MC), a second frequency modulation control NMOS tube (N2 MC), …, an N-th frequency modulation control NMOS tube (NnMC) and a first mirror image control NMOS tube (N1 MAC);
The drain end of the ith frequency modulation NMOS tube (NiM) is connected with the source end of the ith frequency modulation control NMOS tube (NiMC), n is an integer larger than 1, (i=1, 2, … …, n);
the drain end of the first mirror NMOS tube (N1 MA) is connected with the source end of the first mirror control NMOS tube (N1 MAC);
the gate of the ith frequency modulation control NMOS tube (NiMC) is connected with an ith enabling signal (ENi), and the first mirror image control NMOS tube (N1 MAC) is connected with a basic mirror image enabling signal (EN 1A);
The drain ends of the frequency modulation control NMOS tube and the first mirror image control NMOS tube (N1 MAC) are connected with the drain end and the gate end of the third PMOS tube (P3);
The source end of each frequency modulation NMOS tube and the source end of the first mirror NMOS tube (N1 MA) are grounded;
the gates of the frequency modulation NMOS tube and the first mirror NMOS tube (N1 MA) are connected with the source end of the second PMOS tube (P2);
the source end of the third PMOS tube (P3) is connected with the working Voltage (VDD);
the gate end of the third PMOS tube (P3) outputs an oscillation control signal to the annular oscillation circuit;
The calibration circuit comprises a zeroth calibration NMOS tube (NC 0), a first calibration NMOS tube (NC 1), a (K-1) th calibration NMOS tube (NC (K-1)), a zeroth calibration control NMOS tube (NC 0C), a first calibration control NMOS tube (NC 1C), a (K-1) th calibration control NMOS tube (NC (K-1) C), wherein K is a positive integer smaller than n;
A j-th correction NMOS tube (NCj) whose drain is connected with the source end of the j-th correction control NMOS tube (NCjC), (j=1, 2, … …, k-1), whose gate is connected with the j-th correction enable signal CALEN (j), and whose drain is connected with the drain end and gate end of the third PMOS tube (P3);
the source end of each correction NMOS tube is grounded;
the gate end of each correction NMOS tube is connected with the source end of the second PMOS tube (P2).
2. A programmable frequency generator as claimed in claim 1, wherein,
The total width-to-length ratio of each frequency modulation NMOS tube and the first mirror NMOS tube (N1 MA) in the mirror current circuit is designed asThe width-to-length ratio (W/L) n corresponding to the n-th frequency modulation NMOS tube (NnM) with the highest n is/>The (N-1) th frequency modulation NMOS tube (N (N-1) M) of the next highest order N-1 has a width-to-length ratio (W/L) n-1 of/>The width-to-length ratio of the rest low bits is 1/2 of the width-to-length ratio corresponding to the previous bit of the first frequency modulation NMOS tube until the width-to-length ratio (W/L) 1 of the first frequency modulation NMOS tube (N1M) at the lowest bit is/>In addition, the width-to-length ratio of the first mirror NMOS tube (N1 MA) is also/>
The calibration circuit has a zero-th calibration NMOS tube (NC 0), a first calibration NMOS tube (NC 1), a (K-1) -th calibration NMOS tube (NC (K-1)), and the aspect ratio of the calibration NMOS tube is doubled in sequence.
3. A programmable frequency generator as claimed in claim 2, characterized in that,
The sum of the width-to-length ratios of the zeroth correction NMOS tube (NC 0), the first correction NMOS tube (NC 1), the (K-1) th correction NMOS tube (NC (K-1)) is larger than the width-to-length ratio of the first NMOS tube (N1), and smaller than
4. A programmable frequency generator as claimed in claim 3, characterized in that,
The width-to-length ratio of the zeroth correction NMOS tube (NC 0) is smaller than that of the first frequency modulation NMOS tube (N1M);
The aspect ratio of the (K-1) th correction NMOS tube (NC (K-1)) is less than 2 n-2.
5. A programmable frequency generator as defined in claim 4, wherein,
The gate end of each correction control NMOS tube in the correction circuit is respectively connected with the output of an AND gate (AND);
Each AND gate (AND) has one input for receiving a correction enable signal (CALEN) AND another input for receiving a correction select signal (CAL (k-1:0)).
6. A programmable frequency generator as claimed in claim 1, wherein,
The current generation circuit further comprises a zeroth PMOS tube (P0), a first PMOS tube (P1), a zeroth NMOS tube (N0), a zeroth resistor (R0) and an operational amplifier (OP);
The source ends of the zeroth PMOS tube (P0) and the first PMOS tube (P1) are connected with the working Voltage (VDD);
the gates of the zeroth PMOS tube (P0), the first PMOS tube (P1) and the second PMOS tube (P2) are connected with the output of the operational amplifier (OP);
The drain end of the zeroth PMOS tube (P0) is short-circuited with the drain end and the gate end of the zeroth NMOS tube (N0), and the input of the operational amplifier (OP) is negative;
The drain end of the first PMOS tube (P1) is connected with one ends of the input positive resistor and the zero resistor (R0) of the operational amplifier (OP);
the source end of the zeroth NMOS tube (N0) and the other end of the zeroth resistor (R0) are grounded.
7. A programmable frequency generator as claimed in claim 1, wherein,
The annular oscillating circuit comprises a fourth PMOS tube (P4), a fifth PMOS tube (P5), a sixth PMOS tube (P6), a seventh PMOS tube (P7), a third NMOS tube (N3), a fourth NMOS tube (N4), a fifth NMOS tube (N5), a sixth NMOS tube (N6), a zeroth capacitor (C0), a first capacitor (C1), a second capacitor (C2) and a Buffer (BUF);
The source ends of the fourth PMOS tube (P4), the fifth PMOS tube (P5), the sixth PMOS tube (P6) and the seventh PMOS tube (P7) are connected with the working Voltage (VDD), and the gate ends of the third PMOS tube (P3);
The gate of the third NMOS tube (N3) is connected with the drain end of the sixth PMOS tube (P6), the drain end of the fifth NMOS tube (N5) and one end of the second capacitor (C2);
A gate of the fourth NMOS tube (N4) is connected with a drain end of the fourth PMOS tube (P4), a drain end of the third NMOS tube (N3) and one end of a zeroth capacitor (C0);
A gate of the fifth NMOS tube (N5) is connected with a drain end of the fifth PMOS tube (P5), a drain end of the fourth NMOS tube (N4) and one end of the first capacitor (C1);
the source ends of the third NMOS tube (N3), the fourth NMOS tube (N4), the fifth NMOS tube (N5) and the sixth NMOS tube (N6) are grounded, and the other ends of the zeroth capacitor (C0), the first capacitor (C1) and the second capacitor (C2) are grounded;
The drain end of the seventh PMOS tube (P7) and the drain end of the sixth NMOS tube (N6) are connected with the input end of the Buffer (BUF),
The Buffer (BUF) output acts as a programmable frequency generator output (VOUT).
8. A programmable frequency generator as claimed in claim 7, characterized in that,
The capacitance values of the zeroth capacitor (C0), the first capacitor (C1) and the second capacitor (C2) are the same.
9. A method of calibrating a programmable frequency generator according to any of claims 1 to 8, comprising the steps of:
S1, calibrating a programmable frequency generator before the programmable frequency generator works, and configuring a (K-1) th correction enabling signal (CALEN (K-1)) of a gate end of a (K-1) th correction control NMOS tube (NC (K-1) C) of a calibration circuit to be high level 1, and configuring correction enabling signals of gate ends of other correction control NMOS tubes to be low level 0 before the programmable frequency generator calibrates;
s2, calibrating a programmable frequency generator, which comprises the following steps:
s21, measuring PFG frequency difference caused by mismatching of each frequency modulation NMOS tube:
firstly, disconnecting the current of an N-th frequency modulation NMOS tube (NnM) corresponding to the highest bit N, conducting the current of each frequency modulation NMOS tube corresponding to the rest low bits and a first mirror NMOS tube (N1 MA), and recording the frequency f n of square wave output by an output end (VOUT) of a programmable frequency generator at the moment; then, the current of an N-th frequency modulation NMOS tube (NnM) corresponding to the highest bit N is conducted, the currents of all frequency modulation NMOS tubes corresponding to the rest low bits and a first mirror NMOS tube (N1 MA) are disconnected, the frequency f nT of square wave output by an output end (VOUT) of the programmable frequency generator at the moment is recorded, and the frequency difference of f n-fnT is recorded as f Δn;
Disconnecting the current of the N-th frequency modulation NMOS tube (NnM) and the (N-1) th frequency modulation NMOS tube (N (N-1) M) corresponding to the highest order N and the next highest order N-1, conducting the current of each frequency modulation NMOS tube and the first mirror NMOS tube (N1 MA) corresponding to the rest low order, and recording the frequency f n-1 of the square wave output by the output end (VOUT) of the programmable frequency generator at the moment; then keeping the current of an N-th frequency modulation NMOS tube (NnM) corresponding to the highest level N off, switching on the current of an N-1 th frequency modulation NMOS tube (N (N-1) M) corresponding to the next highest level N-1, switching off the currents of all the frequency modulation NMOS tubes corresponding to the rest low levels and a first mirror NMOS tube (N1 MA), recording the frequency f (n-1)T of square wave output by the output end (VOUT) of the programmable frequency generator at the moment, and recording the frequency difference of f (n-1)-f(n-1)T as f Δ(n-1);
The measurement of the remaining bits is analogized in sequence until the measurement completes the frequency difference f Δi for each bit, (i=1, 2, … …, n);
S22, when the programmable frequency generator works, when a corresponding bit current mirror of at least one frequency modulation NMOS tube is used, a (K-1) th correction enabling signal (CALEN (K-1)) of a (K-1) th correction control NMOS tube (NC (K-1) C) of a correction circuit is configured to be low-level 0, and correction enabling signals of the gate ends of the rest correction control NMOS tubes are controlled to be at least one high-level 1, so that the correction circuit is controlled to subtract corresponding frequency difference; the total frequency difference to be subtracted by the correction circuit is the sum of the frequencies to be subtracted of the corresponding bit current mirrors of all the frequency modulation NMOS tubes to be used;
When the highest n current mirror corresponding to the n-th frequency modulation NMOS tube (NnM) is used, a calibration circuit needs to be controlled to enable the frequency subtracted by the output frequency to be 1/2*f Δn; when the N-1 th FM NMOS tube (N (N-1) M) is used, the calibration circuit is controlled to make the subtracted frequency of the output frequency be 1/2 x (f Δ(n-1)-1/2*fΔn), and so on, and when the t-th FM NMOS tube NtM is used, the calibration circuit is controlled to make the subtracted frequency of the output frequency be
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