CN114679157A - Programmable frequency generator and calibration method thereof - Google Patents
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Abstract
The invention discloses a programmable frequency generator.A calibration circuit is added in a circuit, the digit k of the calibration circuit is less than the digit n of a frequency modulation circuit, so that the digit of the frequency modulation circuit and the width-length ratio of a first mirror image NMOS (N-channel metal oxide semiconductor) tube can be reduced, the area of the frequency modulation circuit is greatly reduced, and the frequency output by the programmable frequency generator is calibrated by the calibration circuit with less digit and total width-length ratio, so that the programmable frequency generator has smaller chip area and the cost for calibrating the programmable frequency generator is saved while the range and the precision of the frequency output by the programmable frequency generator are ensured. The invention also discloses a calibration method of the programmable frequency generator.
Description
Technical Field
The present invention relates to semiconductor integrated circuit oscillator technology, and more particularly, to a programmable frequency generator and a calibration method thereof.
Background
The Programmable Frequency Generator (PFG) can adjust the output frequency through software control and can be used for an atomizer and other applications, and the closer the frequency of an atomizing sheet of the atomizer is to the output frequency of the PFG, the better the generated atomizing effect is. Because the frequency of different atomizing plates is different and the frequency of the atomizing plates is changed by the change of the working environment, the output frequency of the PFG needs to be adjustable within a certain range and the step (step length) in frequency following can be changed uniformly, so that the atomizer can produce the best use effect.
As shown in fig. 1, the principle of a general Programmable Frequency Generator (PFG) circuit without calibration is as follows: the input current I1 is VGS/R0, VGS is the gate-source voltage of the zeroth NMOS transistor on the left, R0 is the resistance of the 0 th resistor R0 in fig. 1, and the input current I1 passes through the first frequency modulation NMOS transistor N1M, the second frequency modulation NMOS transistors N2M, …, the mth frequency modulation NMOS transistors NmM and NmMA second NMOS tube N2 and the like are output to a third PMOS tube P3 in a mirror image manner, then are mirrored to ring oscillator circuits consisting of fourth PMOS tubes P4 to seventh PMOS tubes P7, third NMOS tubes N3 to sixth NMOS tube N6, a zero capacitor C0 to a second capacitor C2 and the like to generate oscillation, and finally a square wave is output by an output end VOUT of a Programmable Frequency Generator (PFG), wherein the frequency of the square wave is in direct proportion to the frequency of VOUT
Wherein i is 1, 2, 3, …, m, IN2 is a drain current of the second NMOS transistor N2, IiM is a current flowing through the ith fm NMOS transistor NiM when turned on, bi is a weighting coefficient of IiM, bi is 1 when the ith enable signal Eni is high voltage, bi is 0 when the ith enable signal Eni is 0V, and the capacitance values of the zeroth capacitor C0, the first capacitor C1 and the second capacitor C2 are equal, m is an integer greater than 1 (m may be 8 or 9 according to the application), and i is a positive integer less than or equal to m;
the width-to-length ratio of the first fm NMOS transistor N1M,
the width-to-length ratio of the second fm NMOS transistor N2M,
is the width-length ratio of the (M-1) th frequency modulation NMOS tube N (M-1) M,
each fm NMOS NmM is used to adjust the range of the output frequency of the Programmable Frequency Generator (PFG).
From the above equation, the frequency step (step) of the square wave is proportional to
In the electric circuit, the electric current is supplied to the power supply,
this value is usually small. Taking a Programmable Frequency Generator (PFG) with an output frequency of 2.4MHz as an example, if the frequency step (step) is 1KHz, then
This requires the second NMOS transistor N2 to have a large size in order to meet the requirement of MOS transistor mismatch, which results in a large total area of the first fm NMOS transistor N1M to the mth fm NMOS transistor NmM and the second NMOS transistor N2, which is not favorable for saving the chip cost.
Disclosure of Invention
The invention provides a programmable frequency generator and a calibration method thereof, which ensure the range and the precision of the frequency output by the programmable frequency generator, ensure that the programmable frequency generator has smaller chip area and save the cost for calibrating the programmable frequency generator.
In order to solve the above technical problem, the present invention provides a programmable frequency generator, which comprises a current generating circuit, a mirror current circuit, a ring oscillator circuit and a calibration circuit;
the current generating circuit comprises a second PMOS tube P2 and a first NMOS tube N1;
a source terminal of the second PMOS transistor P2 is connected to the operating voltage VDD, and a drain terminal thereof is connected to the drain terminal and the gate terminal of the first NMOS transistor N1;
the source end of the first NMOS transistor N1 is grounded;
the mirror current circuit comprises a frequency modulation circuit, a calibration circuit and a third PMOS tube P3;
the frequency modulation circuit comprises a first frequency modulation NMOS tube N1M, a second frequency modulation NMOS tube N2M, …, an nth frequency modulation NMOS tube NnM, a first mirror image NMOS tube N1MA, a first frequency modulation control NMOS tube N1MC, a second frequency modulation control NMOS tube N2MC, a second mirror image NMOS tube …, an nth frequency modulation control NMOS tube NnMC and a first mirror image control NMOS tube N1 MAC;
the drain end of an ith frequency modulation NMOS tube NiM is connected with the source end of an ith frequency modulation control NMOS tube NiMC, n is an integer larger than 1, (i is 1, 2, … …, n);
the drain end of the first mirror image NMOS tube N1MA is connected with the MAC source end of the first mirror image control NMOS tube N1;
the grid end of an ith frequency modulation control NMOS tube NiMC is connected with an ith enabling signal ENi, and a first mirror image control NMOS tube N1MAC is connected with a basic mirror image enabling signal EN 1A;
the drain end of each frequency modulation control NMOS tube and the drain end and the gate end of the first mirror image control NMOS tube N1MAC are connected with the drain end and the gate end of a third PMOS tube P3;
the source ends of each frequency modulation NMOS tube and the first mirror image NMOS tube N1MA are grounded;
the grid ends of each frequency modulation NMOS tube and the first mirror image NMOS tube N1MA are connected with the source end of a second PMOS tube P2;
the source end of the third PMOS pipe P3 is connected with the working voltage VDD;
the gate terminal of the third PMOS tube P3 outputs an oscillation control signal to the ring oscillation circuit;
the calibration circuit comprises a zeroth correction NMOS tube NC0, a first correction NMOS tube NC1, ·, a (K-1) th correction NMOS tube NC (K-1), a zeroth correction control NMOS tube NC0C, a first correction control NMOS tube NC1C, ·, a (K-1) th correction control NMOS tube NC (K-1) C, wherein K is a positive integer smaller than n;
a jth calibration NMOS NCj, having a drain terminal connected to the source terminal of the jth calibration control NMOS NCjC, (j ═ 1, 2, … …, k-1), a gate terminal connected to a jth calibration enable signal calen (j), and a drain terminal connected to the drain terminal and the gate terminal of the third PMOS P3;
the source end of each correction NMOS tube is grounded;
the gate terminal of each correction NMOS transistor is connected with the source terminal of the second PMOS transistor P2.
Preferably, the total width-to-length ratio of each frequency modulation NMOS transistor and the first mirror NMOS transistor N1MA in the mirror current circuit is designed to be
Width-to-length ratio (W/L) corresponding to the nth frequency modulation NMOS tube NnM of the highest bit nnIs composed of
The width-to-length ratio corresponding to the (N-1) th frequency modulation NMOS transistor N (N-1) M of the next highest N-1 is (W/L)n-1Is composed of
The width-length ratios of the other low-order bits are 1/2 of the width-length ratio corresponding to the previous frequency modulation NMOS tube in turn, and the width-length ratios (W/L) of the first frequency modulation NMOS tube N1M to the lowest order bit1Is composed of
In addition, the width-to-length ratio of the first mirror image NMOS transistor N1MA is also
The width-to-length ratios of the zero correction NMOS tube NC0, the first correction NMOS tube NC1, the (K-1) correction NMOS tube NC (K-1) are doubled in sequence.
Preferably, the sum of the width-to-length ratios of the zeroth correction NMOS transistor NC0, the first correction NMOS transistor NC 1.. and the (K-1) th correction NMOS transistor NC (K-1) is greater than the width-to-length ratio of the first NMOS transistor N1 and less than the width-to-length ratio of the first NMOS transistor N1
Preferably, the width-to-length ratio of the zeroth correction NMOS transistor NC0 is smaller than the width-to-length ratio of the first fm NMOS transistor N1M;
the width-to-length ratio of the (K-1) th correction NMOS tube NC (K-1) is less than
Preferably, the gate end of each correction control NMOS tube in the correction circuit is connected to the output of an AND gate AND, respectively;
each AND gate AND has one input terminal connected to the calibration enable signal CALENN AND the other input terminal connected to the calibration select signal CAL (k-1: 0).
Preferably, the current generating circuit further includes a zeroth PMOS transistor P0, a first PMOS transistor P1, a zeroth NMOS transistor N0, a zeroth resistor R0, and an operational amplifier OP;
the source ends of the zeroth PMOS tube P0 and the first PMOS tube P1 are connected with the working voltage VDD;
the grid ends of a zeroth PMOS pipe P0, a first PMOS pipe P1 and a second PMOS pipe P2 are connected with the output of the operational amplifier OP;
the drain end of the zeroth PMOS tube P0 is in short circuit with the drain end and the gate end of the zeroth NMOS tube N0 and the input negative of the operational amplifier OP;
the drain end of the first PMOS tube P1 is connected with the input positive end of the operational amplifier OP and one end of a zero resistor R0;
the source end of the zeroth NMOS transistor N0 and the other end of the zeroth resistor R0 are grounded.
Preferably, the ring oscillator circuit includes a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a zero capacitor C0, a first capacitor C1, a second capacitor C2, and a buffer BUF;
the source ends of a fourth PMOS tube P4, a fifth PMOS tube P5, a sixth PMOS tube P6 and a seventh PMOS tube P7 are connected with the working voltage VDD, and the gate end is connected with the gate end of a third PMOS tube P3;
the grid electrode of the third NMOS tube N3 is connected with the drain end of the sixth PMOS tube P6, the drain end of the fifth NMOS tube N5 and one end of the second capacitor C2;
the grid electrode of the fourth NMOS tube N4 is connected with the drain electrode of the fourth PMOS tube P4, the drain electrode of the third NMOS tube N3 and one end of a zero capacitor C0;
a gate terminal of the fifth NMOS transistor N5 is connected to the drain terminal of the fifth PMOS transistor P5, the drain terminal of the fourth NMOS transistor N4 and one end of the first capacitor C1;
the source ends of a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5 and a sixth NMOS tube N6, the other end of a zero capacitor C0, the other end of a first capacitor C1 and the other end of a second capacitor C2 are grounded;
the drain terminal of the seventh PMOS tube P7 and the drain terminal of the sixth NMOS tube N6 are connected with the input terminal of the buffer BUF,
the output terminal of the buffer BUF is used as the output terminal VOUT of the programmable frequency generator.
Preferably, the capacitance values of the zeroth capacitor C0, the first capacitor C1 and the second capacitor C2 are the same.
In order to solve the above technical problem, the calibration method of the programmable frequency generator provided by the present invention comprises the following steps:
s1, before the programmable frequency generator works, calibrating the programmable frequency generator, before calibrating the programmable frequency generator, configuring a (k-1) th calibration enable signal CALENN (k-1) of a gate end of a (k-1) th calibration control NMOS tube NC (k-1) C of a calibration circuit into a high level 1, and configuring calibration enable signals of gate ends of other correction control NMOS tubes into a low level 0;
s2, calibrating the programmable frequency generator, comprising the following steps:
s21, measuring PFG frequency difference caused by mismatching of all frequency modulation NMOS tubes:
the current of the nth frequency modulation NMOS tube NnM corresponding to the highest bit N is firstly cut off, the currents of the frequency modulation NMOS tubes corresponding to the rest lower bits and the first mirror image NMOS tube N1MA are conducted, and the frequency f of the square wave output by the output end VOUT of the programmable frequency generator at the moment is recordedn(ii) a Then the current of the nth frequency modulation NMOS tube NnM corresponding to the highest bit N is conducted, the current of each frequency modulation NMOS tube corresponding to the rest lower bits and the current of the first mirror image NMOS tube N1MA are disconnected, and the frequency f of the square wave output by the output end VOUT of the programmable frequency generator at the moment is recordednTRecord fn-fnTFrequency difference of fΔn；
Then the current of the nth frequency modulation NMOS tube NnM and the (N-1) th frequency modulation NMOS tube N (N-1) M corresponding to the highest bit N and the next highest bit N-1 is cut off, the current of each frequency modulation NMOS tube corresponding to the rest lower bits and the current of the first mirror image NMOS tube N1MA are conducted, and the frequency f of the square wave output by the output end VOUT of the programmable frequency generator at the moment is recordedn-1(ii) a Then keeping the current of the nth frequency modulation NMOS tube NnM corresponding to the highest bit N to be switched off, switching on the current of the nth-1 frequency modulation NMOS tube N (N-1) M corresponding to the second highest bit N-1, switching off the current of each frequency modulation NMOS tube corresponding to the rest lower bits and the first mirror image NMOS tube N1MA, and recording the frequency f of the square wave output by the output end VOUT of the programmable frequency generator at the moment(n-1) T, record f(n-1)-f(n-1) frequency difference of T is fΔ(n-1)；
The measurement of the rest bits is analogized in turn until the frequency difference f of each bit is measuredΔi，(i＝1，2，……，n)；
S22, when the programmable frequency generator works and a corresponding bit current mirror of at least one frequency modulation NMOS tube is used, configuring a (k-1) th correction enabling signal CALENN (k-1) of a (k-1) th correction control NMOS tube NC (k-1) C gate end of a calibration circuit to be low level 0, and controlling the correction enabling signals of the gate ends of the other correction control NMOS tubes to be at least one high level 1, so as to control the calibration circuit to subtract a corresponding frequency difference; the total frequency difference required to be subtracted by the correction circuit is the sum of the frequencies required to be subtracted of the corresponding bit current mirrors of the frequency modulation NMOS tubes required to be used;
when the highest n-bit current mirror corresponding to the nth fm NMOS NnM is used, the calibration circuit needs to be controlled to reduce the output frequency by 1/2 × fΔn(ii) a When using the next higher N-1 current mirror corresponding to the N-1 frequency modulation NMOS transistor N (N-1) M, the calibration circuit needs to be controlled to make the frequency subtracted by the output frequency 1/2 (f)Δ(n-1)-1/2*fΔn) By analogy, when the tth tuning NMOS NtM corresponding to the tth current mirror is used, the calibration circuit needs to be controlled to subtract the output frequency to obtain the frequency
(t＝1，2…，n-1)。
According to the Programmable Frequency Generator (PFG), the calibration circuit is added in the circuit, the number of bits of the calibration circuit is k smaller than the number of bits N of the frequency modulation circuit, so that the number of bits of the frequency modulation circuit and the width-length ratio of the first mirror NMOS tube N1MA can be reduced, the area of the frequency modulation circuit is greatly reduced, the frequency output by the Programmable Frequency Generator (PFG) is calibrated through the calibration circuit with the smaller number of bits and the total width-length ratio, the range and the precision of the frequency output by the Programmable Frequency Generator (PFG) are guaranteed, meanwhile, the Programmable Frequency Generator (PFG) has a smaller chip area, and the cost of calibrating the Programmable Frequency Generator (PFG) is saved.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the present invention are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a circuit diagram of a prior art frequency programmable frequency generator without calibration;
FIG. 2 is a circuit diagram of one embodiment of a programmable frequency generator of the present invention;
FIG. 3 is a circuit diagram of a calibration circuit for one embodiment of the programmable frequency generator of the present invention;
FIG. 4 is a circuit diagram of a ring oscillator circuit according to an embodiment of the programmable frequency generator of the present invention.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
Example one
As shown in fig. 2, the Programmable Frequency Generator (PFG) includes a current generating circuit, a mirror current circuit, a ring oscillator circuit and a calibration circuit;
the current generating circuit comprises a second PMOS tube P2 and a first NMOS tube N1;
the source end of the second PMOS tube P2 is connected with the working voltage VDD, and the drain end of the second PMOS tube P2 is connected with the drain end and the gate end of the first NMOS tube N1;
the source end of the first NMOS transistor N1 is grounded;
the mirror current circuit comprises a frequency modulation circuit, a calibration circuit and a third PMOS tube P3;
the frequency modulation circuit comprises a first frequency modulation NMOS tube N1M, a second frequency modulation NMOS tube N2M, …, an nth frequency modulation NMOS tube NnM, a first mirror image NMOS tube N1MA, a first frequency modulation control NMOS tube N1MC, a second frequency modulation control NMOS tube N2MC, a second frequency modulation control NMOS tube …, an nth frequency modulation control NMOS tube NnMC, and a first mirror image control NMOS tube N1MAC；
The drain end of an ith frequency modulation NMOS tube NiM is connected with the source end of an ith frequency modulation control NMOS tube NiMC, n is an integer larger than 1, (i is 1, 2, … …, n);
the drain end of the first mirror image NMOS transistor N1MA is connected with the first mirror image control NMOS transistor N1MAC source end;
the gate terminal of the ith frequency modulation control NMOS tube NiMC is connected with the ith enable signal ENi, and the first mirror image control NMOS tube N1MAC is connected with a basic image enable signal EN 1A;
each frequency modulation control NMOS transistor and the first mirror image control NMOS transistor N1MAThe drain end of the transistor C is connected with the drain end and the gate end of a third PMOS transistor P3;
the source ends of each frequency modulation NMOS tube and the first mirror image NMOS tube N1MA are grounded;
the grid ends of each frequency modulation NMOS tube and the first mirror image NMOS tube N1MA are connected with the source end of a second PMOS tube P2;
the source end of the third PMOS pipe P3 is connected with the working voltage VDD;
the gate terminal of the third PMOS tube P3 outputs an oscillation control signal to the ring oscillation circuit;
as shown in fig. 3, the calibration circuit includes a zeroth correction NMOS transistor NC0, a first correction NMOS transistor NC1, ·, a (K-1) th correction NMOS transistor NC (K-1), a zeroth correction control NMOS transistor NC0C, a first correction control NMOS transistor NC1C,. and a (K-1) th correction control NMOS transistor NC (K-1) C, where K is a positive integer less than n;
a jth correction NMOS NCj having a drain connected to the source of the jth correction control NMOS NCjC, (j ═ 1, 2, … …, k-1), a gate connected to a jth correction enable signal calen (j), and a drain connected to the drain and gate of a third PMOS transistor P3;
the source end of each correction NMOS tube is grounded;
the gate terminal of each correction NMOS transistor is connected with the source terminal of the second PMOS transistor P2.
The Programmable Frequency Generator (PFG) according to the first embodiment is a mirror current circuit composed of a first frequency modulation NMOS transistor N1M, a second frequency modulation NMOS transistor N2M, …, an nth frequency modulation NMOS transistor NnM, a first mirror image NMOS transistor N1MA, a first frequency modulation control NMOS transistor N1MC, a second frequency modulation control NMOS transistor N2MC, …, an nth frequency modulation control NMOS transistor nmc, a first mirror image control NMOS transistor N1MAC, and the like, wherein the first frequency modulation control NMOS transistor N1MC, the second frequency modulation control NMOS transistor N2MC, …, the nth frequency modulation control NMOS transistor nmc, and the first mirror image control NMOS transistor N1MAC are used for controlling the on-off of currents of corresponding branches; the calibration circuit is composed of a zeroth correction NMOS tube NC0, a first correction NMOS tube NC1, a second correction NMOS tube NC (K-1), a zeroth correction control NMOS tube NC0C, a first correction control NMOS tube NC1C, a second correction control NMOS tube NC (K-1) C and the like.
In the Programmable Frequency Generator (PFG) according to the first embodiment, the calibration circuit is added to the circuit, and the number of bits of the calibration circuit is k smaller than the number of bits N of the frequency modulation circuit, so that the number of bits of the frequency modulation circuit and the width-to-length ratio of the first mirror NMOS transistor N1MA can be reduced, the area of the frequency modulation circuit can be greatly reduced, and the frequency output by the Programmable Frequency Generator (PFG) is calibrated by the calibration circuit with the smaller number of bits and the smaller total width-to-length ratio, so that the Programmable Frequency Generator (PFG) has a smaller chip area while the range and the accuracy of the frequency output by the Programmable Frequency Generator (PFG) are ensured, and the cost for calibrating the Programmable Frequency Generator (PFG) is saved.
Example two
Based on the Programmable Frequency Generator (PFG) of the first embodiment, the total width-to-length ratio of each frequency modulation NMOS transistor and the first mirror NMOS transistor N1MA in the mirror current circuit is designed to be
Width-to-length ratio (W/L) corresponding to the nth frequency modulation NMOS tube NnM of the highest bit nnIs composed of
The width-to-length ratio corresponding to the (N-1) th frequency modulation NMOS transistor N (N-1) M of the next highest N-1 is (W/L)n-1Is composed of
The width-length ratios of the other low-order bits are 1/2 of the width-length ratio corresponding to the previous frequency modulation NMOS tube in turn, and the width-length ratios (W/L) of the first frequency modulation NMOS tube N1M to the lowest order bit1Is composed of
In addition, the width-to-length ratio of the first mirror NMOS transistor N1MA is also
The width-to-length ratios of the zero correction NMOS tube NC0, the first correction NMOS tube NC1, the (K-1) correction NMOS tube NC (K-1) are doubled in sequence.
Preferably, the sum of the width-to-length ratios of the zeroth correction NMOS transistor NC0, the first correction NMOS transistor NC 1.. and the (K-1) th correction NMOS transistor NC (K-1) is greater than the width-to-length ratio of the first NMOS transistor N1 and less than the width-to-length ratio of the first NMOS transistor N1
Preferably, the width-to-length ratio of the zeroth correction NMOS transistor NC0 is smaller than the width-to-length ratio of the first fm NMOS transistor N1M;
the width-to-length ratio of the (K-1) th correction NMOS tube NC (K-1) is less than
Preferably, the gate end of each correction control NMOS tube in the correction circuit is connected to the output of an AND gate AND, respectively;
each AND gate AND has one input terminal connected to the calibration enable signal CALENN AND the other input terminal connected to the calibration select signal CAL (k-1: 0).
The Programmable Frequency Generator (PFG) of the second embodiment can be determined by matching the resistor in the current generating circuit and the capacitor in the ring oscillator circuit in circuit design
The width-to-length ratio (W/L) of the first frequency modulation NMOS tube N1M at the lowest position1Is composed of
In addition, the width-to-length ratio of the first mirror NMOS transistor N1MA is also
The same effect is to make the width-to-length ratio W/L of the highest bit and the total W/L size of all lower bits the same during calibration.
EXAMPLE III
Based on the Programmable Frequency Generator (PFG) of the first embodiment, the current generating circuit further includes a zeroth PMOS transistor P0, a first PMOS transistor P1, a zeroth NMOS transistor N0, a zeroth resistor R0 and an operational amplifier OP;
the source ends of the zeroth PMOS tube P0 and the first PMOS tube P1 are connected with the working voltage VDD;
the grid ends of a zeroth PMOS pipe P0, a first PMOS pipe P1 and a second PMOS pipe P2 are connected with the output of the operational amplifier OP;
the drain end of the zeroth PMOS tube P0 is in short circuit with the drain end and the gate end of the zeroth NMOS tube N0 and the input negative of the operational amplifier OP;
the drain end of the first PMOS tube P1 is connected with the input positive end of the operational amplifier OP and one end of a zero resistor R0;
the source end of the zeroth NMOS transistor N0 and the other end of the zeroth resistor R0 are grounded.
The Programmable Frequency Generator (PFG) of the third embodiment comprises a current generating circuit including a zeroth PMOS transistor P0, a first PMOS transistor P1, a second PMOS transistor P2, a zeroth NMOS transistor N0, a first NMOS transistor N1, a zeroth resistor R0, and an operational amplifier OP.
Example four
Based on the Programmable Frequency Generator (PFG) of the first embodiment, as shown in fig. 4, the ring oscillator circuit includes a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a zero capacitor C0, a first capacitor C1, a second capacitor C2, and a buffer BUF;
the source ends of a fourth PMOS tube P4, a fifth PMOS tube P5, a sixth PMOS tube P6 and a seventh PMOS tube P7 are connected with the working voltage VDD, and the gate end is connected with the gate end of a third PMOS tube P3;
the grid electrode of the third NMOS tube N3 is connected with the drain electrode of the sixth PMOS tube P6, the drain electrode of the fifth NMOS tube N5 and one end of the second capacitor C2;
the grid electrode of the fourth NMOS tube N4 is connected with the drain electrode of the fourth PMOS tube P4, the drain electrode of the third NMOS tube N3 and one end of a zero capacitor C0;
a gate terminal of the fifth NMOS transistor N5 is connected to the drain terminal of the fifth PMOS transistor P5, the drain terminal of the fourth NMOS transistor N4 and one end of the first capacitor C1;
the source ends of a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5 and a sixth NMOS transistor N6, the other end of a zero capacitor C0, the other end of a first capacitor C1 and the other end of a second capacitor C2 are grounded;
the drain terminal of the seventh PMOS tube P7 and the drain terminal of the sixth NMOS tube N6 are connected with the input terminal of the buffer BUF,
the output terminal of the buffer BUF is used as the output terminal VOUT of the programmable frequency generator.
Preferably, the capacitance values of the zeroth capacitor C0, the first capacitor C1 and the second capacitor C2 are the same.
EXAMPLE five
The method of calibrating a Programmable Frequency Generator (PFG) of embodiment two, comprising the steps of:
s1, before the programmable frequency generator works, calibrating the programmable frequency generator, before calibrating the programmable frequency generator, configuring a (k-1) th calibration enable signal CALENN (k-1) of a gate end of a (k-1) th calibration control NMOS tube NC (k-1) C of a calibration circuit into a high level 1, and configuring calibration enable signals of gate ends of other correction control NMOS tubes into a low level 0;
s2, calibrating the programmable frequency generator, comprising the following steps:
s21, measuring PFG frequency difference caused by mismatching of all frequency modulation NMOS tubes:
the current of the nth frequency modulation NMOS tube NnM corresponding to the highest bit N is firstly cut off, the currents of the frequency modulation NMOS tubes corresponding to the rest lower bits and the first mirror image NMOS tube N1MA are conducted, and the frequency f of the square wave output by the output end VOUT of the programmable frequency generator at the moment is recordedn(ii) a Then the current of the nth frequency modulation NMOS tube NnM corresponding to the highest bit N is conducted, the current of each frequency modulation NMOS tube corresponding to the rest lower bits and the current of the first mirror image NMOS tube N1MA are disconnected, and the frequency f of the square wave output by the output end VOUT of the programmable frequency generator at the moment is recordednTRecord fn-fnTFrequency difference of fΔn；
Then the current of the nth frequency modulation NMOS tube NnM and the (N-1) th frequency modulation NMOS tube N (N-1) M corresponding to the highest bit N and the next highest bit N-1 is cut off, the current of each frequency modulation NMOS tube corresponding to the other lower bits and the current of the first mirror image NMOS tube N1MA are conducted, and the output end VOUT of the programmable frequency generator at the moment is recordedFrequency f of square waven-1(ii) a Then keeping the current of the nth frequency modulation NMOS tube NnM corresponding to the highest bit N to be switched off, switching on the current of the nth-1 frequency modulation NMOS tube N (N-1) M corresponding to the second highest bit N-1, switching off the current of each frequency modulation NMOS tube corresponding to the rest lower bits and the first mirror image NMOS tube N1MA, and recording the frequency f of the square wave output by the output end VOUT of the programmable frequency generator at the moment(n-1)TRecord f(n-1)-f(n-1)THas a frequency difference of fΔ(n-1)；
And the measurement of the rest bits is analogized in turn until the frequency difference f of each bit is measuredΔi，(i＝1，2，……，n)；
S22, when the programmable frequency generator works and a corresponding bit current mirror of at least one frequency modulation NMOS tube is used, configuring a (k-1) th correction enabling signal CALENN (k-1) of a (k-1) th correction control NMOS tube NC (k-1) C gate end of a calibration circuit to be low level 0, and controlling the correction enabling signals of the gate ends of the other correction control NMOS tubes to be at least one high level 1, so as to control the calibration circuit to subtract a corresponding frequency difference; the total frequency difference required to be subtracted by the correction circuit is the sum of the frequencies required to be subtracted of the corresponding bit current mirrors of the frequency modulation NMOS tubes required to be used;
when the highest n-bit current mirror corresponding to the nth fm NMOS NnM is used, the calibration circuit needs to be controlled to reduce the output frequency by 1/2 × fΔn(ii) a When using the sub-high N-1 current mirror corresponding to the N-1 th frequency modulation NMOS transistor N (N-1) M, the calibration circuit needs to be controlled to make the frequency subtracted by the output frequency 1/2 x (f)Δ(n-1)-1/2*fΔn) By analogy, when the tth tuning NMOS NtM corresponding to the tth current mirror is used, the calibration circuit needs to be controlled to subtract the output frequency to obtain the frequency
(t＝1，2…，n-1)。
Taking n-10 as an example, when the output of the Programmable Frequency Generator (PFG) corresponds to an input of 11,1100,0011, the frequency error that the calibration circuit needs to subtract is as follows:
1/2*fΔ10
+1/2*(fΔ9-1/2*fΔ10)
+1/2*(fΔ8-1/2*fΔ9-1/4*fΔ10)
+1/2*(fΔ7-1/2*fΔ8-1/4*fΔ9-1/8*fΔ10)
+1/2*(fΔ2-1/2*fΔ3-1/4*fΔ4-1/8*fΔ5-1/16*fΔ6-1/32*fΔ7-1/64*fΔ8-1/128*fΔ9-1/256*fΔ10)
+1/2*(fΔ1-1/2*fΔ2-1/4*fΔ3-1/8*fΔ4-1/16*fΔ5-1/32*fΔ6-1/64*fΔ7-1/128*fΔ8-1/256*fΔ9-1/512*fΔ10)。
the calibration method of the Programmable Frequency Generator (PFG) can greatly reduce the total area of the circuit and save the circuit cost.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (9)
1. A programmable frequency generator is characterized by comprising a current generating circuit, a mirror current circuit, a ring oscillator circuit and a calibration circuit;
the current generation circuit comprises a second PMOS tube (P2) and a first NMOS tube (N1);
a second PMOS tube (P2), the source terminal of which is connected with the working Voltage (VDD), and the drain terminal of which is connected with the drain terminal and the gate terminal of the first NMOS tube (N1);
the source end of the first NMOS tube (N1) is grounded;
the mirror current circuit comprises a frequency modulation circuit, a calibration circuit and a third PMOS tube (P3);
the frequency modulation circuit comprises a first frequency modulation NMOS tube (N1M), a second frequency modulation NMOS tube (N2M), …, an nth frequency modulation NMOS tube (NnM), a first mirror image NMOS tube (N1MA), a first frequency modulation control NMOS tube (N1MC), a second frequency modulation control NMOS tube (N2MC), a …, an nth frequency modulation control NMOS tube (NnMC) and a first mirror image control NMOS tube (N1 MAC);
the drain terminal of the ith frequency modulation NMOS tube (NiM) is connected with the source terminal of the ith frequency modulation control NMOS tube (NiMC), n is an integer larger than 1, (i is 1, 2, … …, n);
the drain end of the first mirror image NMOS tube (N1MA) is connected with the source end of a first mirror image control NMOS tube (N1 MAC);
the grid end of an ith frequency modulation control NMOS tube (NiMC) is connected with an ith enabling signal (ENi), and a first mirror image control NMOS tube (N1MAC) is connected with a basic mirror image enabling signal (EN 1A);
the drain ends of the frequency modulation control NMOS tubes and the first mirror image control NMOS tube (N1MAC) are connected with the drain end and the grid end of a third PMOS tube (P3);
the source ends of each frequency modulation NMOS tube and the first mirror image NMOS tube (N1MA) are grounded;
the grid ends of each frequency modulation NMOS tube and the first mirror image NMOS tube (N1MA) are connected with the source end of the second PMOS tube (P2);
the source end of the third PMOS tube (P3) is connected with the working Voltage (VDD);
the grid end of the third PMOS tube (P3) outputs an oscillation control signal to the annular oscillation circuit;
the calibration circuit comprises a zeroth correction NMOS tube (NC0), a first correction NMOS tube (NC1), a zeroth correction NMOS tube (NC (K-1)), a zeroth correction control NMOS tube (NC0C), a first correction control NMOS tube (NC1C), a zeroth correction control NMOS tube (K-1) and a (K-1) correction control NMOS tube (NC (K-1) C), wherein K is a positive integer smaller than n;
a jth correction NMOS tube (NCj), wherein the drain terminal of the jth correction NMOS tube (NCj) is connected with the source terminal of the jth correction control NMOS tube (NCjC), (j is 1, 2, … …, k-1), the gate terminal of the jth correction NMOS tube is connected with a jth correction enabling signal CALEN (j), and the drain terminal of the jth correction NMOS tube is connected with the drain terminal and the gate terminal of a third PMOS tube (P3);
the source end of each correction NMOS tube is grounded;
the gate terminal of each correction NMOS tube is connected with the source terminal of the second PMOS tube (P2).
2. The programmable frequency generator of claim 1,
the total width-to-length ratio of each frequency modulation NMOS transistor and the first mirror image NMOS transistor (N1MA) in the mirror image current circuit is designed to be
The width-to-length ratio (W/L) corresponding to the nth frequency modulation NMOS tube (NnM) of the highest bit nnIs composed of
The width-to-length ratio corresponding to the (N-1) th frequency modulation NMOS tube (N (N-1) M) of the next highest N-1 is (W/L)n-1Is composed of
The width-length ratios of the other lower positions are 1/2 of the width-length ratio corresponding to the previous frequency modulation NMOS tube in sequence till the width-length ratio (W/L) of the first frequency modulation NMOS tube (N1M) at the lowest position1Is composed of
The width-to-length ratio of the first mirror NMOS transistor (N1MA) is also set to
The width-to-length ratios of the zeroth correction NMOS tube (NC0), the first correction NMOS tube (NC1), and the (K-1) correction NMOS tube (NC (K-1)) of the calibration circuit are doubled in sequence.
3. The programmable frequency generator of claim 2,
the sum of the width-length ratios of the zeroth correction NMOS transistor (NC0), the first correction NMOS transistor (NC1), the second correction NMOS transistor (K-1) and the (K-1) correction NMOS transistor (NC (K-1)) is larger than the width-length ratio of the first NMOS transistor (N1) and smaller than the width-length ratio of the first NMOS transistor (N1)
4. The programmable frequency generator of claim 3,
the width-length ratio of the zero correction NMOS tube (NC0) is smaller than that of the first frequency modulation NMOS tube (N1M);
the width-to-length ratio of the (K-1) th correction NMOS tube (NC (K-1)) is less than 2n-2。
5. The programmable frequency generator of claim 4,
the gate end of each correction control NMOS tube in the correction circuit is respectively connected with the output of an AND gate (AND);
each AND gate (AND) has one input terminal for receiving a calibration enable signal (CALENN) AND the other input terminal for receiving a calibration select signal (CAL (k-1: 0)).
6. The programmable frequency generator of claim 1,
the current generation circuit also comprises a zeroth PMOS (P0), a first PMOS (P1), a zeroth NMOS (N0), a zeroth resistor (R0) and an operational amplifier (OP);
the source ends of the zeroth PMOS tube (P0) and the first PMOS tube (P1) are connected with the working Voltage (VDD);
the grid ends of a zeroth PMOS tube (P0), a first PMOS tube (P1) and a second PMOS tube (P2) are connected with the output of the operational amplifier (OP);
the drain end of the zeroth PMOS tube (P0) is short-circuited with the drain end and the gate end of the zeroth NMOS tube (N0) and the input negative of the operational amplifier (OP);
the drain end of the first PMOS tube (P1) is connected with the input positive end of the operational amplifier (OP) and one end of a zero-th resistor (R0);
the source end of the zeroth NMOS transistor (N0) and the other end of the zeroth resistor (R0) are grounded.
7. The programmable frequency generator of claim 1,
the annular oscillation circuit comprises a fourth PMOS (P4), a fifth PMOS (P5), a sixth PMOS (P6), a seventh PMOS (P7), a third NMOS (N3), a fourth NMOS (N4), a fifth NMOS (N5), a sixth NMOS (N6), a zero capacitor (C0), a first capacitor (C1), a second capacitor (C2) and a Buffer (BUF);
the source ends of a fourth PMOS tube (P4), a fifth PMOS tube (P5), a sixth PMOS tube (P6) and a seventh PMOS tube (P7) are connected with the working Voltage (VDD), and the grid end is connected with the grid end of a third PMOS tube (P3);
a gate terminal of the third NMOS transistor (N3) is connected with a drain terminal of the sixth PMOS transistor (P6), a drain terminal of the fifth NMOS transistor (N5) and one end of the second capacitor (C2);
a fourth NMOS transistor (N4), the gate terminal of which is connected to the drain terminal of the fourth PMOS transistor (P4), the drain terminal of the third NMOS transistor (N3) and one end of the zeroth capacitor (C0);
a fifth NMOS transistor (N5), the gate terminal of which is connected to the drain terminal of the fifth PMOS transistor (P5), the drain terminal of the fourth NMOS transistor (N4) and one terminal of the first capacitor (C1);
the source ends of a third NMOS transistor (N3), a fourth NMOS transistor (N4), a fifth NMOS transistor (N5) and a sixth NMOS transistor (N6), the other end of a zero capacitor (C0), the other end of a first capacitor (C1) and the other end of a second capacitor (C2) are grounded;
the drain terminal of the seventh PMOS tube (P7) and the drain terminal of the sixth NMOS tube (N6) are connected with the input terminal of the Buffer (BUF),
the output of the Buffer (BUF) is used as the output (VOUT) of the programmable frequency generator.
8. The programmable frequency generator of claim 7,
the capacitance values of the zeroth capacitor (C0), the first capacitor (C1) and the second capacitor (C2) are the same.
9. A method of calibrating a programmable frequency generator according to any of claims 1 to 8, comprising the steps of:
s1, before the programmable frequency generator works, calibrating the programmable frequency generator, before calibrating the programmable frequency generator, configuring a (K-1) th correction enabling signal (CALEN (K-1)) of a gate end of a (K-1) th correction control NMOS tube (NC (K-1) C) of a calibration circuit into a high level 1, and configuring correction enabling signals of gate ends of the rest correction control NMOS tubes into a low level 0;
s2, calibrating the programmable frequency generator, comprising the following steps:
s21, measuring PFG frequency difference caused by mismatching of all frequency modulation NMOS tubes:
firstly, the nth regulation corresponding to the highest position nThe current of the frequency NMOS tube (NnM) is cut off, the currents of the frequency modulation NMOS tubes corresponding to the other low bits and the first mirror image NMOS tube (N1MA) are conducted, and the frequency f of the square wave output by the output end (VOUT) of the programmable frequency generator at the moment is recordedn(ii) a Then the current of the nth frequency modulation NMOS tube (NnM) corresponding to the highest bit N is conducted, the current of each frequency modulation NMOS tube corresponding to the rest lower bits and the current of the first mirror image NMOS tube (N1MA) are disconnected, and the frequency f of the square wave output by the output end (VOUT) of the programmable frequency generator at the moment is recordednTRecord fn-fnTFrequency difference of fΔn；
Then the current of the nth frequency modulation NMOS tube (NnM) and the (N-1) th frequency modulation NMOS tube (N (N-1) M) corresponding to the highest bit N and the next highest bit N-1 is cut off, the current of each frequency modulation NMOS tube and the first mirror image NMOS tube (N1MA) corresponding to the other lower bits are conducted, and the frequency f of the square wave output by the output end (VOUT) of the programmable frequency generator at the moment is recordedn-1(ii) a Then keeping the current of the nth frequency modulation NMOS tube (NnM) corresponding to the highest bit N to be switched off, switching on the current of the (N-1) th frequency modulation NMOS tube (N (N-1) M) corresponding to the second highest bit N-1, switching off the current of each frequency modulation NMOS tube and the first mirror image NMOS tube (N1MA) corresponding to the other lower bits, and recording the frequency f of the square wave output by the output end (VOUT) of the programmable frequency generator at the moment(n-1)TRecord f(n-1)-f(n-1)TFrequency difference of fΔ(n-1)；
The measurement of the rest bits is analogized in turn until the frequency difference f of each bit is measuredΔi，(i＝1，2，……，n)；
S22, when the programmable frequency generator works, and when a corresponding bit current mirror of at least one frequency modulation NMOS tube is used, configuring a (K-1) th correction enabling signal (CALENN (K-1)) of a gate end of a (K-1) th correction control NMOS tube (NC (K-1) C) of a calibration circuit to be low level 0, and controlling correction enabling signals of gate ends of other correction control NMOS tubes to be at least one high level 1, so as to control the calibration circuit to subtract a corresponding frequency difference; the total frequency difference required to be subtracted by the correction circuit is the sum of the frequencies required to be subtracted of the corresponding bit current mirrors of the frequency modulation NMOS tubes required to be used;
when the highest-order n current mirror corresponding to the nth frequency modulation NMOS transistor (NnM) is usedThe calibration circuit is controlled to subtract the output frequency by 1/2 fΔn(ii) a When using the sub-high N-1 current mirror corresponding to the N-1 frequency modulation NMOS transistor (N (N-1) M), the calibration circuit needs to be controlled to make the frequency subtracted by the output frequency 1/2 x (f)Δ(n-1)-1/2*fΔn) By analogy, when the tth tuning NMOS NtM corresponding to the tth current mirror is used, the calibration circuit needs to be controlled to subtract the output frequency to obtain the frequency
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040008090A1 (en) * | 2002-04-02 | 2004-01-15 | Stmicroelectronics S.R.I. | Adjustable frequency oscillator circuit and relative calibration method |
| US20110063004A1 (en) * | 2009-09-14 | 2011-03-17 | Sunplus Technology Co., Ltd. | Frequency synthesis system with self-calibrated loop stability and bandwidth |
| CN105281710A (en) * | 2014-06-09 | 2016-01-27 | 镇江新晔网络科技有限公司 | Frequency generator used for electrical signal calibration |
| CN112130610A (en) * | 2020-10-10 | 2020-12-25 | 深圳市爱协生科技有限公司 | High power supply rejection ratio band gap reference circuit |
-
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040008090A1 (en) * | 2002-04-02 | 2004-01-15 | Stmicroelectronics S.R.I. | Adjustable frequency oscillator circuit and relative calibration method |
| US20110063004A1 (en) * | 2009-09-14 | 2011-03-17 | Sunplus Technology Co., Ltd. | Frequency synthesis system with self-calibrated loop stability and bandwidth |
| CN105281710A (en) * | 2014-06-09 | 2016-01-27 | 镇江新晔网络科技有限公司 | Frequency generator used for electrical signal calibration |
| CN112130610A (en) * | 2020-10-10 | 2020-12-25 | 深圳市爱协生科技有限公司 | High power supply rejection ratio band gap reference circuit |
Non-Patent Citations (1)
| Title |
|---|
| 马华;叶以正;王永生;张岩;: "抗工艺漂移可编程带通滤波器的设计与优化", 哈尔滨工程大学学报, no. 02, 15 February 2010 (2010-02-15) * |
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