CN114678323A - Semiconductor device and method of forming the same - Google Patents

Abstract

The invention discloses a semiconductor device and a forming method thereof. The active structure is disposed in the substrate and includes a first active region, a second active region disposed outside the first active region, and a third active region disposed outside the second active region. Shallow trench isolation is disposed in the substrate surrounding the active structure. The third active region and the second active region of the active structure can enhance the structural stability of the semiconductor device, improve the surrounding stress and prevent the semiconductor device from collapsing or damaging.

Description

Semiconductor device and method for forming the same

Technical Field

The present invention relates to a semiconductor device and a method for forming the same, and more particularly, to a semiconductor device including an active structure and an insulating structure and a method for forming the same.

Background

As semiconductor devices are miniaturized and integrated circuits are complicated, device sizes are continuously reduced and structures are continuously changed, so that maintaining the performance of small-sized semiconductor devices is a major goal in the industry. In a semiconductor fabrication process, a plurality of active regions are defined on a substrate as a basis, and then required components are formed on the active regions. Generally, the active regions are formed by photolithography and etching, but the width of the active regions is gradually reduced and the distance between the active regions is also gradually reduced under the requirement of size reduction, so that the manufacturing process thereof also faces many limitations and challenges, and thus cannot meet the product requirements.

Disclosure of Invention

An object of the present invention is to provide a semiconductor device and a method of forming the same, which includes a first active region, a second active region disposed outside the first active region, and a third active region disposed outside the second active region. Therefore, the structure strength and the surrounding stress of the semiconductor device can be improved, and the collapse or damage of the structure of the semiconductor device is avoided.

To achieve the above objective, an embodiment of the present invention provides a semiconductor device including a substrate, an active structure and a shallow trench isolation. The active structure is disposed in the substrate and includes a first active region, a second active region, and a third active region. The first active region includes a plurality of active region cells extending in a first direction in parallel to and spaced apart from each other. The second active region is disposed outside the first active region. The third active area sets up the second active area outside, the second active area and the third active area all includes along the first side that the second direction extends and along the second side that the third direction extends, and first side direct connection the second side, wherein, the second direction is crossing and not perpendicular to the first direction, the second direction perpendicular to the third direction. The shallow trench isolation is disposed in the substrate, surrounding the active structure.

To achieve the above objective, an embodiment of the present invention provides a method for forming a semiconductor device, including the following steps. Firstly, providing a substrate, and forming an active structure and shallow trench isolation in the substrate, wherein the shallow trench isolation surrounds the active structure. The active structure includes a first active region, a second active region, and a third active region. The first active region includes a plurality of active region cells extending in a first direction in parallel to and spaced apart from each other. The second active region is disposed outside the first active region. The third active area sets up the second active area outside, the second active area and the third active area all includes along the first side that the second direction extends and along the second side that the third direction extends, and first side direct connection the second side, wherein, the second direction is crossing and not perpendicular to the first direction, the second direction perpendicular to the third direction.

Drawings

The accompanying drawings are included to provide a further understanding of embodiments of the invention, and are incorporated in and constitute a part of this specification. These drawings and description are included to explain the principles of some embodiments. It should be noted that all the drawings are schematic drawings, and the relative sizes and proportions are adjusted for the purpose of illustration and drawing convenience. The same reference signs represent corresponding or similar features in different embodiments.

Fig. 1 to 9 are schematic views illustrating a method of forming a semiconductor device according to a first embodiment of the present invention, in which:

FIG. 1 is a schematic top view of a semiconductor device in a self-aligned double patterning process according to the present invention;

FIG. 2 is a schematic cross-sectional view taken along line A-A' of FIG. 1;

FIG. 3 is a schematic top view of a semiconductor device after a photoresist layer is formed;

FIG. 4 is a schematic top view of a semiconductor device after an etching process is performed thereon;

FIG. 5 is a schematic cross-sectional view taken along line A-A' of FIG. 4;

FIG. 6 is a schematic top view of a semiconductor device after another photoresist layer is formed;

FIG. 7 is a cross-sectional view taken along line A-A' of FIG. 6;

FIG. 8 is a schematic top view of a semiconductor device after forming an active structure and shallow trench isolation in accordance with the present invention; and

fig. 9 is a schematic cross-sectional view taken along line a-a' of fig. 8.

Fig. 10 to 11 are schematic views illustrating a method of forming a semiconductor device according to a second embodiment of the present invention, wherein:

FIG. 10 is a schematic top view of a semiconductor device after a photoresist layer is formed thereon according to the present invention; and

fig. 11 is a top view of the semiconductor device after forming an active structure and shallow trench isolation according to the present invention.

Wherein the reference numerals are as follows:

100 substrate

101 first active region

102 shallow trench isolation

101a, 101b active area cell

103. 303 second active region

103a, 303a first side edge

103b, 303b second side edge

105 third active region

105a first side edge

105b second side

110 first mask layer

120 second mask layer

122 first pattern

124. 124a second pattern

126. 126a third pattern

130 mask pattern

132 spacer

134. 136, 140, 340 photoresist layer

142. 342 first photoresist layer

142a opening

144. 344 second photoresist layer

144a, 344a first part

144b, 344b second part

200. 200a active structure

202 shallow trench isolation

300. 400 semiconductor device

304. 306 groove

342a opening

343a, 343b trenches

D1 first direction

O1 and O2 pore diameter

L1, L2, L3 Length

W1, W2, W3, W4, W5, W6 widths

x and y directions

Detailed Description

In order to make the present invention more comprehensible to those skilled in the art, preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. It is to be understood that the following embodiments are capable of other embodiments and that various changes, substitutions and alterations can be made to the features of the various embodiments described herein without departing from the spirit of the invention.

Referring to fig. 1 to 9, a method for forming a semiconductor device 300 according to a first embodiment of the present invention is illustrated, in which fig. 1, fig. 3, fig. 4, fig. 6, and fig. 8 are schematic top views of the semiconductor device 300 at different stages of formation, respectively, and fig. 2, fig. 5, fig. 7, and fig. 9 are schematic cross-sectional views of the semiconductor device 300 at different stages of formation. First, a substrate 100, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe), or a silicon-on-insulator (SOI) substrate, is provided, and an isolation structure, such as a Shallow Trench Isolation (STI) 202, is formed in the substrate 100 to define an active area structure (active area structure)200 in the substrate 100. The active structure 200 may be fabricated by a self-aligned double patterning (SADP) process or a self-aligned reverse patterning (SARP) process, but is not limited thereto.

In the present embodiment, the active structure 200 is preferably fabricated by the self-aligned double patterning process, which includes, but is not limited to, the following steps. First, as shown in fig. 1 and 2, a first mask layer 110, a second mask layer 120, and a plurality of mask patterns 130 are sequentially formed on a substrate 100. The first mask layer 110 and the second mask layer 120 may have a single-layer structure or a multi-layer structure, for example, each of the first mask layer 110 and the second mask layer 120 may include a material such as an oxide or a nitride, wherein the first mask layer 110 preferably includes a polysilicon layer, and the second mask layer 120 includes a silicon nitride layer, but not limited thereto. In detail, the mask patterns 130 are, for example, spaced apart from each other on the second mask layer 120, and may have the same pitch (pitch) therebetween and extend along a first direction D1, wherein the first direction D1 is, for example, perpendicular to the y direction or the x direction, as shown in fig. 1. In one embodiment, the mask patterns 130 are formed by, for example, a standard gate process, and thus, the material of each mask pattern 130 may be, but is not limited to, polysilicon or other suitable materials.

As shown in fig. 1 and 2, deposition and etch-back processes are sequentially performed to form spacers 132 on each mask pattern 130, the spacers 132 for example surround sidewalls of each mask pattern 130, wherein the spacers 132 for example comprise nitride materials or other materials having an etching selectivity with respect to the mask pattern 130. It should be noted that, in the present embodiment, each mask pattern 130 is preferably rectangular, so that the spacer 132 surrounding each mask pattern 130 can be a closed rectangular frame (rectangular frame) when viewed from the top view shown in fig. 1, but is not limited thereto. One skilled in the art will readily appreciate that the mask pattern may have other shapes for the actual device requirements, such that the spacer may alternatively take the shape of a square frame, a circular ring, a racetrack-shaped, or other suitable shapes.

Then, a photoresist layer 134 (e.g., comprising a suitable photoresist material) is formed on the substrate 100 to cover the mask patterns 130 and the spacers 132, and particularly to cover both ends of each mask pattern 130 and each spacer 132, as shown in fig. 1. It is noted that the photoresist layer 134 has a closed rectangular frame shape, and has a portion extending in a second direction (i.e., y direction) and a portion extending in a third direction (i.e., x direction), wherein the second direction may be perpendicular to the third direction, and a width W1 of the portion extending in the second direction (i.e., y direction) may be about equal to a width W2 of the portion extending in the third direction (i.e., x direction), but is not limited thereto.

Subsequently, the mask pattern 130 is completely removed, and an etching process is performed through the photoresist layer 134 and the spacers 132 to simultaneously transfer the patterns of the photoresist layer 134 and the spacers 132 to the underlying second mask layer 120, thereby forming the structure shown in fig. 3. In detail, after the etching process is performed, the second mask layer 120 may be patterned into a plurality of first patterns 122 extending in the first direction D1, a plurality of second patterns 124 extending in the second direction (i.e., y direction), and a plurality of third patterns 126 extending in the third direction (i.e., x direction), wherein each of the first patterns 122 directly contacts the second pattern 124 or the third pattern 126. It is noted that the shapes of the second pattern 124 and the third pattern 126 may be a closed rectangular frame shape corresponding to the photoresist layer 134, and are disposed outside all the first patterns 122, and each of the second pattern 124 and each of the third pattern 126 may have a width W1 and a width W2 respectively identical to the width W1 and the width W2 of the portion of the photoresist layer 134, as shown in fig. 3. In one embodiment, the width W1 can be selected to be the same as the width W2, but not limited thereto.

As shown in fig. 3, after the photoresist layer 134 is removed, a photoresist layer 136 (e.g., comprising a suitable photoresist material) is formed on the substrate 100 to cover the first pattern 122, the second pattern 124 and the third pattern 126 of the second mask layer 120. It is noted that the photoresist layer 136 completely covers all of the first pattern 122, and partially covers the second pattern 124 and the third pattern 126. With this arrangement, the width W1 and the width W2 of the second pattern 124 and the third pattern 126 can be exposed outside the photoresist layer 136, for example, about half of the width W1 and the width W2 are exposed. It should be understood by those skilled in the art that the widths W1 and W2 of the second pattern 124 and the third pattern 126 covered/exposed by the photoresist layer 136 can be adjusted according to the actual device requirements, and are not limited thereto.

As shown in fig. 4 and 5, an etching process is performed through the photoresist layer 136 to partially remove the second pattern 124 and the third pattern 126 of the second mask layer 120, and then the photoresist layer 136 is completely removed. Thus, the second pattern 124 and the third pattern 126 of the second mask layer 120 can be further patterned into a second pattern 124a and a third pattern 126a, so as to reduce the widths W1 and W2 of the second pattern 124 and the third pattern 126 to a width W3 and a width W4, respectively, and in addition, after the etching process is performed, a portion of the underlying first mask layer 110 can be exposed, as shown in fig. 4.

As shown in fig. 6 and 7, a photoresist layer 140 (e.g., comprising a suitable photoresist material) is formed on the substrate 100 to cover the first pattern 122, the second pattern 124a and the third pattern 126a of the second mask layer 120. In detail, the photoresist layer 140 includes a first photoresist layer 142 and a second photoresist layer 144, wherein the first photoresist layer 142 entirely covers all of the first pattern 122 and partially covers the second pattern 124a and the third pattern 126a, so that the width W3 and the width W4 of the second pattern 124a and the third pattern 126a can be partially exposed outside the photoresist layer 142, for example, about half of the width W3 and the width W4 can be exposed, but not limited thereto. In addition, the first photoresist layer 142 further includes a plurality of openings 142a spaced apart from each other and alternately arranged to respectively align and expose a portion of each of the first patterns 122 thereunder, as shown in fig. 6 and 7. On the other hand, the second photoresist layer 144 is disposed on the outer side of the first photoresist layer 142 to partially cover the first mask layer 110 exposed to the outermost side. It is noted that the second photoresist layer 144 does not contact the first photoresist layer 142, and the second photoresist layer 144 and the first photoresist layer 142 are spaced apart to expose a portion of the second mask layer 120 (including a portion of the second pattern 124a and a portion of the third pattern 126a) and a portion of the first mask layer 110, as shown in fig. 6 and 7. It should be noted that the second photoresist layer 144 includes a first portion 144a extending in the y direction and a second portion 144b extending in the third direction (i.e., the x direction), and the first portion 144a extending along the second direction (i.e., the y direction) and the second portion 144b extending along the x direction may also preferably present a closed rectangular frame shape, so as to be disposed at equal intervals outside the first photoresist layer 142, but not limited thereto.

Then, an etching process is performed through the photoresist layer 140 to remove the exposed first pattern 122, the second pattern 124a and the third pattern 126a, and the pattern of the photoresist layer 140 (particularly, the pattern of the second photoresist layer 144) is transferred into a portion of the first mask layer 110 therebelow, and then the photoresist layer 140 is completely removed to expose the first mask layer 110 and the remaining first pattern 122, the second pattern 124a and the third pattern 126 a. Next, another etching process is performed through the remaining first pattern 122, the second pattern 124a, the third pattern 126a and the patterned first mask layer 110 to pattern the underlying substrate 100, so as to form a plurality of shallow trench isolations 102 in the substrate 100. Thus, the active structure 200 is defined in the substrate 100, and then the shallow trench isolation 102 is filled with an insulating material (not shown), such as silicon oxide, silicon nitride, or silicon oxynitride, so as to form a shallow trench isolation 202 in the substrate 100, the top surface of which is aligned with the surface of the substrate 100, as shown in fig. 8 and 9.

In detail, the active structure 200 includes a first active region 101, a second active region 103, and a third active region 105, which are sequentially disposed from inside to outside, the second active region 103 is disposed outside the first active region 101, and the third active region 105 is disposed outside the second active region 103, such that the second active region 103 is located between the third active region 105 and the first active region 101, and the shallow trench isolation 202 surrounds the active structure 200, and a portion of the shallow trench isolation 202 is disposed between the second active region 103 and the third active region 105, and between the first active region 101 and the second active region 103. In the present embodiment, the second active region 103 is, for example, entirely surrounded outside the first active region 101, and the third active region 105 is also entirely surrounded outside the second active region 103 so as to simultaneously surround the second active region 103 and the first active region 101, as shown in fig. 8, but not limited thereto. The first active region 101 further includes a plurality of active region cells 101a, 101b extending along the first direction D1 in parallel and separated from each other, wherein the active region cells 101a, 101b are sequentially arranged in a plurality of rows in the first direction D1, for example, alternately arranged with each other, and may be a specific arrangement as a whole, such as an array arrangement (array arrangement) shown in fig. 8, but not limited thereto. It should be noted that, among the active area cells 101a and 101b, the active area cells 101a of the first portion have the same length L1 in the first direction D1, and the active area cells 101b of the second portion have different lengths in the first direction D1, and are different from the length L1, such as a length L2 greater than the length L1 or a length L3 less than the length L1.

Preferably, the second portion of active area cells 101b are located on two opposite sides of the first portion of active area cells 101a in the third direction (i.e., x direction), and may directly contact the second active area 103 disposed outside all of the active area cells 101a and 101b, while the first portion of active area cells 101a do not contact the second active area 103. In this embodiment, the second active region 103 further includes a plurality of first sides 103a extending along the second direction (i.e., the y direction) and a plurality of second sides 103b extending along the third direction (i.e., the x direction), and each first side 103a and each second side 103b are connected to each other, so that the second active region 103 may be in a closed rectangular frame shape as a whole, as shown in fig. 8. In addition, the first side 103a and the second side 103b may have the same width W5, such as about half of the width W3 and the width W4 of the second pattern 124a or the third pattern 126a, but not limited thereto. On the other hand, the third active region 105 also includes a plurality of first sides 105a extending along the second direction (i.e., the y direction) and a plurality of second sides 105b extending along the third direction (i.e., the x direction), and each first side 105a is also connected to each second side 105b, so that the third active region 105 can also be a closed rectangular frame as shown in fig. 8. In addition, the first side 105a and the second side 105b of the third active region 105 may also have the same width W6, wherein the width W5 of the first side 103a or the second side 103b of the second active region 103 is greater than the width W6 of the first side 105a or the second side 105b of the third active region 105.

Thus, the semiconductor device 300 according to the first embodiment of the present invention is completed, which includes the first active region 101, the second active region 103, and the third active region 105 sequentially arranged from inside to outside. With this arrangement, the second active region 103 can uniformly distribute stress influence from the first active region 101 and the shallow trench isolation 202 through the second portion of the active region unit 101b connected thereto, and stabilize the structure of the active region units 101a and 101b through the rectangular frame that can integrally surround all the active region units 101a and 101b, thereby preventing any of the active region units 101a and 101b from collapsing or damaging the structure. In addition, the third active region 105 disposed outside the second active region 103 and the first active region 101 can further protect the inner structure, maintain the integrity thereof, and avoid the occurrence of structural deformation.

In addition, it should be readily apparent to those skilled in the art that other aspects of the semiconductor device and method for forming the same may be made without limitation to the present invention to meet the requirements of actual products. Further embodiments or variations of the method of the semiconductor device of the present invention are described below. For simplicity, the following description mainly refers to the differences between the embodiments, and the description of the same parts is not repeated. In addition, the same components in the embodiments of the present invention are labeled with the same reference numerals to facilitate the comparison between the embodiments.

Referring to fig. 10 to 11, a method for forming a semiconductor device 400 according to a second embodiment of the present invention is illustrated. The manufacturing process of the semiconductor device 400 in this embodiment is substantially the same as the manufacturing process of the semiconductor device 300 in the first embodiment, as shown in fig. 1 to 5, and the description of the same parts is omitted. The main difference between the present embodiment and the first embodiment is that the photoresist layer 340 is formed on the substrate 100 to cover the first pattern 122, the second pattern 124a and the third pattern 126a of the second mask layer 120, and the first photoresist layer 342 in the photoresist layer 340 simultaneously includes a plurality of openings 342a disposed on the inner side and trenches 343a, 343b disposed on the outer side and opened outward.

In detail, the photoresist layer 340 includes a first photoresist layer 342 and a second photoresist layer 344, wherein the first photoresist layer 342 includes a plurality of side edges (not labeled) extending along the second direction (i.e., the y direction) and a plurality of side edges (not labeled) extending along the third direction (i.e., the x direction) to present a square shape and entirely cover all of the first pattern 122 and partially cover the second pattern 124a and the third pattern 126a, so that the width W3 and the width W4 of the second pattern 124a and the third pattern 126a can be exposed outside the photoresist layer 342, for example, about half of the width W3 and the width W4 can be exposed, but not limited thereto. In addition, the openings 342a of the first photoresist layers 342 are spaced apart from each other and alternately arranged in sequence along the first direction D1 to respectively align and expose a portion of each of the underlying first patterns 122, as shown in fig. 10. The trenches 343a, 343b of the first photoresist layer 342 may be sequentially arranged on the sides of the first photoresist layer 342 along the second direction (i.e., the y direction) and the third direction (i.e., the x direction) to partially expose the underlying second pattern 124a or the third pattern 126 a. Preferably, an aperture (not shown) of each trench 343a, 343b is different from an aperture (not shown) of each opening 342a, and is preferably larger than an aperture of each opening 342a, but not limited thereto. It is noted that each of the trenches 343a, 343b opens outwardly in a direction away from the opening 342a (i.e., toward the second photoresist layer 344), as shown in fig. 10. In an embodiment, each of the trenches 343a may have the same aperture O1 in the second direction (i.e., y direction), and each of the trenches 343b may also have the same aperture O2 in the third direction (i.e., x direction), wherein the aperture O1 of each of the trenches 343a may be selected to be the same as the aperture O2 of each of the trenches 343b, but not limited thereto.

On the other hand, the second photoresist layer 344 includes a first portion 344a extending in the second direction (i.e., y direction) and a second portion 344b extending in the third direction (i.e., x direction) to also present a closed rectangular frame shape. Thus, the second photoresist layer 344 may be disposed outside the first photoresist layer 342 to partially cover the first mask layer 110 exposed to the outermost side. It is noted that the second photoresist layer 344 does not contact the first photoresist layer 342, and is spaced apart from the first photoresist layer 342 to expose a portion of the second mask layer 120 (including a portion of the second pattern 124a and a portion of the third pattern 126a) and a portion of the first mask layer 110, as shown in fig. 10.

Then, an etching process is performed through the photoresist layer 340 to remove the exposed first pattern 122, the second pattern 124a and the third pattern 126a, and the pattern of the photoresist layer 340 (particularly, the pattern of the second photoresist layer 344) is transferred into a portion of the first mask layer 110 below, and then the photoresist layer 340 is completely removed to expose the first mask layer 110 and the remaining first pattern 122, the second pattern 124a and the third pattern 126 a. Next, another etching process is performed through the remaining first pattern 122, the second pattern 124a, the third pattern 126a and the patterned first mask layer 110 to pattern the underlying substrate 100, so as to form a plurality of shallow trenches (not shown) in the substrate 100. Thus, the active structure 200a is defined in the substrate 100, and then deposition and planarization processes are sequentially performed to form the shallow trench isolation 202 filling the shallow trench, so as to complete the semiconductor device 400 of the present embodiment, as shown in fig. 11.

The structure of the semiconductor device 400 of the present embodiment is substantially the same as the semiconductor device 300 of the first embodiment, and includes the substrate 100, the active structure 200a, and the shallow trench isolation 202, wherein the active structure 200a also includes the first active region 101 (including the active region units 101a and 101b), the second active region 303, and the third active region 105, which are sequentially disposed from the inside to the outside, and the same points are not repeated herein. It should be noted that the second active region 303 of the present embodiment includes a plurality of first sides 303a extending along the second direction (i.e., the y direction) and a plurality of second sides 303b extending along the third direction (i.e., the x direction), and each first side 303a and each second side 303b are connected to each other, so that the second active region 303 may be a closed rectangular frame as a whole. Furthermore, a plurality of trenches 304 opened outward are additionally disposed on each first side 303a, each trench 304 is opened toward the first side 105a of the third active region 105, and the same aperture O1 may be formed in the second direction (i.e., the y direction); each second side 303b is additionally provided with a plurality of trenches 306 opened outward in the third direction (i.e., x direction), each trench 306 is opened toward the second side 105b of the third active region 105, and the third direction (i.e., x direction) may have the same aperture O2, wherein the aperture O1 of each trench 304 may be the same as the aperture O2 of each trench 306, but is not limited thereto. In another embodiment, the aperture O1 of each trench 304 may be different from the aperture O2 of each trench 306, or each trench 304 and/or each trench 306 may have apertures of different sizes.

As such, the first side 303a and the second side 303b of the second active region 303 may respectively form a battlement-shaped contour, which is preferably close to the third active region 105 disposed at the outer side and far from the first active region 101 disposed at the inner side. In other words, in the present embodiment, the active area unit 101b of the second portion directly contacts the end of the first side 303a or the second side 303b not provided with the battlement-shaped contour, and the end of the first side 303a or the second side 303b provided with the battlement-shaped contour does not contact any active area unit 101a or 101 b. With this configuration, the second active region 303 of the present embodiment can also uniformly distribute the stress influence from the first active region 101 and the shallow trench isolation 202 through the active region unit 101b of the second portion connected thereto, and stabilize the structure of the active region units 101a and 101b through the rectangular frame that can integrally surround all the active region units 101a and 101b, thereby preventing any of the active region units 101a and 101b from collapsing or damaging the structure. In addition, the second active region 303 may further guide the stress outward by using the trenches 304 and 306 opened outward, so as to further protect the integrity of the inner structure and prevent the active region units 101a and 101b from deformation or distortion. Furthermore, the trenches 304, 306 are integrated into the fabrication process of the active structure 200a, thereby avoiding the use of additional masks and resulting in a semiconductor device 400 with more optimized overall structural stability without increasing the fabrication process and the fabrication cost.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (20)

1. A semiconductor device, comprising:

a substrate; and

an active structure disposed in the substrate, the active structure comprising:

a first active region including a plurality of active region cells, the active region cells extending in a first direction in parallel to each other and spaced apart from each other;

a second active region disposed outside the first active region;

a third active region disposed outside the second active region, wherein the second active region and the third active region each include a first side extending along a second direction and a second side extending along a third direction, and the first side is directly connected to the second side, wherein the second direction is perpendicular to the third direction and the second direction intersects with the first direction and is not perpendicular to the first direction; and

and the shallow trench isolation is arranged in the substrate and surrounds the active structure.

2. The semiconductor device of claim 1, wherein the second active region comprises a plurality of trenches, each trench being disposed on and facing the first side of the second active region or the second side of the second active region.

3. The semiconductor device according to claim 2, wherein the trenches have the same aperture.

4. The semiconductor device according to claim 2, wherein the trenches have different apertures.

5. The semiconductor device of claim 1, wherein the first side of the second active region or the second side of the second active region has a battlement-like profile that does not contact the active region cells.

6. The semiconductor device according to claim 1, wherein the active region cell of the first portion directly contacts the first side of the second active region or the second side of the second active region.

7. The semiconductor device according to claim 6, wherein the active region cells of the first portion have different lengths in the first direction.

8. The semiconductor device of claim 1, wherein a width of the first side of the second active region or the second side of the second active region is greater than a width of the first side of the third active region or the second side of the third active region.

9. The semiconductor device of claim 1, wherein a portion of shallow trench isolation is disposed between the second active region and the third active region, and between the active region cell and the second active region.

10. A method of forming a semiconductor device, comprising:

providing a substrate; and

forming an active structure and shallow trench isolation in the substrate, the shallow trench isolation surrounding the active structure, wherein the active structure comprises:

a first active region including a plurality of active region cells, the active region cells extending in a first direction in parallel to each other and spaced apart from each other;

a second active region disposed outside all of the first active regions; and

the third active area is arranged outside the second active area, the second active area and the third active area both comprise a first side edge extending along the second direction and a second side edge extending along the third direction, and the first side edge is directly connected with the second side edge, wherein the second direction is intersected and not perpendicular to the first direction, and the second direction is perpendicular to the third direction.

11. The method for forming a semiconductor memory device according to claim 10, further comprising:

forming a first mask layer and a second mask layer stacked in sequence on the substrate;

performing a self-aligned double patterning process, forming a plurality of mask patterns on the second mask layer, extending in the first direction in parallel and spaced apart from each other, and forming spacers on the second mask layer;

forming a photoresist layer on the second mask layer, wherein the photoresist layer is overlapped at two ends of each mask pattern; and

and performing an etching process on the second mask layer through the photoresist layer and the mask pattern to form a plurality of first patterns, a plurality of second patterns and a plurality of third patterns, wherein the first patterns are parallel to each other and extend along the first direction in a mutually separated mode, the second patterns extend along the second direction, the third patterns extend along the third direction, and each first pattern directly contacts with the second patterns or the third patterns.

12. The method for forming a semiconductor memory device according to claim 11, further comprising:

forming another photoresist layer on the substrate, wherein the another photoresist layer completely covers the first pattern and partially covers the second pattern and the third pattern; and

and carrying out another etching manufacturing process on the second pattern and the third pattern through the another photoresist layer.

13. The method for forming a semiconductor memory device according to claim 11, further comprising:

forming another photoresist layer on the substrate to cover the first pattern, the second pattern and the third pattern, wherein the another photoresist layer includes a first photoresist layer and a second photoresist layer on the first photoresist layer, the first photoresist layer includes a plurality of openings, and each opening exposes a portion of each first pattern; and

and carrying out another etching manufacturing process on the first mask layer and the substrate through the other photoresist layer, the first pattern, the second pattern and the third pattern to form the active structure.

14. The method of claim 13, wherein the first photoresist layer further comprises a plurality of trenches, each trench portion exposing the second pattern or the third pattern.

15. The method as claimed in claim 13, wherein the openings are arranged in sequence along the first direction, and the trenches are arranged in sequence along the second direction or a third direction.

16. The method according to claim 14, wherein an aperture of the opening is different from an aperture of the trench.

17. The method of claim 10, wherein the first side of the second active region or the second side of the second active region has a battlement-like profile that does not contact the active region cells.

18. The method of claim 10, wherein the second active region comprises a plurality of trenches, each trench being disposed at the first side of the second active region or the second side of the second active region and facing the first side of the third active region or the second side of the third active region.

19. The method of claim 18, wherein the trenches have the same aperture.

20. The method of claim 18, wherein the trenches have different apertures.

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