CN114678256A - Semiconductor epitaxial structure, preparation method thereof and semiconductor structure - Google Patents

Semiconductor epitaxial structure, preparation method thereof and semiconductor structure Download PDF

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CN114678256A
CN114678256A CN202011573455.4A CN202011573455A CN114678256A CN 114678256 A CN114678256 A CN 114678256A CN 202011573455 A CN202011573455 A CN 202011573455A CN 114678256 A CN114678256 A CN 114678256A
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layer
substrate
component
transition
transition layer
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张晖
周文龙
孔苏苏
李仕强
谈科伟
杜小青
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Dynax Semiconductor Inc
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

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Abstract

The application relates to a semiconductor epitaxial structure, a preparation method thereof and a semiconductor structure, wherein the semiconductor epitaxial structure comprises a substrate and a first transition layer, and the first transition layer is formed on the substrate; wherein a concentration of a first component of the first transition layer, which is an element of the substrate, varies in a gradient along a direction in which a thickness increases. The first transition layer is formed on the substrate, the concentration of the first component changes along the gradient of the thickness increasing direction, the first component is the element of the substrate, the defects of dislocation, pits or crystal grain boundaries and the like caused by mismatching of crystal lattices and thermal expansion are avoided, the thermal resistance of an epitaxial layer is effectively reduced, and the performance, reliability and service life of the manufactured semiconductor device are improved.

Description

Semiconductor epitaxial structure, preparation method thereof and semiconductor structure
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor epitaxial structure, a preparation method thereof and a semiconductor structure.
Background
The semi-insulating silicon carbide (SiC) has the advantages of high thermal conductivity, high resistivity and the like, has higher maturity in the aspect of mass production, and is widely applied to preparing epitaxial structures with high frequency and high power. For example, SiC remains the best substrate choice for gallium nitride (GaN) Electron Mobility Transistor (HEMT) epitaxial structures.
However, in the conventional process for growing a heteroepitaxial single crystal film on a SiC substrate, defects such as dislocation, pits or grain boundaries are generated due to inevitable lattice and thermal expansion mismatching, interface thermal resistance is increased, the temperature of the manufactured semiconductor device is increased too fast, and the performance, reliability and service life of the semiconductor device are seriously affected.
Disclosure of Invention
In view of the above, it is necessary to provide a semiconductor epitaxial structure, a method for manufacturing the same, and a semiconductor structure that can effectively reduce the thermal resistance of the epitaxial layer, so as to improve the performance, reliability, and lifespan of the semiconductor device.
To achieve the above and other objects, a first aspect of the present application provides a semiconductor epitaxial structure, including:
a substrate; and
a first transition layer formed on the substrate;
wherein a concentration of a first component of the first transition layer, which is an element of the substrate, varies in a gradient along a direction in which a thickness increases.
In the semiconductor epitaxial structure in the above embodiment, since there is a region with higher initial defect density and lower thermal conductivity near the interface where the epitaxial layer, such as the nucleation layer, is formed on the substrate, and the thermal conductivity of the region improves as the thickness of the nucleation layer increases, however, since the thermal conductivity of the epitaxial layer is lower than that of the substrate, increasing the thickness of the epitaxial layer will increase the effective thermal resistance of the overall epitaxial structure. In order to reduce the thermal resistance of the whole epitaxial structure and obtain a thin epitaxial layer with high crystallization quality and low interface disorder, a first transition layer with the concentration of a first component changing along the gradient of the thickness increasing direction is formed on the upper surface of the substrate, the first component is an element of the substrate, so that the in-plane lattice atomic configuration on the substrate is perfectly converted into the epitaxial layer lattice within the transition range of 1 primitive cell-5 primitive cell thickness, the epitaxial layer with high quality is obtained, and the thickness of the epitaxial layer is effectively controlled while the thermal resistance of the epitaxial layer is effectively reduced. Thereby avoiding the defects of dislocation, pits or grain boundaries and the like caused by lattice and thermal expansion mismatching, reducing the interface thermal resistance, improving the performance and reliability of the manufactured semiconductor device and prolonging the service life.
In one embodiment, the concentration of the first component of the first transition layer is stepped down or tapered down in the direction of increasing thickness such that the in-plane lattice atomic configuration on the substrate is perfectly converted to the epitaxial layer lattice over the transition range of 1-5 primitive cell thickness.
In one embodiment, the first transition layer includes a first intermediate layer and a second intermediate layer stacked in this order, the first intermediate layer being located between the substrate and the second intermediate layer, wherein a concentration of the first component of the first intermediate layer is greater than a concentration of the first component of the second intermediate layer.
In one embodiment, the semiconductor epitaxial structure further comprises a nucleation layer, a second transition layer and a channel layer which are sequentially stacked, wherein the nucleation layer is positioned between the first transition layer and the second transition layer; wherein a concentration of a second component of the second transition layer varies in a gradient along a direction of increasing thickness, the second component of the second transition layer being an element of the channel layer.
In the semiconductor epitaxial structure in the above embodiment, by forming the second transition layer, in which the concentration of the second component changes in a gradient manner along the direction of increasing the thickness, on the side of the nucleation layer away from the substrate, and the second component of the second transition layer is an element of the channel layer, the in-plane lattice atom configuration of the nucleation layer is perfectly converted into the lattice of the channel layer within the transition range of 1 primitive cell to 5 primitive cells, for example, 0.5nm to 1.5nm, so as to avoid growing the buffer layer and directly grow the high-quality channel layer, thereby realizing the design of the buffer-layer-free structure, dissipating the heat generated in the thin channel into the substrate more effectively, reducing the thermal resistance of the whole epitaxial structure effectively, and alleviating the problem of self-heating of the manufactured semiconductor device. Due to the realization of the buffer-layer-free structure design, the thickness of the whole epitaxial structure is effectively reduced, the consumption of raw materials is reduced while the performance of the manufactured semiconductor device is ensured, the Deposition time is obviously shortened, the manufacturing cost is reduced to the maximum extent, and the capacity of Metal-organic Chemical Vapor Deposition (MOCVD) is increased.
In one embodiment, the concentration of the second component of the second transition layer is stepwise or gradually increased in the direction of increasing thickness.
In one embodiment, the first transition layer further comprises a third component, the third component being an element of the nucleation layer, and a concentration of the third component of the first transition layer is stepped up or gradually increased in a direction of increasing thickness.
In one embodiment, the second transition layer further comprises a fourth component, the fourth component being an element of the nucleation layer, the concentration of the fourth component of the second transition layer being stepped or tapered in a direction of increasing thickness.
In one embodiment, the second transition layer includes a third intermediate layer and a fourth intermediate layer stacked in this order, the third intermediate layer being located between the nucleation layer and the fourth intermediate layer, and a concentration of the second component of the third intermediate layer being smaller than a concentration of the second component of the fourth intermediate layer.
The second aspect of the present application provides a semiconductor structure, which is manufactured by using the semiconductor epitaxial structure described in any of the embodiments of the present application, and the thickness of the epitaxial layer is effectively controlled while the thermal resistance of the epitaxial layer is effectively reduced, so that the performance, reliability and service life of the manufactured semiconductor device are improved.
A third aspect of the present application provides a method for manufacturing a semiconductor epitaxial structure, including:
providing a substrate;
and forming a first transition layer on the substrate, wherein the concentration of a first component of the first transition layer is changed along the gradient of the thickness increasing direction, and the first component is an element of the substrate.
In the method for manufacturing the semiconductor epitaxial structure in the above embodiment, the first transition layer in which the concentration of the first component changes in a gradient manner along the thickness increasing direction is formed on the upper surface of the substrate, and the first component is an element of the substrate, so that the in-plane lattice atomic configuration on the substrate is perfectly converted into the epitaxial layer lattice within the transition range of 1 primitive cell to 5 primitive cells in thickness, so as to obtain the high-quality epitaxial layer, and the thickness of the epitaxial layer is effectively controlled while the thermal resistance of the epitaxial layer is effectively reduced. Thereby avoiding the defects of dislocation, pits or grain boundaries and the like caused by lattice and thermal expansion mismatching, reducing the interface thermal resistance, improving the performance and reliability of the manufactured semiconductor device and prolonging the service life.
Drawings
For a better understanding of the description and/or illustration of embodiments and/or examples of those applications disclosed herein, reference may be made to one or more of the drawings. The additional details or examples used to describe the figures should not be considered limiting of the scope of any of the disclosed applications, the presently described embodiments and/or examples, and the presently understood best mode of such applications.
Fig. 1 is a schematic cross-sectional view of a semiconductor epitaxial structure provided in a first embodiment of the present application;
fig. 2 is a schematic cross-sectional view of a semiconductor epitaxial structure provided in a second embodiment of the present application;
fig. 3 is a schematic cross-sectional view of a semiconductor epitaxial structure provided in a third embodiment of the present application;
fig. 4 is a schematic cross-sectional view of a semiconductor epitaxial structure provided in a fourth embodiment of the present application;
fig. 5 is a schematic cross-sectional view of a semiconductor epitaxial structure provided in a fifth embodiment of the present application;
fig. 6 is a schematic cross-sectional view of a semiconductor epitaxial structure provided in a sixth embodiment of the present application;
fig. 7 is a flow chart illustrating a method for fabricating a semiconductor epitaxial structure according to an embodiment of the present disclosure;
fig. 8 is a schematic flow chart illustrating a method for fabricating a semiconductor epitaxial structure according to another embodiment of the present disclosure;
fig. 9 is a flow chart illustrating a method for fabricating a semiconductor epitaxial structure according to yet another embodiment of the present disclosure.
Description of reference numerals: 10-substrate, 20-nucleation layer, 12-first intermediate layer, 121-first intermediate layer, 122-second intermediate layer, 23-second intermediate layer, 231-third intermediate layer, 232-fourth intermediate layer, 30-channel layer, 40-barrier layer, 50-cap layer.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for convenience in describing the relationship of one element or feature to another element or feature illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the application are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.
The multilayer structure described in the present application may be formed layer by layer or may be integrally formed; the adjacent two-layer structures can be in contact with each other or isolated from each other.
Please refer to fig. 1 to 9. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present application, and although the drawings only show the components related to the present application and are not drawn according to the number, shape and size of the components in actual implementation, the type, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Referring to fig. 1, in one embodiment of the present application, a semiconductor epitaxial structure is provided, which includes a substrate 10 and a first transition layer 12, the first transition layer 12 being formed on the substrate 10, wherein a concentration of a first component of the first transition layer 12 varies in a gradient along a direction of increasing thickness, the first component being an element of the substrate 10.
By way of example, with continued reference to fig. 1, since there is a region of higher initial defect density and lower thermal conductivity near the interface where an epitaxial layer, such as a nucleation layer, is formed on substrate 10, and the thermal conductivity of this region improves as the thickness of the epitaxial layer increases, however, since the thermal conductivity of the epitaxial layer is lower than that of substrate 10, increasing the thickness of the epitaxial layer increases the effective thermal resistance of the overall epitaxial structure. In order to reduce the thermal resistance of the whole epitaxial structure and obtain a thin epitaxial layer with high crystalline quality and low interface disorder, a first transition layer 12 with the concentration of a first component changing along the gradient of the thickness increasing direction is formed on the upper surface of a substrate 10, the first component is an element of the substrate 10, so that the in-plane lattice atomic configuration of the substrate 10 is perfectly converted into the epitaxial layer lattice within the transition range of 1 primitive cell-5 primitive cell thickness, the epitaxial layer with high quality is obtained, and the thickness of the epitaxial layer is well controlled while the thermal resistance of the epitaxial layer is effectively reduced. Thereby avoiding the defects of dislocation, pits or grain boundaries and the like caused by lattice and thermal expansion mismatching, reducing the interface thermal resistance, improving the performance and reliability of the manufactured semiconductor device and prolonging the service life.
As an example, referring to fig. 2, in an embodiment of the present application, the nucleation layer 20 is formed on the surface of the first transition layer 12 far from the substrate 10, such as a SiC substrate, and the embodiment exemplifies an implementation principle of the present application by forming the nucleation layer 20 on the SiC substrate, for example, the nucleation layer 20 is an aluminum nitride (AlN) nucleation layer, and by controlling a gradient change of a silicon composition along a thickness direction during the growth of the first transition layer 12, within a transition range of a 1 primitive cell-5 primitive cell thickness, such as 0.5nm-1.5nm, an in-plane lattice atom configuration of the SiC substrate is perfectly converted into an AlN lattice, so as to obtain a high-quality AlN nucleation layer, and reduce a thickness of the AlN layer from a conventional 50nm-500nm to 2nm-50 nm. The defects of dislocation, pits, grain boundaries and the like caused by lattice, thermal expansion mismatching and the like are avoided, the interface thermal resistance is reduced, and the performance, reliability and service life of the manufactured semiconductor device are improved.
By way of example, with continued reference to fig. 2, in one embodiment of the present application, the concentration of the first component of the first transition layer 12 may be configured to be stepped or tapered in the direction of increasing thickness such that the in-plane lattice atomic configuration on the substrate 10 is perfectly transformed to the lattice of an adjacent epitaxial layer, such as the nucleation layer 20, within the transition range of 1 cell-5 cells thick, such as 0.5nm-1.5nm, to achieve a high quality epitaxial layer, while effectively reducing the thermal resistance of the epitaxial layer, while effectively controlling the thickness of the epitaxial layer.
By way of example, in one embodiment of the present application, please continue to refer to fig. 2, the first transition layer 12 may be provided as comprising (Al)ySi1-y) N buffer transition layer, y is more than 0 and less than 1, so as to form an interface structure with gradually changed components. Experiments show that the composition-induced lattice mismatch and the difference in surface energy gradient between the epitaxial layer and the substrate are significantly reduced, thereby forming a high-quality epitaxial layer.
By way of example, in one embodiment of the present application, with continued reference to fig. 2, the first transition layer 12 further includes a third component that is an element of the nucleation layer 20, the concentration of the third component of the first transition layer 12 being graded or incrementally increased in the direction of increasing thickness. Preferably, the elements of the first transition layer 12 other than the first element are the same as the elements of the nucleation layer 20. For example, the first transition layer may be provided to include (Al)ySi1-y) N buffer transition layer, 0 < y < 1, to form a composition gradient interface structure, wherein, the aluminum is the element of the nucleation layer, the concentration of the aluminum in the first transition layer 12 is increased along the thickness increasing direction, so that the in-plane lattice atom configuration on the substrate 10 is perfectly transformed into the lattice of the nucleation layer 20 in the transition range of 1 primitive cell-5 primitive cell thickness, such as 0.5nm-1.5nm, to obtain high quality epitaxial layer, and the thickness of the epitaxial layer is effectively controlled while the thermal resistance of the epitaxial layer is effectively reduced.
By way of example, in one embodiment of the present application, please continue with reference to FIG. 2, can provide for including (Al)ySi1-y) The thickness of the buffer transition layer of N is 0.5nm-5 nm; for example, in order to obtain an optimal growth interface, it may be provided that (Al) is includedySi1-y) The thickness of the buffer transition layer of N is 1 nm. The nucleation layer 20 may be provided as an aluminum nitride (AlN) nucleation layer, and the AlN nucleation layer may be provided to have a thickness of 5nm to 50 nm. As an example, the AlN nucleation layer may be set to a thickness of 30nm in order to achieve an optimal thermal resistance value.
Further, referring to fig. 3, in an embodiment of the present application, the first transition layer 12 includes a first intermediate layer 121 and a second intermediate layer 122 stacked in sequence, the first intermediate layer 121 is located between the substrate 10 and the second intermediate layer 122; wherein the concentration of the first component of the first intermediate layer 121 is greater than the concentration of the first component of the second intermediate layer 122.
As an example, with continued reference to fig. 3, the first intermediate layer 121 may be set to be a silicon-doped aluminum nitride layer, the atomic ratio of aluminum to silicon in the first intermediate layer 121 may be set to 0.4-0.6, for example, the atomic ratio of silicon to aluminum in the first intermediate layer 121 may be set to 0.6, for example, the first intermediate layer 121 may be set to be (Al) 1/3Si2/3)Nx，x>0; the second intermediate layer 122 may be provided as a silicon-doped aluminum nitride layer, the atomic ratio of aluminum to silicon in the second intermediate layer 122 may be provided to be 0.6-0.4, the atomic ratio of silicon to aluminum in the second intermediate layer 122 may be provided to be 0.4, for example, the second intermediate layer 122 may be provided as (Al)2/3Si1/3)Nx，x>0. By setting the concentration of the silicon component of the first intermediate layer 121 to be greater than the concentration of the silicon component of the second intermediate layer 122 so that the in-plane lattice atomic configuration on the substrate 10 passes through the transition of the first intermediate layer 121 and the second intermediate layer 122, and is perfectly converted into the lattice of the adjacent epitaxial layer, for example, the nucleation layer 20, a high-quality epitaxial layer is obtained, and the thickness of the epitaxial layer is effectively controlled while the thermal resistance of the epitaxial layer is effectively reduced.
By way of example, continuing to refer to FIG. 3, in one embodiment of the present application, the first intermediate layer 121 has a thickness of 0.3nm to 3nm and the second intermediate layer 122 has a thickness of 0.3nm to 3nm in order to obtain an optimal growth interface. The sum of the thicknesses of the first intermediate layer 121 and the second intermediate layer 122 may be set to 1nm to 3 nm. The nucleation layer 20 may be set to a thickness of 25nm to 35nm for obtaining an optimal thermal resistance value, for example, the nucleation layer 20 may be set to a thickness of 30 nm.
Further, referring to fig. 4, in an embodiment of the present application, the semiconductor epitaxial structure further includes a nucleation layer 20, a second transition layer 23, and a channel layer 30, which are sequentially stacked, wherein the nucleation layer 20 is located between the first transition layer 12 and the second transition layer 23; wherein the concentration of the second component of the second transition layer 23 varies in a gradient along the direction of increasing thickness, the second component of the second transition layer 23 being an element of the channel layer 30.
As an example, continuing to refer to fig. 4, by forming a second transition layer 23 between the nucleation layer 20 and the channel layer 30, where the concentration of the second component changes in a gradient manner along the thickness increasing direction, and the second component of the second transition layer 23 is an element of the channel layer 30, such that the in-plane lattice atom configuration of the nucleation layer 20 is in the transition range of 1 primitive cell to 5 primitive cell thickness, for example, 0.5nm to 1.5nm, and is perfectly converted into the lattice of the channel layer 30, so as to avoid growing a buffer layer and directly grow a high-quality channel layer, and implement a buffer-layer-free structure design, the heat generated in the thin channel will be more effectively dissipated into the substrate 10, effectively reducing the thermal resistance of the overall epitaxial structure, and alleviating the problem of self-heating of the manufactured semiconductor device. Due to the realization of the buffer-layer-free structure design, the thickness of the whole epitaxial structure is effectively reduced, the consumption of raw materials is reduced while the performance of the manufactured semiconductor device is ensured, the Deposition time is obviously shortened, the manufacturing cost is reduced to the maximum extent, and the capacity of Metal-organic Chemical Vapor Deposition (MOCVD) is increased.
By way of example, with continued reference to fig. 4, in one embodiment of the present application, the concentration of the second component of the second transition layer is stepped up or gradually increased in the direction of increasing thickness. Preferably, the elements of the second transition layer 12 other than the second element are the same as the elements of the nucleation layer 20. For example, the second transition layer 23 may be provided to include AlxGa1-xN, x is more than 0 and less than 1, so as to form an interface structure with gradually changed components. Experiments have shown that the present embodiment significantly mitigates composition-induced lattice mismatch and surface energy gradient differences between the channel layer 30 and nucleation layer 20, thereby forming a high quality channel layer 30.
By way of example, continuing to refer to FIG. 4, in one embodiment of the present application, provision may be made for including AlxGa1-xThe thickness of the transition channel layer of N is 0.5nm-5nm, 0 < x < 1, and Al can be included to obtain optimal growth interfacexGa1-xThe thickness of the transition channel layer of N is 2 nm; can be used forThe channel layer 30 is provided as a gallium nitride (GaN) channel layer, and the thickness of the GaN channel layer is provided to be 5nm-500nm, for example, the thickness of the GaN channel layer may be provided to be 250 nm.
By way of example, in one embodiment of the present application, with continued reference to fig. 4, the second transition layer 23 further comprises a fourth component that is an element of the nucleation layer 20, the concentration of the fourth component of the second transition layer 23 being stepped or tapered in the direction of increasing thickness. For example, the second transition layer 23 may be provided to include Al xGa1-xN, x is more than 0 and less than 1, so as to form an interface structure with gradually changed components. For example, the aluminum in the second transition layer 23 is an element of the nucleation layer, and the concentration of the aluminum in the second transition layer decreases stepwise or gradually in the direction of increasing the thickness, so that the in-plane lattice atomic configuration of the nucleation layer 20 is perfectly converted into the lattice of the channel layer 30 within the transition range of 1 primitive cell to 5 primitive cells, for example, 0.5nm to 1.5nm, to avoid growing the buffer layer and directly grow the high-quality channel layer, thereby realizing the buffer-layer-free structure design.
As an example, in an embodiment of the present application, referring to fig. 5, the nucleation layer 20 may be provided as an aluminum nitride nucleation layer, the channel layer 30 may be provided as a gallium nitride channel layer, the second transition layer 23 includes a third intermediate layer 231 and a fourth intermediate layer 232 that are sequentially stacked, the third intermediate layer 231 is located between the aluminum nitride nucleation layer and the fourth intermediate layer 232, the third intermediate layer 231 may be provided as a gallium-doped aluminum nitride layer, an atomic ratio of gallium to aluminum in the third intermediate layer 231 is provided as 0.4-0.6, for example, the third intermediate layer 231 may be provided as (Al)2/3Ga1/3)Nx，x>0; the fourth intermediate layer 232 may be provided as a gallium-doped aluminum nitride layer, and the atomic ratio of gallium to aluminum in the fourth intermediate layer 232 may be provided to be 0.6 to 0.4, for example, the fourth intermediate layer 232 may be provided as (Al) 1/3Ga2/3)Nx，x>0。
In the embodiment, by inhibiting the formation of structural defects in a GaN-AlN interface, a high-quality GaN channel layer can be obtained, a buffer-layer-free structure is realized, heat generated in a thin GaN channel can be more effectively dissipated into a substrate, and the expected thermal resistance of the material is greatly reduced, so that the problem of self-heating of a device is relieved; by avoiding a thick doped (which may be, for example, carbon-doped or iron-doped, etc.) buffer layer, the trapping effect is made smaller; the AlN nucleating layer can effectively serve as a back barrier, so that the carrier limitation in high-frequency application is improved; generally, the total thickness of the epitaxial layer of the traditional GaN-on-SiC HEMT is 1500nm-3000nm, the total thickness of the epitaxial layer is reduced to 300nm-1500nm, the consumption of raw materials can be reduced, and the Deposition time is obviously shortened, so that the manufacturing cost is reduced to the maximum extent, and the capacity of Metal-organic Chemical Vapor Deposition (MOCVD) is increased. Compared with a standard HEMT structure with an intentionally doped (carbon or iron, etc.) buffer layer, the material quality and device performance are not affected, even the material is superior to the traditional material at the device level.
As an example, referring to fig. 6, in an embodiment of the present application, a side of the channel layer 30 away from the substrate 10 is provided with a barrier layer 40 and a cap layer 50, which are sequentially stacked, the barrier layer 40 is used to form a heterojunction structure in combination with the channel layer 30; the cap layer 50 is located on a side of the barrier layer 40 away from the channel layer 30; the barrier layer 40 may be provided as an aluminum gallium nitride (AlGaN) barrier layer, and the thickness of the barrier layer 40 may be provided in the range of 10nm to 50 nm; the cap layer 50 may be provided as a gallium nitride cap layer, the thickness of the cap layer 50 may be provided to be 1nm to 10nm, and the cap layer 50 may be a passivation layer for passivating the surface of the barrier layer 40, reducing gate current, and facilitating metal/semiconductor ohmic contact.
In one embodiment of the present application, the substrate may be a silicon carbide substrate or a gallium nitride substrate, etc., and for example, the substrate may be provided to include at least one of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, Sapphire (Sapphire), germanium, or silicon (Si).
In one embodiment of the present application, a multilayer epitaxial structure formed on a substrate may include a III-V compound based semiconductor material. The group III-V compound is a compound of boron (B), aluminum (Al), gallium (Ga), indium (In) and nitrogen (N), phosphorus (P), arsenic (As) or antimony (Sb) of group III of the periodic table, and mainly includes gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN) and the like.
In an embodiment of the present application, a semiconductor structure is provided, which is manufactured by using the semiconductor epitaxial structure described in any embodiment of the present application, and the thermal resistance of the epitaxial layer is effectively reduced, and the thickness of the epitaxial layer is effectively controlled, so that the performance, reliability and service life of the manufactured semiconductor device are improved.
By way of example, referring to fig. 7, in one embodiment of the present application, there is provided a semiconductor epitaxial structure fabrication method, including:
Step 202: providing a silicon carbide substrate;
step 204: and forming a first transition layer on the substrate, wherein the concentration of a first component of the first transition layer is changed along the gradient of the thickness increasing direction, and the first component is an element of the substrate.
As an example, continuing to refer to fig. 7, by forming a first transition layer on the upper surface of the substrate, in which the concentration of a first component varies in a gradient along the direction of increasing thickness, the first component being an element of the substrate, the in-plane lattice atomic configuration on the substrate is perfectly converted into the epitaxial layer lattice within the transition range of 1 primitive cell to 5 primitive cells thick, so as to obtain a high-quality epitaxial layer, and the thickness of the epitaxial layer is effectively controlled while the thermal resistance of the epitaxial layer is effectively reduced. Thereby avoiding the defects of dislocation, pits or grain boundaries and the like caused by lattice and thermal expansion mismatching, reducing the interface thermal resistance, improving the performance and reliability of the manufactured semiconductor device and prolonging the service life.
As an example, referring to fig. 8, in an embodiment of the present application, the step of forming the first transition layer on the substrate includes:
step 2042: and forming a first transition layer on one side of the substrate by adopting a physical vapor deposition process, and controlling the gradient change of the concentration of a first component of the first transition layer along the thickness increasing direction in the process of growing the first transition layer, wherein the first component is an element of the substrate.
As an example, continuing with fig. 8, a first transition layer having a concentration of a first component that is an element of the substrate that varies in a gradient along a direction of increasing thickness may be formed between the substrate and the nucleation layer such that an in-plane lattice atomic configuration on the substrate is perfectly converted into a nucleation layer lattice within a transition range of 1 cell-5 cells thick to obtain a high quality nucleation layer, while effectively reducing the thermal resistance of the epitaxial layer, while effectively controlling the thickness of the nucleation layer. Thereby avoiding the defects of dislocation, pits or grain boundaries and the like caused by lattice and thermal expansion mismatching, reducing the interface thermal resistance, improving the performance and reliability of the manufactured semiconductor device and prolonging the service life. The nucleation layer and the first transition layer are formed by adopting a physical vapor deposition process, so that the deposition time can be obviously shortened, the manufacturing cost can be reduced to the maximum extent, and the productivity can be increased.
As an example, referring to fig. 9, in an embodiment of the application, after forming the first transition layer on the substrate, the method further includes:
step 2043: and forming a nucleation layer on one side of the first transition layer far away from the substrate by adopting a physical vapor deposition process.
As an example, continuing to refer to fig. 8, by forming a first transition layer between the substrate and the nucleation layer, in which the concentration of the first component varies in a gradient manner along the thickness direction, the in-plane lattice atom configuration on the substrate is perfectly converted into the nucleation layer lattice within the transition range of 1-5 primitive cell thickness, so as to obtain a high-quality nucleation layer, and the thickness of the nucleation layer is effectively controlled while the thermal resistance of the epitaxial layer is effectively reduced. Thereby avoiding the defects of dislocation, pits or crystal grain boundaries and the like caused by mismatching of crystal lattices and thermal expansion, reducing the interface thermal resistance, improving the performance and the reliability of the manufactured semiconductor device and prolonging the service life of the manufactured semiconductor device. The nucleation layer and the first transition layer are formed by adopting a physical vapor deposition process, so that the deposition time can be obviously shortened, the manufacturing cost can be reduced to the maximum extent, and the productivity can be increased.
As an example, with continuing reference to fig. 9, in an embodiment of the present application, after forming a nucleation layer on a side of the first transition layer away from the substrate, the method further includes:
step 2044: and forming a second transition layer on one side of the nucleation layer, which is far away from the substrate, by adopting a physical vapor deposition process, forming a channel layer on one side of the second transition layer, which is far away from the nucleation layer, by adopting a metal organic compound chemical vapor deposition process, and controlling the concentration of a second component of the second transition layer to change along the gradient of the thickness increasing direction in the process of growing the second transition layer, wherein the second component is an element of the channel layer.
By way of example, with continued reference to fig. 9, by forming a second transition layer with a concentration of a second component varying in a gradient manner along a thickness increasing direction on a side of the nucleation layer away from the substrate, where the second component of the second transition layer is an element of the channel layer, so that the nucleation layer is in a transition range of 1 primitive cell to 5 primitive cells, for example, 0.5nm to 1.5nm, an in-plane lattice atom configuration of the nucleation layer is perfectly converted into a channel layer lattice, thereby avoiding growing a buffer layer and directly growing a high-quality channel layer, realizing a buffer-layer-free structure design, and dissipating heat generated in a thin channel into the substrate more effectively, thereby effectively reducing the thermal resistance of the whole epitaxial structure and alleviating the problem of self-heating of the semiconductor device. Due to the fact that the buffer-layer-free structure design is achieved, the thickness of the whole epitaxial structure is effectively reduced, the consumption of raw materials is reduced while the performance of the manufactured semiconductor device is guaranteed, the deposition time is obviously shortened, the manufacturing cost is reduced to the maximum extent, and the capacity of MOCVD is increased.
As an example, in an embodiment of the present application, a Metal-organic Chemical Vapor Deposition (MOCVD) process is used to form a III-V compound epitaxial structure on the substrate, so that the production cost can be effectively controlled while ensuring the productivity and the production efficiency.
In one embodiment of the present application, the III-V compound is a compound formed of boron (B), aluminum (Al), gallium (Ga), indium (In), and nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb) of group III of the periodic table, mainly including arsenic gallium (GaAs), indium phosphide (InP), gallium nitride (gan), and the like.
For specific limitations of the semiconductor epitaxial structure preparation method in the above embodiments, reference may be made to the above limitations of the semiconductor epitaxial structure, and details are not described here.
The steps in the method for preparing the semiconductor epitaxial structure in the above embodiments are not strictly limited in order of execution unless explicitly stated herein, and may be performed in other orders. Moreover, at least a portion of the steps of the method may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed sequentially, but may be performed alternately or in turns with other steps or at least a portion of the other steps.
The method for manufacturing the semiconductor epitaxial structure in the above embodiments is intended to schematically illustrate the principle of forming the semiconductor epitaxial structure in the embodiments of the present application, and is not intended to be a specific limitation on the semiconductor epitaxial structure in the embodiments of the present application. Other fabrication methods may also be employed to fabricate the semiconductor epitaxial structure in the embodiments of the present application.
Note that the above-described embodiments are for illustrative purposes only and are not meant to limit the present application.
The embodiments in the present specification are all described in a progressive manner, and each embodiment focuses on differences from other embodiments, and portions that are the same and similar between the embodiments may be referred to each other.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A semiconductor epitaxial structure, comprising:
A substrate; and
a first transition layer formed on the substrate;
wherein a concentration of a first component of the first transition layer, which is an element of the substrate, varies in a gradient along a direction in which a thickness increases.
2. The semiconductor epitaxial structure of claim 1, wherein the concentration of the first component of the first transition layer is stepped or tapered in a direction of increasing thickness.
3. The semiconductor epitaxial structure according to claim 2, wherein the first transition layer comprises a first intermediate layer and a second intermediate layer laminated in this order, the first intermediate layer being located between the substrate and the second intermediate layer,
wherein a concentration of the first component of the first intermediate layer is greater than a concentration of the first component of the second intermediate layer.
4. The semiconductor epitaxial structure of any one of claims 1 to 3, further comprising a nucleation layer, a second transition layer and a channel layer sequentially stacked,
the nucleation layer is located between the first transition layer and the second transition layer;
wherein a concentration of a second component of the second transition layer varies in a gradient along a direction of increasing thickness, the second component of the second transition layer being an element of the channel layer.
5. The semiconductor epitaxial structure of claim 4, wherein the concentration of the second component of the second transition layer is stepped up or graded up in the direction of increasing thickness.
6. The semiconductor epitaxial structure of claim 4 wherein the first transition layer further comprises a third composition, the third composition being an element of the nucleation layer.
7. The semiconductor epitaxial structure of claim 5, wherein the second transition layer further comprises a fourth component, the fourth component being an element of the nucleation layer.
8. The semiconductor epitaxial structure of claim 5, wherein the second transition layer comprises a third intermediate layer and a fourth intermediate layer stacked in this order, the third intermediate layer being located between the nucleation layer and the fourth intermediate layer,
the concentration of the second component of the third intermediate layer is less than the concentration of the second component of the fourth intermediate layer.
9. A semiconductor structure characterized by being produced using the semiconductor epitaxial structure of any one of claims 1 to 8.
10. A method for preparing a semiconductor epitaxial structure is characterized by comprising the following steps:
Providing a substrate;
and forming a first transition layer on the substrate, wherein the concentration of a first component of the first transition layer is changed along the gradient of the thickness increasing direction, and the first component is an element of the substrate.
CN202011573455.4A 2020-12-24 2020-12-24 Semiconductor epitaxial structure, preparation method thereof and semiconductor structure Pending CN114678256A (en)

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