CN1965400A - Field-effect transistor, semiconductor device, a method for manufacturing them, and a method of semiconductor crystal growth - Google Patents

Field-effect transistor, semiconductor device, a method for manufacturing them, and a method of semiconductor crystal growth Download PDF

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Publication number
CN1965400A
CN1965400A CNA2005800187981A CN200580018798A CN1965400A CN 1965400 A CN1965400 A CN 1965400A CN A2005800187981 A CNA2005800187981 A CN A2005800187981A CN 200580018798 A CN200580018798 A CN 200580018798A CN 1965400 A CN1965400 A CN 1965400A
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semiconductor layer
layer
crystal growth
effect transistor
field
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CN100501951C (en
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平田宏治
小嵜正芳
千田昌伸
柴田直树
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Toyoda Gosei Co Ltd
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Toyoda Gosei Co Ltd
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Abstract

A field-effect transistor which comprises a buffer layer and a barrier layer each of which is made of a Group III nitride compound semiconductor and has a channel at the interface inside of the buffer layer to the barrier layer, wherein the barrier layer has multiple-layer structure comprising a rapid interface providing layer which composes the lowest semiconductor layer in said barrier layer and whose composition varies rapidly at the interface of said buffer layer, and an electrode connection plane providing layer which constructs the uppermost semiconductor layer and whose upper surface is formed flat.

Description

Field-effect transistor, semiconductor device, its manufacture method and method for growing semiconductor crystal
Technical field
The present invention relates to can be by III group-III nitride compound semiconductor crystal grow field-effect transistor (for example various FET and the HEMT) structure made and the manufacture method of field-effect transistor.
The invention still further relates to can be by III group-III nitride compound semiconductor crystal grow field-effect transistor (for example various FET and the HEMT) structure made and the manufacture method of field-effect transistor.
In addition, the present invention relates to the method for the high insulator-semiconductor of crystalline growth and the method for manufacturing field-effect transistor.
The present invention is used for the device of Production Example such as field-effect transistor.
Background technology
Usually, for growing for the field-effect transistor structure of making and manufacture method thereof by III group-III nitride compound semiconductor crystal, for example, the prior art that is disclosed in the patent document 1 is widely known by the people.
In existing invention, often use hydrogen (H 2) as carrier gas, carrying material gas in crystalline growth semiconductor layer process.
Reason is as follows.
(reason 1) uses hydrogen relatively more easily to provide by the formed semiconductor layer of the crystal growth with excellent degree of crystallinity than other carrier gas of use.This sheet resistivity for device, change device property and yield of devices are favourable.
(reason 2) by using hydrogen, the easier for example flatness at interface or compare with the device that adopts other carrier gas and to form the emergentness that changes around improving the interface between resilient coating and the barrier layer of each semiconductor layer of improving.This can obtain and keep outstanding carrier mobility, i.e. migration is easier, and this is for device miniatureization with to improve device performance favourable.
[patent document 1] Japanese Laid-Open Patent Application 2003-45899.
Figure 12 illustrates the sectional view of existing field-effect transistor 10.Field-effect transistor 10 is semiconductor device of making by crystal growth sequential aggradation III group-III nitride compound semiconductor, and it has the AlN resilient coating 2 of the about 0.3 μ m thickness on carborundum (SiC) the crystal growth substrate 1 that is formed on about 500 μ m thickness.
On resilient coating 2, form the not Doped GaN semiconductor layer 3 of about 2 μ m thickness, and form the not doped with Al of about 35nm thickness thereon 0.25Ga0 .75The N semiconductor layer.Reference numeral 5,6 and 7 is represented source electrode, grid deposit and drain electrode respectively.
Because semiconductor layer 3 and semiconductor layer 4 have the semiconductor crystal component that differs from one another, therefore be used to provide the crystal growth condition of optimum crystal mass to have nothing in common with each other.Particularly, importantly such as the growth conditions of crystal growth temperature and pressure (being the dividing potential drop and the stagnation pressure of each gas).For example, in the AlGaN crystal growing process, the crystal growth temperature of optimum crystal mass raises greatly with the change of aluminium ratio of components usually.
Therefore, for example, for above-mentioned semiconductor layer 3, optimum crystal growth temperature is about 1050 ℃, and for semiconductor layer 4, optimum crystal growth temperature is about 1150 ℃, and this temperature is higher 100 ℃ than the crystal growth temperature of semiconductor layer 3.
Usually, the crystal growth pressure of AlGaN semiconductor layer 4 (stagnation pressure) is less than the pressure of GaN semiconductor layer 3, so that the Al ratio of components balance in the semiconductor layer 4.
For other existing field-effect transistor, following patent document 2-5 illustrates that other is concrete
Embodiment.
[patent document 2] Japanese Laid-Open Patent Application 2002-57158.
[patent document 3] Japanese Laid-Open Patent Application 2003-45899.
[patent document 4] Japanese Laid-Open Patent Application 2002-16087.
[patent document 5] Japanese Laid-Open Patent Application 2003-277196.
In addition, for existing field-effect transistor, for example, known use not the Doped GaN layer as the semiconductor device such as HEMT of channel layer.Yet this existing device comprises undesirable conducting shell, and it forms around the interface that is present on the nucleating layer (being lattice constant difference relaxation layer).When this conducting shell was formed in the device, the breakdown field intensity of device may descend, and this is undesirable.
In order to address this problem, invented the field-effect transistor shown in the following patent document 6.This field-effect transistor comprise by doped with II B family impurity for example Zn be formed on resilient coating on the nucleating layer, resilient coating is the semiconductor layer with high conductivity, it is difficult to make diffusion of impurities to add channel layer.This can make the field-effect transistor electrical isolation device and improve breakdown field intensity.
For the high resistivity semiconductor layer that uses in rule HFET, the not Doped GaN layer shown in for example known following non-patent document 1.The Doped GaN layer does not become to have 2 μ m thickness 1050 ℃ of crystal growth temperature deposit, has reported the GaN layer and can have Ω/cm greater than 100M 2Sheet resistivity (resistivity: 2 * 10 4Ω cm).
[patent document 6] Japanese Laid-Open Patent Application 2002-57158.
[non-patent document 1] Seikoh YOSHIDA, " AlGaN/GaN Power FET " Furukawa Electric Review, No.109, January, 2002.
Summary of the invention
Problem to be solved
Yet, use hydrogen (H 2) as carrier gas, the surface of the semiconductor layer of the top may be difficult to form smoothly or be level and smooth, this produces following problem.
When (problem 1) becomes excessive when the fluctuation of semiconductor layer surface roughness for the electrode size that will connect, be difficult on this rough surface, form electrode.As a result, the electrode microminiaturization is prevented from and device is difficult to form forr a short time.
(problem 2) even electrode is formed on the pre-position, and electrical characteristics for example bonding strength and ohm property can not become enough stable.Be difficult to keep the yield of device, be difficult to provide the industrial mass production of target field effect transistor.
The reason that surface on the above-mentioned semiconductor layer becomes coarse may be because use hydrogen (H 2) etch processes.Thus, in order to overcome this problem, other element is nitrogen (N for example 2) can come to form resilient coating by crystal growth as carrier, this causes improving the roughness on the semiconductor surface.Yet, adopt this process, be difficult to obtain simultaneously for reason given above 1 and 2 required electrical characteristics for example mobility and sheet resistivity.
When the crystal growth condition of crystal mass of each semiconductor layer shown in Figure 12 (3 and 4) is paid close attention in employing, can keep the high-crystal quality in each semiconductor layer.Yet, adopt this crystal growth condition, make the interface sedimentary condition on every side of these two semiconductor layers (3 and 4) trend towards disturbance.In brief, this interface between two-layer becomes coarse.This may be because the atom that constitutes semiconductor layer 3 upper surfaces according to this two-layer between the variation of crystal growth condition distil.
This decline of degree of crystallinity is tended to owing to the carrier gas etching takes place.This can understand by following file at an easy rate.
(1) Japanese Laid-Open Patent Application H11-068159.
(2) Japanese Laid-Open Patent Application H9-139543.
(3) Japanese Laid-Open Patent Application H8-88432.
This interface roughness tends to reduce the mobility of charge carrier rate that is limited on the passage, and described charge carrier constitutes accurate 2 dimensional electron gas and reduces electric current.As a result, device property deterioration.
In addition, when semiconductor layer doped high conductivity impurity, always be not easy to the non-doped layer that deposition has enough low impurity concentration after forming high impurity doped semiconductor.This is because impurity remains in the crystal growing furnace or impurity spreads in each semiconductor layer.
When this impurity will form the passage place and sneak into semiconductor layer, be difficult to form passage with high mobility.This is because be used to form the impurity of passage in semiconductor mobile charge carrier to be disperseed.
On the contrary, have the high semiconductor device that punctures field intensity, about 100M Ω/cm in order to make 2Sheet resistivity may be not enough.Therefore, the prior art shown in the non-patent document 1 is difficult to can crystal growth to have the semiconductor of enough high-insulativities, to satisfy required more high-performance at present.In addition, non-patent document 1 does not have to propose to overcome the suggestion of this problem.
Finish the present invention in order to overcome aforesaid drawbacks.Therefore, the present invention seeks to produce a kind of field-effect transistor, it has excellent sheet resistivity, forms the certainty and the charge carrier high mobility of microelectrode, and the high-performance and the microminiaturization of suitable device.
Another object of the present invention is to produce a kind of field-effect transistor, and it improves the mobility that charge carrier passes passage, improves device property thus.
Another object of the present invention is to form the non-doping semiconductor layer with excellent insulating properties.
In addition, another purpose of the present invention is to realize having the semiconductor device of the high mobility that charge carrier transmits and the height of device punctures field intensity in passage.
At this, above-mentioned each purpose can be enough to realize separately by one of them of each invention, and each invention among the application needn't guarantee to exist the solution that solves all problems immediately.
The means of dealing with problems
Following means can be used for overcoming above-mentioned shortcoming.
That is, first aspect present invention provides a kind of field-effect transistor, it comprises resilient coating and barrier layer, each resilient coating and barrier layer are made by III group-III nitride compound semiconductor and are had passage in resilient coating to the interface side on barrier layer, and described barrier layer comprises following two-layer (1) and (2) at least altogether.
(1) abrupt interface accommodating layer constitutes in the barrier layer the semiconductor layer of below, and it is formed and changes suddenly on the resilient coating interface;
(2) electrode joint face accommodating layer, the semiconductor layer of the top in the formation barrier layer, and its upper surface forms smooth.
Generally, the barrier layer is sometimes referred to as carrier supply layer, and resilient coating is sometimes referred to as basic unit.The resilient coating of first aspect present invention is not meant that the thin film semiconductive layer that is formed between the aimed semiconductor layer that will form by crystal growth (for example, the AlN layer of about 250nm thickness) with in order to eliminate or alleviate the crystal growth substrate of the lattice constant difference of these layers in the growing semiconductor crystal field, but the resilient coating in the first aspect present invention (basic unit) also can comprise this semiconductor layer.
For example, when using the semiconductor growing substrate of making by the GaN bulk crystals, may there be the problem of lattice constant difference, but needs the resilient coating (basic unit) of first aspect present invention explanation.At this, the crystal growth substrate of being made by the GaN bulk crystals can be used as the resilient coating (basic unit) in the first aspect present invention.
In the semiconductor layer the superiors, form drain electrode, source electrode and gate electrode.At this, gate electrode can pass through to form indirectly such as the layer of dielectric film.The structure of each electrode can be arbitrarily, can select and adopt the known and suitable arbitrary structures of considering ohm property and correction.Field-effect transistor of the present invention can be the field-effect transistor of any type, for example normal open transistor npn npn by change condition such as barrier layer thickness and the normal transistor npn npn that closes.
Hereinafter explanation forms the various conditions of optimum structure and the best practice of producing field-effect transistor of the present invention.
In order to form the big passage of carrier mobility and each Ohmic electrode of optimization ohm property on barrier layer on every side, need the carrier energy grade (be the band gap of each semiconductor layer) of optimization perpendicular to the barrier layer.And for the optimized energy grade, following at least parameter (1)-(3) are very important.
(1) thickness of semiconductor layer
Particularly, by making the thickness optimization of each semiconductor layer that constitutes the barrier layer, the barrier layer can be the depletion layer of suitable degree, and can obtain optimum charge carrier tunnel efficient in tunnel effect.In addition, by making the thickness optimization of each semiconductor layer that constitutes the barrier layer, can suitably keep for the grid voltage control that passage is formed and disappear.In brief, by making the thickness optimization of each semiconductor layer, can improve the electronics supply and more easily control electronics Guinier-Preston zone (passage).
(2) Al ratio of components
By making the Al ratio of components optimization of each semiconductor layer, can make the band-gap energy and the electron affinity optimization of half and half conductor layer.Basically, the band-gap energy on barrier layer should be greater than the band-gap energy of resilient coating.Therefore, in order to use Al xGa 1-xN (0＜x≤1) forms each barrier layer and resilient coating, and the Al ratio of components x on barrier layer should be greater than the Al ratio of components x of resilient coating.Preferably, the band-gap energy difference of barrier layer and resilient coating can be very big.The Al ratio of components on barrier layer can be to make the optimized parameter of barrier layer ohm property.
Particularly, the semiconductor layer that directly contacts Ohmic electrode (source electrode and drain electrode) can keep excellent ohm property by making its Al ratio of components optimization.
(3) there is or do not exist impurity
Exist, do not exist or concentration by controlled doping agent (impurity), can each semi-conductive carrier concentration of optimization, insulating properties and ohm property.In order to realize high mobility, form passage at least or be present in parameatal semiconductor layer and preferably undope impurity to prevent charge carrier diffusion.And, the semiconductor layer that need have a high resistivity any impurity that can undope.Thereby, be that the semiconductor layer as the resilient coating the superiors can be preferably the non-impurity-doped layer at least.
The barrier layer can not must be the non-impurity-doped layer.As selection, the barrier layer can be a n-type layer.By using n-type barrier layer, can make field-effect transistor high-quality of the present invention with effect disclosed by the invention and effect.
Therefore, each parameter of optimization is very important.
Considered that above each problem invented following each side.Thereby, preferably adopt following any aspect to implement the present invention.
That is second aspect present invention is: be included in each semiconductor layer in the barrier layer in the first aspect by unadulterated Al xGa 1-xN (0＜x≤1) makes.
Third aspect present invention is: be included in each semiconductor layer in the barrier layer in first aspect or the second aspect by unadulterated Al xGa 1-xN (0.15≤x≤0.3) makes.
Fourth aspect present invention is: be included in second or the third aspect in the Al ratio of components x of each semiconductor layer according to sedimentary sequence and basic monotone decreasing.
At this, " basic monotone decreasing " represents following lapse conditions.That is, when function z=f (N) by formula " N 1＜N 2→ f (N 1) 〉=f (N 2) " when representing, wherein digital N is an independent variable, N 1And N 2Be the Any Digit in digital N territory, then function f is sensu lato monotonic decreasing function, and independent variable z is with number N monotone decreasing.Therefore, the Al ratio of components x that constitutes each all or part of semiconductor layer on barrier layer sets identical being also included within the fourth aspect present invention.
Similarly, when digital N is replaced by continuous variable such as time t, can use above-mentioned formula.That is, as formula " t 1＜t 2→ z 1=f (t 1) 〉=z 2=f (t 2) " satisfy the random time t in the predetermined domain 1And t 2The time, non-independent variable z is equally with independent variable t monotone decreasing.
Fifth aspect present invention is: the barrier layer in the either side aspect the present invention first to fourth comprises the barrier layer ground floor and the barrier layer second layer that is deposited on the ground floor upper surface of barrier layer below being formed on.
At this, the barrier layer ground floor is the abrupt interface accommodating layer among the present invention, and the barrier layer second layer is the electrode joint face accommodating layer among the present invention.
Sixth aspect present invention is: the thickness d of the barrier layer ground floor in aspect the 5th 1Thickness d with the barrier layer second layer 2Be set to 10nm≤d 1≤ 30nm, 10nm≤d 2≤ 30nm and 30nm≤d 1+ d 2≤ 60nm.
Seventh aspect present invention is: in the either side aspect first to the 6th, the resilient coating the superiors are made by Doped GaN not.At this, resilient coating can have single layer structure.At this moment, resilient coating self is represented the resilient coating the superiors.
Eighth aspect present invention is: a kind of method of making field-effect transistor, described field-effect transistor comprises resilient coating and barrier layer, described resilient coating and barrier layer are made by III group-III nitride compound semiconductor and are had passage in resilient coating to the interface side on barrier layer, described method comprises the crystal growing process that is used for the crystal growth barrier layer, wherein hydrogen (H 2) voltage ratio R in the carrier gas of carrying barrier material gas is basic reduces continuously or gradually reduce substantially, and by formula r 1〉=R 〉=r 2(1 〉=r 1＞1/4,1/2＞r 2〉=0, r 1＞r 2) in the zone of representative, t monotone decreasing in time.
More preferably, partial pressure R can reduce or gradually reduce substantially substantially continuously, and by formula r 1〉=R 〉=r 2(1 〉=r 1＞1/2,1/4＞r 2〉=0) in Dai Biao the zone, at the crystal growing process that is used for the crystal growth barrier layer, t monotone decreasing in time.
Ninth aspect present invention is: the barrier layer in eighth aspect present invention comprises m+1 semiconductor layer altogether, and each layer gradually reduces partial pressure than the unadulterated Al of R cause by m time (m 〉=1) xGa 1-xN (0＜x≤1) makes.
Tenth aspect present invention is: the barrier layer in ninth aspect present invention has double-decker, comprises the at first barrier layer ground floor of deposition, and it utilizes hydrogen (H 2) grow by crystal growth as main carrier gas; Chen Ji the barrier layer second layer thereon, it utilizes rare gas or comprises nitrogen (N 2) inert gas grow by crystal growth as main carrier gas.
By adopting aforementioned aspect of the present invention, aforesaid drawbacks can effectively or rationally be overcome.
Of the present invention ten are on the one hand: a kind of method of making field-effect transistor, described field-effect transistor comprises a plurality of semiconductor layers, each semiconductor layer is made by crystal growth by III group-III nitride compound semiconductor, described method comprises: form first crystal growing process of the first semiconductor layer A, channel layer deposition and distillation surface are thereon gone up or on every side; With form second crystal growing process directly be deposited on the second semiconductor layer B on the first semiconductor layer A, wherein the band-gap energy E of the second semiconductor layer B BBand-gap energy E greater than the first semiconductor layer A A, and the crystal growth condition of the second semiconductor layer B is set to limit the crystal growth condition of the atom distillation that forms the first semiconductor layer A upper surface at least at the commitment of second crystal growing process.
At this, because form or remove channel layer (electronics gas-bearing formation) according to the grid voltage open/close state that is applied to the pre-defined gate electrode, so channel layer cannot be a directly actuated target in the manufacture process.The electronics gas-bearing formation of channel layer be the electronics gas-bearing formation of about 100  of thickness and place the first semiconductor layer A and the second semiconductor layer B between the interface around.
The important parameter of the atom distillation of the decision crystal growth condition restriction formation first semiconductor layer A upper surface is dividing potential drop, carrier gas kind, each carrier gas dividing potential drop, V/III ratio and the crystal growth rate of for example crystal growth temperature, each material gas, the atom that especially ought comprise easy distillation is the Ga atomic time in the GaN crystal for example, and the dividing potential drop of trimethyl gallium (TMG) is set to relatively or is absolute high.
The present invention the 12 aspect is: the crystal growth temperature T of the second semiconductor layer B in the present invention the tenth on the one hand BBe lower than the crystal growth temperature T of the first semiconductor layer A A
The present invention the 13 aspect is: the crystal growth pressure P of the second semiconductor layer B in aspect the present invention the 11 or 12 BApproximate the crystal growth pressure P of the first semiconductor layer A A
The present invention the 14 aspect is: the first semiconductor layer A is by binary or the unadulterated Al of ternary xGa 1-xN (0≤x＜1) makes, and the second semiconductor layer B is by the unadulterated Al of ternary yGa 1-yN (x＜y≤1) makes.
The present invention the 15 aspect is: first semiconductor layer A in aspect the present invention the 14 and the crystal growth temperature T of the second semiconductor layer B AAnd T BSatisfy " 950 ℃≤T of formulas respectively B＜T A", wherein aluminium ratio of components x is about 0, aluminium ratio of components y is 0.15-0.30, and the crystal growth pressure P of the first semiconductor layer A and the second semiconductor layer B AAnd P BBe respectively about normal pressure.
The present invention the 16 aspect is: the crystal growth temperature T of the first semiconductor layer A in the either side aspect the present invention the 11 to 15 AIt is 1200 ℃ or lower.
The present invention the 17 aspect is: the crystal growth temperature T of the first semiconductor layer A in the either side aspect the present invention the 11 to 16 ACrystal growth temperature T than the described second semiconductor layer B BHigh 50 ℃ or more.Preferred this temperature range can be 50 ℃-150 ℃.
The present invention's the tenth eight aspect is: the crystal growth temperature T of the second semiconductor layer B in the either side aspect the present invention the 11 to 17 BSatisfy " 950 ℃≤T of formulas B＜1050 ℃ ".
The present invention the 19 aspect is: the crystal growth temperature T of the first semiconductor layer A in the present invention's the tenth eight aspect ASatisfy " 1050 ℃≤T of formulas A＜1150 ℃ ".
The present invention the 20 aspect is: a kind of field-effect transistor, it comprises a plurality of semiconductor layers, each semiconductor layer is made by crystal growth by III group-III nitride compound semiconductor, described field-effect transistor comprises: the first semiconductor layer A, thereon on the interface or the channel layer that deposits on every side and distil; With the second semiconductor layer B, it directly is deposited on the described first semiconductor layer A, the band-gap energy E of the wherein said second semiconductor layer B BBand-gap energy E greater than the described first semiconductor layer A A, and form the atom distillation of the described first semiconductor layer A upper surface by restriction, make the described first semiconductor layer A upper surface form substantially flat.
The present invention the 20 is on the one hand: the first semiconductor layer A in aspect the present invention the 20 is by binary or the unadulterated Al of ternary xGa 1-xN (0≤x＜1) makes, and the second semiconductor layer B is by the unadulterated Al of ternary yGa 1-yN (x＜y≤1) makes.
The present invention the 22 aspect is: the aluminium ratio of components x in the present invention the 20 on the one hand is about 0, and described aluminium ratio of components y is 0.15-0.30.
The present invention the 23 aspect is: the thickness of the second semiconductor layer B in the either side aspect the present invention 20 to 22 is 1nm or bigger.More preferably the thickness of the second semiconductor layer B can be 5nm or bigger.
By adopting aforementioned aspect of the present invention, aforesaid drawbacks can effectively or rationally be overcome.
The present invention the 24 aspect is: a kind of by Al xGa 1-xThe method of crystal growth high resistivity semiconductor layer A (semiconductor layer that promptly has high resistivity) on the crystal growth face that N (0≤x≤1) makes by crystal growth, wherein said high resistivity semiconductor layer A is by unadulterated Al xGa 1-xN (0≤x≤1) makes, and the crystal growth temperature of described high resistivity semiconductor layer A is set at 1120 ℃-1160 ℃ at the commitment of crystal growing process at least.
At this, the commitment of crystal growing process approximately is first minute that the crystal growth of high resistivity semiconductor layer A begins.
The present invention the 25 aspect is: the crystal growth rate of the high resistivity semiconductor layer A in aspect the present invention the 23 is 65nm/ minute or higher at the commitment of crystal growing process at least.
The present invention the 26 aspect is: the high resistivity semiconductor layer A in aspect the present invention the 24 or 25 made by unadulterated GaN crystal.
The present invention the 27 aspect is: the crystal growth rate of the high resistivity semiconductor layer A in the either side aspect the present invention 24 to 26 is 100nm/ minute or lower at the commitment of crystal growing process at least.
The present invention's the 20 eight aspect is: the crystal growth rate of the high resistivity semiconductor layer A in the either side aspect the present invention 24 to 27 is 70nm/ minute-90nm/ minute at the commitment of crystal growing process at least.
The present invention the 29 aspect is: the crystal growth temperature of the high resistivity semiconductor layer A in the either side of the present invention's 24 to 20 eight aspect is set at 1130 ℃-1150 ℃ at the commitment of crystal growing process at least.More preferably, crystal growth temperature can be 1130 ℃-1140 ℃.
The present invention the 30 aspect is: the V/III ratio of the crystalline material gas of supplying in the reative cell in the either side aspect the present invention 24 to 29 is 1400-1550 at the commitment of the crystal growing process of described high resistivity semiconductor layer A at least.
At this, the ratio of the molal quantity that the V/III ratio of crystalline material gas representative is included in the V group element crystalline material gas in will the unit volume semiconductor layer of crystalline growth and the molal quantity that is included in the III family element crystalline material gas in will the unit volume semiconductor layer of crystalline growth.
The present invention the 30 is on the one hand: a kind of by unadulterated Al xGa 1-xThe III group-III nitride compound semiconductor that N (0≤x≤1) makes, it is by the growing method manufacturing in the either side of the present invention 24 to 30 aspects and have 1 * 10 8Ω cm or higher resistivity.
The present invention the 32 aspect is: a kind of field-effect transistor comprises: the crystal growth substrate; By resilient coating and the barrier layer that III group-III nitride compound semiconductor is made, it is formed on the described crystal growth substrate; Be formed on the passage of described resilient coating towards the interface side on described barrier layer, wherein comprise high resistivity semiconductor A to the described resilient coating of small part, it is by unadulterated Al xGa 1-xN (0≤x≤1) makes and has 1 * 10 8Ω cm or higher resistivity.
The present invention the 33 aspect is: a kind of semiconductor device, it forms by a plurality of semiconductor layers of deposition, each semiconductor layer is made by III group-III nitride compound semiconductor on the crystal growth substrate, described semiconductor device comprises: high resistivity layer, it prevents from or suppresses electric current to leak, wherein said high resistivity layer is made by high resistivity semiconductor layer A, and described high resistivity semiconductor layer A is by unadulterated Al xGa 1-xN (0≤x≤1) makes and has 1 * 10 8Ω cm or higher resistivity.
By adopting aforementioned aspect of the present invention, aforesaid drawbacks can effectively or rationally be overcome.
The invention effect
The effect that obtains by the present invention is as follows.
According to first aspect present invention, the abrupt interface accommodating layer can keep excellent barrier layer degree of crystallinity, and the semiconductor crystal around the interface between barrier layer and the resilient coating is formed variation suddenly.
In addition, electrode joint face accommodating layer can keep the flatness and the smoothness of the barrier layer surface of excellence.
Constitutive mutation around the interface between maintenance barrier layer and the resilient coating descends for the limiting carrier mobility and produces effect, and carrier mobility descends and causes owing to charge carrier when charge carrier transmits in passage spreads.
As a result, according to first aspect present invention, the mobility of charge carrier rate of transmitting in the passage that forms around the interface, various the electrical characteristics for example sheet resistivity of field-effect transistor can be made very remarkably.And, can keep the flatness and the smoothness of barrier layer surface with flying colors, this improves the tack of gate electrode.As a result, the tack of gate electrode improves, and can easily improve the controlling filed effect by using grid voltage.
According to second aspect present invention, the barrier layer can obtain bigger band-gap energy.Resilient coating can comprise the semiconductor crystal that comprises indium (In), and is poor to obtain band-gap energy bigger between barrier band gap energy and the resilient coating band-gap energy.As a result, according to second aspect present invention, the interface between barrier layer and the resilient coating almost can not roughening.In brief, according to second aspect present invention, the interface between barrier layer and the resilient coating can be guaranteed smooth and level and smooth more, and this is synergy and effect because of first aspect present invention, and this can determine to keep the carrier mobility of excellence more.
In addition, usefully the barrier layer forms undoped layer, so that have preferred semiconductor device breakdown field intensity.
When the semiconductor crystal that comprises indium (In) formed by crystal growth, roughening was tended at the interface between semiconductor crystal and deposition other semiconductor layer thereon.This can be at an easy rate from below with reference to understanding the file.
(1) Japanese Laid-Open Patent Application H11-068159
(2) Japanese Laid-Open Patent Application H9-139543
(3) Japanese Laid-Open Patent Application H8-88432
According to third aspect present invention, can or be more prone to the parameatal potential curve of optimization.Particularly, the lower limit of aluminium ratio of components is necessary to guarantee to form passage, and the upper limit of aluminium ratio of components is necessary to obtain excellent Ohmic electrode.
More preferably, this aspect can be used with seventh aspect present invention.
According to fourth aspect present invention, the difference of barrier band gap energy and resilient coating band-gap energy can keep greatlyyer.As a result, can or be more prone to the parameatal potential curve of optimization.Particularly, the semiconductor layer that directly connects Ohmic electrode can keep excellent ohm property by the optimization of electronic affinity.
More preferably, this aspect can be used with the present invention the 3rd and the 7th aspect.
According to fifth aspect present invention, the barrier layer of field-effect transistor of the present invention can have double-decker.That is the ground floor on barrier layer forms the abrupt interface accommodating layer, and the second layer on barrier layer forms electrode joint face accommodating layer.That is the barrier layer that comprises the abrupt interface accommodating layer that has different advantages separately and electrode joint face accommodating layer can obtain by depositing minimized layer.
In brief, adopt this structure to provide the easiest mode of field-effect transistor of the present invention.As a result, according to fifth aspect present invention, can High-efficient Production for microminiaturized and have a field-effect transistor of the present invention that high-performance has remarkable advantage.
According to sixth aspect present invention, the gross thickness on optimization barrier layer, the ohm property on all right optimization barrier layer.But when electrode joint face accommodating layer (second layer on barrier layer) was thin excessively, it is smooth and level and smooth that barrier layer surface is difficult to become.Because the adverse effect that causes device property in uneven thickness of each sedimentary deposit, this should be noted that.
That is the barrier layer ground floor is provided sixth aspect present invention and the barrier layer second layer is empirical and each OK range of global optimization.
In addition, for high mobility is provided, the semiconductor layer that will form passage at least can be without impurity, to prevent the charge carrier diffusion.And, need the semiconductor layer of high resistivity any impurity that can undope.Therefore, especially forming at least, the semiconductor layer of the superiors of resilient coating is a undoped layer.Therefore, seventh aspect present invention is useful.
According to seventh aspect present invention, the superiors of resilient coating are made by GaN.Thereby, when the superiors of resilient coating by the semiconductor (Al that does not comprise indium xGa 1-xN (0≤x≤1)) when making, the band-gap energy of the described the superiors can minimize.As mentioned above, indium (In) is not used in and forms the described the superiors, to prevent the interface roughness between resilient coating and the barrier layer.Therefore, GaN provides the semiconductor of smallest bandgap energy.
As a result, according to seventh aspect present invention, can form required passage.
According to eighth aspect present invention, partial pressure is than R progressively or continuous monotone decreasing in crystal growing process.Thus, can or not only make field-effect transistor more easily, and manufacturing has the field-effect transistor that is equal to device performance and comprises the barrier layer with single layer structure according to first aspect present invention.For example, in order to make the field-effect transistor that comprises the barrier layer with single layer structure, above-mentioned gas voltage ratio R can all even monotone decreasing continuously.
The respond well as mentioned above reason of eighth aspect present invention is that partial pressure is higher more than R, and then said mutation interface accommodating layer just tends to form excellently more.At this, the interface changes favourable for the mobility of electrons transmitted in passage suddenly.And interface surface is smooth and smoothly be favourable, because can or make electrode than existing electrode microminiaturization more easily.
According to ninth aspect present invention, partial pressure progressively descends m time than R and is dull, and this can make the field-effect transistor according to the excellence of first aspect present invention.
According to tenth aspect present invention, can or make field-effect transistor more easily according to fifth aspect present invention.Partial pressure is higher more than R, and then the abrupt interface accommodating layer just tends to form excellently more.Partial pressure is lower more than R, and then electrode joint face accommodating layer just tends to form excellently more.Therefore, according to tenth aspect present invention, can obtain having the field-effect transistor of the device property of remarkable excellence.
The tenth on the one hand according to the present invention, and the crystal growth condition of the second semiconductor layer B is set to limit the crystal growth condition of the atom distillation that forms the first semiconductor layer A upper surface at least at the commitment of second crystal growing process.As a result, owing to form the interface roughness of the first semiconductor layer A that the atom distillation of the first semiconductor layer A upper surface causes and can be prevented from well.Therefore, the upper surface of the first semiconductor layer A (i.e. the lower surface of the second semiconductor layer B) becomes smooth at least on the microscope yardstick, improves the mobility of charge carrier rate of transmitting in passage, and increases the electric current under the conducting state.Therefore, can improve the device property of field-effect transistor.
The 12 aspect according to the present invention, the crystal growth temperature T of the second semiconductor layer B BSet to such an extent that be lower than the crystal growth temperature T of the first semiconductor layer A A, this can limit the atom distillation that forms the first semiconductor layer A upper surface well.
The 13 aspect according to the present invention, the crystal growth pressure P of the second semiconductor layer B BRoughly corresponding to the crystal growth pressure P of the first semiconductor layer A A, the atom distillation that this can be very easy to and restriction forms the first semiconductor layer A upper surface effectively.
The 14 aspect according to the present invention, the band-gap energy E of the second semiconductor layer B BCan be necessary and abundant band-gap energy E greater than the first semiconductor layer A A, can obtain having the structure of the semiconductor layer A of stable crystal structure degree and B at an easy rate and have for example smooth interface of stable surface state.
Therefore, the 14 aspect according to the present invention can be at an easy rate and make the field-effect transistor with excellent operating characteristic definitely.
More generally, indium (In) can be included in the III group-III nitride compound semiconductor that forms semiconductor layer A.It is unfavorable to adopt this material can differ from the more large band gap between maintenance semiconductor layer A and the B.Yet shown in above-mentioned publication application (1) and (3), in order to form smooth and stable interface easily and definitely, semiconductor layer A and semiconductor layer B cannot preferably include indium (In).
The 15 aspect according to the present invention can be more prone to and obtain definitely essential and enough poor (E of band-gap energy B-E A), and semiconductor layer A and B can have stable crystal mass and boundary condition is for example smooth.As a result, according to these conditions, can be at an easy rate and make field-effect transistor definitely with excellent operating characteristic.
More preferably, can adopt according to the present invention the method for either side in the 16 to 19 aspect.By the inventor's test and mistake, experimental each OK range that obtains in these aspects.Thereby, adopt these methods, can make semiconductor device with overall excellent condition, for example band-gap energy design is as passage, the mobility of charge carrier rate of transmitting in passage, for the controllability of formation/cancellation passage and the crystal mass of each semiconductor layer.
The 20 aspect according to the present invention can be at an easy rate and make the field-effect transistor with excellent operating characteristic according to first aspect present invention definitely.
The 20 on the one hand according to the present invention, can be at an easy rate and make the field-effect transistor with excellent operating characteristic of the 14 aspect according to the present invention definitely.More preferably, the aluminium ratio of components x of the first semiconductor layer A is that the aluminium ratio of components y of about 0, the second semiconductor layer B is 0.15-0.30.Preferably, the thickness of the second semiconductor layer B is 1nm or bigger, more preferably 5nm or bigger.
By adopting these conditions, can obtain having the field-effect transistor of the electrical characteristics of remarkable excellence.
The 24 aspect according to the present invention forms the semiconductor layer with high resistivity by crystal growth, and this can make semiconductor layer (the semiconductor layer A of high resistivity) have the insulating properties higher than existing semiconductor layer.As a result, the 24 aspect according to the present invention can form the excellent flatness with interface upper surface and the desirable unadulterated high resistivity layer of excellent degree of crystallinity.
The principle that can form the semiconductor layer with high-insulativity under this crystal growth condition does not throw a flood of light on as yet, but may be because existing be formed on nucleating layer and be difficult to be formed under these crystal growth conditions by the interface state between the crystal growth deposition semiconductor layer thereon traditionally, the existing conductive layer that causes being formed on around the interface disappears.Only just in depth relate to the process that forms interface state, and can be during this period about first minute of crystal growing process in the starting stage of the crystal growing process of high resistivity semiconductor layer A.
More preferably, the crystal growth rate of high resistivity semiconductor layer A is 65nm/ minute or higher (aspect the present invention the 25) at the commitment of crystal growing process at least.That is at the commitment of the crystal growing process of high resistivity semiconductor layer A, crystal growth high resistivity semiconductor layer A can obtain above-mentioned effect and effect more definitely under this quite high growth rate by at least.
The 26 aspect according to the present invention, high resistivity semiconductor layer A can comprise unadulterated GaN.Unadulterated GaN semiconductor layer is as the base substrate or the basic unit of semiconductor device are very useful arbitrarily.For example, shown in following examples of the present invention, unadulterated GaN semiconductor layer can be used as the resilient coating of field-effect transistor.Therefore, the 26 aspect according to the present invention can be manufactured on the high resistivity semiconductor layer that the obvious useful GaN of industrial circle makes.
The crystal growth condition of 13 aspects, the 27 aspect to the can be used for any aluminium ratio of components x of high resistivity semiconductor layer A according to the present invention, and especially they are set to GaN crystal optimization (x=0).
For example, the crystal growth rate of high resistivity semiconductor layer A is preferably 100nm/ minute or lower (the present invention the 27 aspect).Thus, can improve the degree of crystallinity of high resistivity semiconductor layer A, keep the excellent insulating properties of high resistivity semiconductor layer A simultaneously.In addition, the upside on high resistivity semiconductor layer A surface can keep outstanding smooth and level and smooth.
Therefore, when utilizing this high resistivity semiconductor layer A to form the resilient coating of field-effect transistor, the charge carrier that transmits in passage is difficult to diffusion.This can make the device with high carrier mobility.
The crystal growth rate of preferred high resistivity semiconductor layer A can be 70nm/ minute-90nm/ minute (the present invention's the 20 eight aspect).
The crystal growth temperature of preferred high resistivity semiconductor layer A can be 1130 ℃-1150 ℃ (the present invention the 29 aspects).
In order in fact and more easily to realize crystal growth condition of the present invention, the V/III ratio of crystalline material gas can be 1400-1550 (the present invention the 30 aspect).
According to these crystal growth conditions, can form the excellent flatness with interface upside and the desirable unadulterated high resistivity layer of excellent degree of crystallinity more definitely.That is these crystal growth conditions become the extremely important condition of the solution that two different problems are provided: that is exactly to keep interface or semiconductor layer surface smooth; With the breakdown field intensity that keeps semiconductor device.
The unadulterated high resistivity layer of these conditions is satisfied in utilization, can form the resilient coating with excellent quality in field-effect transistor, and this causes improving the operating characteristic and the breakdown field intensity of device.
When the crystal growth temperature of nucleating layer or lattice constant difference relaxation layer is lower than 800 ℃, provide the cuclear density of semiconductor layer (nucleating layer) of crystal growth face and the shape of each nuclear to be optimised for high resistivity semiconductor layer A, can improve the required ELO growth or the length of looking unfamiliar of the high resistivity semiconductor layer A around the interface between semiconductor and high resistivity semiconductor layer A.As a result, the degree of crystallinity of high resistivity semiconductor layer A and insulating properties all can well be kept.This is useful for the device that comprises Sapphire Substrate, and is also useful to the device that comprises other substrate.
Preferably, the growth temperature of semiconductor (nucleating layer) can be 600 ℃ or lower, more preferably 400 ℃ or lower.Can may be because the shape of the cuclear density of nucleating layer and each nuclear is optimised under this condition in the reason that obtains required result under this growth temperature range.
Effect below with reference to growth of document 1 involvement aspect or ELO growth.
(list of references 1) Amano and Akasaki, " Group III nitridecompound on sapphire substrate " Applied physics, Vol.68, No.7 (1999), p.700-772.
The III group-III nitride compound semiconductor layer of making by either side in said method or the present invention the 24 to 30 aspect (being high resistivity semiconductor layer A) has 1 * 10 8Ω cm or higher remarkable high resistivity, so these semiconductors are industrial circle very useful (the present invention the 30 is on the one hand).
The 32 aspect according to the present invention can form the excellent flatness with interface upside and the desirable unadulterated high resistivity layer of excellent degree of crystallinity in field-effect transistor.What as a result, the breakdown field intensity with target field effect transistor of high-performance and high mobility can keep than in the existing device is bigger.
The 33 aspect according to the present invention can form the excellent flatness with face upside and the desirable unadulterated high resistivity layer of excellent degree of crystallinity.As a result, not only can in the aimed semiconductor device, keep the crystal mass of high resistivity layer at least, and the breakdown field intensity of aimed semiconductor device can to keep than in the existing device bigger.
Description of drawings
Fig. 1 is the sectional view according to the field-effect transistor 100 of first embodiment of the invention.
Fig. 2 is the figure that supplies carrier gas in the first embodiment.
Fig. 3 has thickness d when layer 1042 2The time each surperficial micrograph.
Fig. 4 A is the thickness d that layer 1042 is shown 2And the figure that concerns between its surface roughness.
Fig. 4 B is the thickness d that layer 1042 is shown 2And the figure that concerns between the sheet resistivity.
Fig. 5 is the sectional view according to the field-effect transistor 200 of second embodiment of the invention.
Fig. 6 has thickness d when layer 2042 2The time each surperficial micrograph.
Fig. 7 A is the thickness d that layer 2042 is shown 2And the figure that concerns between its surface roughness.
Fig. 7 B is the thickness d that layer 2042 is shown 2And the figure that concerns between the sheet resistivity.
Fig. 8 is the figure of supply carrier gas in improved embodiment 1.
Fig. 9 is the figure of supply carrier gas in improved embodiment 2.
Figure 10 is according to the sectional view of the field-effect transistor 100 of third embodiment of the invention.
Figure 11 is illustrated in the table of the crystal growth condition of semiconductor layer A and B in the field-effect transistor 100.
Figure 12 is the sectional view of existing field-effect transistor 10.
Figure 13 is the sectional view that comprises according to the sample 10 of the high resistivity semiconductor layer 13 that do not mix of four embodiment of the invention.
Figure 14 illustrates the figure that concerns between the crystal growth temperature of high resistivity semiconductor layer 13 and the leakage current.
Figure 15 illustrates the figure that concerns between the crystal growth temperature of high resistivity semiconductor layer 13 and the FWHM.
Figure 16 is the sectional view that comprises according to the sample 20 of the high resistivity semiconductor layer 23 that do not mix of fifth embodiment of the invention.
Figure 17 A illustrates the figure that concerns between the crystal growth rate of high resistivity semiconductor layer 23 and the leakage current.
Figure 17 B illustrates the table that concerns between the crystal growth rate of high resistivity semiconductor layer 23 and the leakage current.
Figure 18 is the sectional view according to the field-effect transistor 600 of sixth embodiment of the invention.
Figure 19 is the sectional view according to the field-effect transistor 700 of seventh embodiment of the invention.
Embodiment
1. first to the tenth aspect of the present invention is described.
Can use rare gas (He, Ne, Ar, Ke, Xe, Rn), nitrogen (N 2) or the mixture of these gases as the inert gas on crystal growth barrier layer.These admixture of gas as inert gas can have any mixing ratio.When using hydrogen (H 2), nitrogen (N 2) or rare gas during as main carrier gas (being the main component of carrier gas), even a small amount of or some other gases sneak in the carrier gas, as long as any undesirable atom or element be not retained in or sneak into will the semiconductor crystal of crystal growth in.
When the material that is used for the crystal growth substrate is included in field-effect transistor of the present invention, consider thermal stability and thermal radiation, carborundum (SiC) may be most preferred.When other considers manufacturing cost, also can use sapphire or silicon (Si).Though, considering thermal stability and thermal radiation, GaN is so not preferred, is to use GaN can not stop the invention process especially.
Ohmic electrode and Schottky electrode can form by known any means.For example, as mentioned above, Ohmic electrode can be formed in the superiors on barrier layer by thin dielectric membrane.
Below with reference to specific embodiments explanation the present invention.
Yet the present invention is not limited to following embodiment.
Embodiment 1
Fig. 1 is the sectional view according to the field-effect transistor 100 of first embodiment of the invention.Field-effect transistor 100 is the semiconductor device that form by crystal growth sequential aggradation III group-III nitride compound semiconductor layer, and crystal growth substrate 101 is made by the sapphire of thick about 300 μ m.On crystal growth substrate 101, form the thick AlN layer 102 of about 40nm that AlN makes.AlN layer 102 relaxes crystal growth substrates 101 and is formed on lattice constant mismatch between the semiconductor layer 103 on the AlN layer 102.
On AlN layer 102, form the thick not Doped GaN semiconductor layer 103 of about 2 μ m.The so-called hereinafter resilient coating of semiconductor layer 103 and AlN layer 102.Resilient coating (comprising AlN layer 102 and semiconductor layer 103) is the semiconductor layer that is called resilient coating in claims.
In addition, on semiconductor layer 103, form the thick not doped with Al of about 40nm 0.2Ga 0.8N semiconductor layer 104.Determine the thickness (about 40nm) of semiconductor layer 104, make charge carrier (electronics) from Ohmic electrode (105 and 107) enter be formed between barrier layer and the resilient coating or layer 1041 and layer 103 between the interface on the tunnel effect of passage become and determine and preferred.
Semiconductor layer 104 comprises two-layer, or thick abrupt interface accommodating layer 1041 and the thick electrode joint face accommodating layer 1042 of about 10nm of about altogether 30nm.This each two-layer layer is all by Al 0.2Ga 0.8The N semiconductor is made.Abrupt interface accommodating layer 1041 utilizes H 2Form by crystal growth as carrier gas, electrode joint face accommodating layer 1042 utilizes N 2Form by crystal growth as carrier gas.
105,106 and 107 represent source electrode (Ohmic electrode), gate electrode (Schottky electrode) and drain electrode (Ohmic electrode) respectively.Each Ohmic electrode (source electrode 105 and drain electrode 107) deposits thin metal layer that the titanium (Ti) of about 100  thickness makes and further deposits the metal level that the aluminium (Al) of about 3000  thickness makes by vapour deposition process by vapour deposition process and forms.These Ohmic electrodes adhere to and the alloying by the short annealing heat treatment that was less than for 1 second under 700 ℃ of-900 ℃ of temperature admirably mutually.Gate electrode 106 is Schottky electrodes, and it deposits metal level that the nickel (Ni) of about 100  thickness makes and further deposit the metal level that the gold (Au) of about 3000  thickness makes by vapour deposition process by vapour deposition process and forms.
A kind of method of making field-effect transistor 100 below is described, with reference to key property of the present invention (semiconductor layer 1041 and 1042).
Each semiconductor layer in the field-effect transistor 100 (semiconductor layer 102,103 and 104) is called gas phase epitaxy of metal organic compound (hereafter is MOVPE) again and forms by the vapour deposition crystal growth.Use following gas: carrier gas (H 2Or N 2), ammonia (NH 3), trimethyl gallium (Ga (CH 3) 3) and trimethyl aluminium (Al (CH 3) 3).
In the present invention, use the method for gas phase epitaxy of metal organic compound (MOVPE) as the crystal growth semiconductor layer.As for other growing method, molecular beam epitaxy (MBE) and halide vapor phase growth (HVPE) usefully.
Fig. 2 illustrates the carrier gas supply when forming barrier layer 104 (being abrupt interface accommodating layer 1041 and electrode joint face accommodating layer 1042) in the first embodiment.Y axis Y among Fig. 2 illustrates hydrogen (H 2) voltage ratio R in carrier gas, axis of abscissas illustrates the crystal growth time.Time t=0 represents the crystal growth time started of abrupt interface accommodating layer 1041, time t=t 1The crystal growth concluding time of expression electrode joint face accommodating layer 1042.In addition, according to following crystal growth condition deposited barrier layer.
(crystal growth condition on barrier layer 104)
(1) the abrupt interface accommodating layer 1041
(a) carrier gas: H 2(R ≈ 1)
(b) crystal growth temperature: 1000 ℃
(c) crystal growth pressure: 1013hPa (total pressure in the crystal growing furnace)
(2) electrode joint face accommodating layer 1042
(a) carrier gas: N 2(R ≈ 0)
(b) crystal growth temperature: 1000 ℃
(c) crystal growth pressure: 1013hPa (total pressure in the crystal growing furnace)
Fig. 3 illustrates the gross thickness (d on barrier layer 104 1+ d 2) when being fixed as 400 , utilize the thickness d of electrode joint face accommodating layer 1042 2As parameter, use 5 kinds of micrograph (d of electrode joint face accommodating layer 1042 surface images (configuration of surface) of atomic force microscope shooting 2=0 -400 ).
Fig. 4 A illustrates the thickness d of electrode joint face accommodating layer 1042 2And the relation between each surperficial roughness.The longitudinal axis is represented the standardization root mean square of the roughness wave pattern on specific direction top electrode joint face accommodating layer 1042 surfaces, adopts and works as d 2=0  (being normalization surface roughness=1) or the value when whole barrier layer 104 is only formed by the abrupt interface accommodating layer 1041 of about 400  of thickness are as standard value.
Fig. 4 B be illustrated in the sheet resistivity standardized value that forms the field-effect transistor 100 before the gate electrode 106 identical with employing with Fig. 4 A work as d 2The value of=0  (being standardized sheet resistivity value=1) is the thickness d of standard value 2Between the figure of relation.
According to these figure, when the gross thickness on barrier layer 104 is 400 , the thickness d of electrode joint face accommodating layer 1042 2Be preferably about 100 -300 , more preferably from about 150 -200 .
By forming barrier layer 104 according to above-mentioned condition, the field-effect transistor 100 of first embodiment of the invention can keep excellent electrical characteristics for example sheet resistivity and excellent surface, compared with prior art can make electrode more effectively microminiaturized.
And, can obtain 200W or higher output characteristic at 2GHz frequency band place.
Embodiment 2
Fig. 5 is the sectional view according to the field-effect transistor 200 of second embodiment of the invention.Field-effect transistor 200 is the semiconductor device that form by crystal growth sequential aggradation III group-III nitride compound semiconductor layer.Crystal growth substrate 201 is made by the carborundum (SiC) of thick about 400 μ m.On crystal growth substrate 201, form the thick AlN layer 202 of about 0.2 μ m.AlN layer 202 is eliminated or is relaxed crystal growth substrate 201 and be formed on lattice constant mismatch between the semiconductor layer 203 on the AlN layer 202.
On AlN layer 202, form the thick not Doped GaN semiconductor layer 203 of about 2 μ m.The so-called hereinafter resilient coating of semiconductor layer 203 and AlN layer 202.Resilient coating (comprising layer 202 and layer 203) is the semiconductor layer that is called resilient coating in claims.
In addition, on semiconductor layer 203, form the thick not doped with Al of about 40nm 0.25Ga 0.75N semiconductor layer 204.Determine the thickness (about 40nm) of semiconductor layer 204, make charge carrier (electronics) from Ohmic electrode (205 and 207) enter be formed between barrier layer and the resilient coating or layer 2041 and layer 203 between the interface on the tunnel effect of passage become and determine and preferred.
Semiconductor layer 204 comprises two-layer, or thick abrupt interface accommodating layer 2041 and the thick electrode joint face accommodating layer 2042 of about 30nm of about altogether 10nm.This each two-layer layer is all by Al 0.25Ga 0.75The N semiconductor is made.Abrupt interface accommodating layer 2041 utilizes H 2Form by crystal growth as carrier gas, electrode joint face accommodating layer 2042 utilizes N 2Form by crystal growth as carrier gas.
205,206 and 207 represent source electrode (Ohmic electrode), gate electrode (Schottky electrode) and drain electrode (Ohmic electrode) respectively.Each Ohmic electrode (source electrode 205 and drain electrode 207) deposits thin metal layer that the titanium (Ti) of about 100  thickness makes and further deposits the metal level that the aluminium (Al) of about 3000  thickness makes by vapour deposition process by vapour deposition process and forms.These Ohmic electrodes adhere to and the alloying by the short annealing heat treatment that was less than for 1 second under 700 ℃ of-900 ℃ of temperature admirably mutually.Gate electrode 206 is Schottky electrodes, and it deposits metal level that the nickel (Ni) of about 100  thickness makes and further deposit the metal level that the gold (Au) of about 3000  thickness makes by vapour deposition process by vapour deposition process and forms.
A kind of method of making field-effect transistor 200 below is described, with reference to key property of the present invention (semiconductor layer 2041 and 2042).
Each semiconductor layer in the field-effect transistor 200 (semiconductor layer 202,203 and 204) is called gas phase epitaxy of metal organic compound (hereafter is MOVPE) again and forms by the vapour deposition crystal growth.Use following gas: carrier gas (H 2Or N 2), ammonia (NH 3), trimethyl gallium (Ga (CH 3) 3) and trimethyl aluminium (Al (CH 3) 3).
In the present invention, use the method for gas phase epitaxy of metal organic compound (MOVPE) as the crystal growth semiconductor layer.As for other growing method, molecular beam epitaxy (MBE) and halide vapor phase growth (HVPE) usefully.
Fig. 2 illustrates the carrier gas supply when forming barrier layer 204 (being abrupt interface accommodating layer 2041 and electrode joint face accommodating layer 2042) in the first embodiment.Y axis Y among Fig. 2 illustrates hydrogen (H 2) voltage ratio R in carrier gas, axis of abscissas illustrates the crystal growth time.Time t=0 represents the crystal growth time started of abrupt interface accommodating layer 2041, time t=t 1The crystal growth concluding time of expression electrode joint face accommodating layer 2042.
In addition, according to following crystal growth condition deposited barrier layer.
(crystal growth condition on barrier layer 204)
(1) the abrupt interface accommodating layer 2041
(a) carrier gas: H 2(R ≈ 1)
(b) crystal growth temperature: 1000 ℃
(c) crystal growth pressure: 1013hPa (total pressure in the crystal growing furnace)
(2) electrode joint face accommodating layer 2042
(a) carrier gas: N 2(R ≈ 0)
(b) crystal growth temperature: 1000 ℃
(c) crystal growth pressure: 1013hPa (total pressure in the crystal growing furnace)
Fig. 6 illustrates the gross thickness (d when barrier layer 204 1+ d 2) when being fixed as 40nm, utilize the thickness d of electrode joint face accommodating layer 2042 2() as parameter, use 2 kinds of micrographs (d2=0nm and 30nm) of electrode joint face accommodating layer 2042 surface images (configuration of surface) of atomic force microscope shooting.
Fig. 7 A illustrates the thickness d of electrode joint face accommodating layer 2042 2And the relation between each surperficial roughness.The longitudinal axis is represented the standardization root mean square of the roughness wave pattern on specific direction top electrode joint face accommodating layer 2042 surfaces, adopts and works as d 2=0  (being normalization surface roughness=1) or the value when whole barrier layer 204 is only formed by the abrupt interface accommodating layer 2041 of the about 40nm of thickness are as standard value.
Fig. 7 B be illustrated in the standardization sheet resistivity value that forms the field-effect transistor 200 before the gate electrode 206 identical with employing with Fig. 4 A work as d 2The value of=0  (being standardized sheet resistivity value=1) is the thickness d of standard value 2Between the figure of relation.
As shown in these figures, the barrier layer can comprise double-decker, comprises abrupt interface accommodating layer 2041 and electrode joint face accommodating layer 2042, so that target electrical characteristics and height and desirable electrode microminiaturization are provided.
By forming barrier layer 204 according to above-mentioned condition, the field-effect transistor 200 of second embodiment of the invention can keep excellent electrical characteristics for example sheet resistivity and excellent surface, compared with prior art can make electrode more effectively microminiaturized.
Other improves embodiment
Though the present invention illustrates the present invention with reference to above embodiment as most realistic and optimum embodiment, the invention is not restricted to this, can suitably improve and do not deviate from spirit of the present invention.
Improve embodiment 1
For example, in the first embodiment, as shown in Figure 2, the voltage ratio R of hydrogen in carrier gas drops to about 0 from about 1 at once.As selection, the voltage ratio R of hydrogen in carrier gas can all even continuous decline, as shown in Figure 8.At this moment, barrier layer 104 cannot have the wherein double-decker of abrupt interface accommodating layer 1041 and the 1042 mutual clear differentiations of electrode joint face accommodating layer, but field-effect transistor has the performance that almost is equal to above-mentioned field-effect transistor 100.
Improve embodiment 2
As selection, the voltage ratio R of hydrogen in carrier gas can progressively reduce with dullness.Further alternatively, the decline process of voltage ratio R can be smoothly and continuously to descend and combination unexpected and that progressively descend.Embodiment as described in Figure 9 can comprise this combination of the process that respectively descends.
By adopting these conditions arbitrarily, can obtain effect of the present invention and effect according to the inventive method.
2. the explanation of the 11 to 23 aspect
When the material that is used for the crystal growth substrate is included in field-effect transistor of the present invention, consider thermal stability and thermal radiation, carborundum (SiC) may be most preferred.As selection, also can use sapphire, silicon (Si) or GaN to form substrate.
Ohmic electrode and Schottky electrode can form by known any means.
Below with reference to specific embodiments explanation the present invention.
Yet the present invention is not limited to following embodiment.
Embodiment 3
Figure 10 is the sectional view of the field-effect transistor 300 of the 3rd embodiment.Field-effect transistor 300 is the semiconductor device that form by crystal growth sequential aggradation III group-III nitride compound semiconductor layer, and crystal growth substrate 301 is made by the carborundum (SiC) of thick about 500 μ m.On crystal growth substrate 301, form the thick AlN layer 302 of about 0.3 μ m that AlN makes.
On AlN layer 302, form the thick not Doped GaN semiconductor layer 303 of about 2 μ m.Semiconductor layer 303 is corresponding to the first semiconductor layer A in the first embodiment of the invention.On semiconductor layer 303 (the first semiconductor layer A), form the thick not doped with Al of about 35nm 0.25Ga 0.75The semiconductor layer 304 of N, it is corresponding to the second semiconductor layer B in the first embodiment of the invention.Determine the thickness of semiconductor layer 304 (the second semiconductor layer B), make that when grid is in on-state the tunnel effect that enters the charge carrier (electronics) of the passage that the interface between semiconductor layer A and B forms from Ohmic electrode (305 and 307) becomes and determines and preferably.
305,306 and 307 represent source electrode (Ohmic electrode), gate electrode (Schottky electrode) and drain electrode (Ohmic electrode) respectively.Each Ohmic electrode (source electrode 305 and drain electrode 307) deposits thin metal layer that the titanium (Ti) of about 100  thickness makes and further deposits the metal level that the aluminium (Al) of about 3000  thickness makes by vapour deposition process by vapour deposition process and forms.These Ohmic electrodes adhere to and the alloying by the short annealing heat treatment that was less than for 1 second under 700 ℃ of-900 ℃ of temperature admirably mutually.Gate electrode 306 is Schottky electrodes, and it deposits metal level that the nickel (Ni) of about 100  thickness makes and further deposit the metal level that the gold (Au) of about 3000  thickness makes by vapour deposition process by vapour deposition process and forms.
A kind of method of making field-effect transistor 300 below is described, with reference to key property of the present invention (semiconductor layer 303 and 304).
Each semiconductor layer in the field-effect transistor 300 (semiconductor layer 302,303 and 304) is called gas phase epitaxy of metal organic compound (hereafter is MOVPE) again and forms by the vapour deposition crystal growth.Use following gas: carrier gas (H 2Or N 2), ammonia (NH 3), trimethyl gallium (Ga (CH 3) 3) and trimethyl aluminium (Al (CH 3) 3).
In the present invention, use the method for gas phase epitaxy of metal organic compound (MOVPE) as the crystal growth semiconductor layer.As for other growing method, molecular beam epitaxy (MBE) and halide vapor phase growth (HVPE) usefully.
Figure 11 illustrates the semiconductor layer A of field-effect transistor 300 in the 3rd embodiment and the crystal growth condition of b.As shown in figure 11, about 2 μ m of thickness and the crystal growth that is included in the semiconductor layer 303 (or first semiconductor layer A among the present invention) in the field-effect transistor 300 are carried out according to following crystal growth condition.
(crystal growth condition of semiconductor layer A)
(1) crystal growth temperature T A: 1100 ℃
(2) crystal growth pressure P A: 1013hPa
Then, the about 0.35 μ m of thickness and by doped with Al not 0.25Ga 0.75The crystal growth of the semiconductor layer 304 that the N crystal is made (or second semiconductor layer B) is carried out according to following crystal growth condition.
(crystal growth condition of semiconductor layer B)
(1) crystal growth temperature T B: 1000 ℃
(2) crystal growth pressure P B: 1013hPa
The maximum of the 3rd embodiment is characterised in that each crystal growth temperature T of the first and second semiconductor layer A and B (semiconductor layer 303 sneaks into 304) AAnd T BAnd each crystal growth pressure P AAnd P BSatisfy following formula (2) respectively.Crystal growth condition in the manufacture process of the existing transistor 10 of following formula (1) representative.
(crystal growth condition in the existing invention)
T B＞T A，
P B＜P A ...(1)
(crystal growth condition in the 3rd embodiment)
1000℃＝T B＜T A＝1100℃
P B=P A=(normal pressure) ... (2)
By adopting this crystal growth condition, be deposited into after thickness is 2 μ m at semiconductor layer 303 (the first semiconductor layer A), the crystal growth temperature in the crystal growing furnace descends, and crystal growth pressure remains on almost under the normal pressure.As a result, can effectively suppress to form the atom distillation of semiconductor layer 303 (the first semiconductor layer A) upper surface.Therefore, by adopting above-mentioned crystal growth condition, can effectively prevent rough interface between semiconductor layer 303 and 304.
As a result, as shown in figure 11, in field-effect transistor 300 of the present invention, on-state current I can be increased to 1.0A/mm from 0.7A/mm, and sheet resistivity ρ can drop to 450 Ω/ from 650 Ω/, and the passage mobility [mu] can be from 1000cm 2/ Vsec is increased to 1500cm 2/ Vsec.
These electrical characteristics have very high performance, make that the sheet concentration of channel layer (two-dimensional electron gas) is about 1 * 10 13Cm -2In brief, the structure and the manufacture method thereof of the field-effect transistor 300 by adopting third embodiment of the invention with respect to prior art, can significantly improve the electrical characteristics of device.
Other improves embodiment
Though the present invention illustrates the present invention with reference to above embodiment as most realistic and optimum embodiment, the invention is not restricted to this, can suitably improve and do not deviate from spirit of the present invention.
Improve embodiment 1
For example, in the first embodiment, the interface between semiconductor layer A (semiconductor layer 303) and the semiconductor layer B (semiconductor layer 304) almost is the plane.The interface can be preferably smooth on micro-scale as far as possible, but can not must be that micro-scale is smooth.For example, the interface between these two semiconductor layers can be a curved surface, and its part is the sizable roughly sphere of radius of curvature.Be further used as selection, the interface between these two semiconductor layers can be rugged and non-planar surface, and it has spacing between suitable inclination, suitable each wall and suitable repetition rate.These conditions are conditions of each field-effect transistor of formation of any design, can utilize arbitrary interface according to the present invention to prevent semiconductor layer A rough surface.Smoothing effect can provide effect of the present invention and effect.
3. the explanation of the 24 to the 33 aspect
In the present invention, use the method for gas phase epitaxy of metal organic compound (MOVPE) as the crystal growth semiconductor layer.As for other growing method, molecular beam epitaxy (MBE) and halide vapor phase growth (HVPE) usefully.
As for the carrier gas of the crystalline material gas of carrying semiconductor layer in crystal growing process, not only can use H 2Gas also can use inert gas.Rare gas (Hc, Ne, Ar, Ke, Xe, Rn), nitrogen (N 2) or the mixture of these gases can be used as the inert gas of crystal growth semiconductor layer.These admixture of gas as inert gas can have any mixing ratio.When using hydrogen (H 2), nitrogen (N 2) or rare gas during as main carrier gas (being the main component of carrier gas), even a small amount of or some other gases sneak in the carrier gas, as long as any undesirable atom or element be not retained in or sneak into will the semiconductor crystal of crystal growth in.
When the material owing to the crystal growth substrate is included in the field-effect transistor of the present invention, consider thermal stability and thermal radiation, carborundum (SiC) may be most preferred.When other considers manufacturing cost, also can use sapphire or silicon (Si).Though, considering thermal stability and thermal radiation, GaN is so not preferred, is to use GaN can not stop the invention process especially.
Ohmic electrode and Schottky electrode can form by known any means.For example, as mentioned above, Ohmic electrode can be formed in the superiors on barrier layer by thin dielectric membrane.
According to the type and the function of device, the barrier layer in the field-effect transistor of the present invention can comprise the semiconductor layer of doped semiconductor not or impurity.Be further used as selection, the barrier layer can comprise a plurality of semiconductor layers that have different compositions separately.These conditions can be applicable to the barrier layer in the field-effect transistor of the present invention.At this, for high mobility is provided, the semiconductor layer that will the form passage impurity that can undope is to prevent the charge carrier diffusion.Therefore, the semiconductor layer the superiors that are included at least in the resilient coating can be preferably formed with unadulterated semiconductor layer.
Below with reference to specific embodiments explanation the present invention.
Yet the present invention is not limited to following embodiment.
The 4th embodiment
Figure 13 is the sectional view of sample 400, and sample 400 comprises the high resistivity semiconductor layer 413 and handle by the MOVPE in the four embodiment of the invention and to make of not mixing.Substrate 411 is made by carborundum (4H-SiC) and is had the thick AlN nucleating layer 412 of about 200nm thereon, and nucleating layer 412 is grown under 1140 ℃ high crystal growth temperature.On high growth temperature nucleating layer 412, under following crystal growth condition, form the high resistivity semiconductor layer 413 of making and having about 2 μ m thickness by Doped GaN not.
(crystal growth condition of high resistivity semiconductor layer 413)
Carrier gas: hydrogen (H 2)
Total pressure in the growth furnace: 1013hPa
Crystal growth rate: 80nm/ minute
V/III ratio: 1473
Crystal growth temperature: (a) 1120 ℃, (b) 1130 ℃, (c) 1140 ℃, (d) 1150 ℃
(to the evaluation of breakdown field intensity)
According to above-mentioned each crystal growth condition, deposit unadulterated high resistivity semiconductor layer 413, and under each crystal growth temperature (a)-(d), make 4 kinds of samples 400 as shown in figure 13 altogether.On the upper surface of each high resistivity semiconductor layer 413, form the electrode of the thick about 15nm that makes by vanadium (V) around the both sides, measure the leakage current of each high resistivity semiconductor layer 413.
Figure 14 is the figure of the relation between the crystal growth temperature ((a)-(d)) of exhibiting high resistivity semiconductor layer 413 and the leakage current when applying 200V voltage.According to this figure, when the high resistivity semiconductor layer when Doped GaN is not made, crystal growth temperature need be 1120 ℃ or higher, makes that the leakage current when applying 200V voltage is 1 * 10 -4A or lower.In order to control leakage current is 1 * 10 -6A or lower, crystal growth ℃ is preferably 1130 ℃ or higher.
The high resistivity semiconductor layer of being made under 1140 ℃ crystal growth temperature by Doped GaN not 413 has 1 * 10 8The significant high resistivity of Ω cm.
(to the evaluation of degree of crystallinity)
Simultaneously, measure the FEHM (being halfwidth) of high resistivity semiconductor layer in each sample ((a)-(d)).Figure 15 illustrates the relation of crystal growth temperature and its FWMH of each high resistivity semiconductor layer 413.FWMH is more little, and then degree of crystallinity is good more.And as FWMH during greater than 300 second of arcs, the degree of crystallinity of high resistivity semiconductor layer 413 progressively descends, and as FWMH during greater than 400 second of arcs, the rapid deterioration of the surface flatness of high resistivity semiconductor layer 413 is until the device property same deterioration of carrier mobility for example.
Therefore, in order to make the field-effect transistor that has high-performance and comprise unadulterated GaN high resistivity semiconductor layer 413, crystal growth temperature should be 1160 ℃ or lower.These trend for degree of crystallinity can be utilized the light microscope visual identification.
According to above-mentioned experimental result, the crystal growth temperature of high resistivity semiconductor layer 413 can be preferably 1120 ℃-1160 ℃, and more preferably 1130 ℃-1150 ℃, thus obtain having high performance field-effect transistor at least.
The 5th embodiment
Figure 16 is the sectional view of sample 500, and sample 500 comprises the high resistivity semiconductor layer 523 and handle by the MOVPE in the fifth embodiment of the invention and to make of not mixing.
Substrate 521 is made by sapphire, and it has " c " plane as primary flat and form the thick AlN nucleating layer 522 of about 40nm thereon, and nucleating layer 522 is grown under 400 ℃ low crystal growth temperature.On low growth temperature nucleating layer 522, under following crystal growth condition, form the high resistivity semiconductor layer 523 of making and having about 2 μ m thickness by Doped GaN not.
(crystal growth condition of high resistivity semiconductor layer 523)
Carrier gas: hydrogen (H 2)
Total pressure in the growth furnace: 1013hPa
Crystal growth temperature: 1150 ℃
V/III ratio: 1473
Crystal growth rate: (e) 659 /minute, (f) 827 /minute, (g) 968 /minute
(to the evaluation of breakdown field intensity)
According to above-mentioned each crystal growth condition, deposit unadulterated high resistivity semiconductor layer 523, and under each crystal growth rate (e)-(g), make 3 kinds of samples 500 altogether as shown in figure 16.On the upper surface of each high resistivity semiconductor layer 5233, form the electrode of the thick about 15nm that makes by vanadium (V) around the both sides, measure the leakage current of each high resistivity semiconductor layer 523.
Figure 17 A and 17B are the graphs of a relation between the crystal growth rate ((e)-(g)) of exhibiting high resistivity semiconductor layer 4523 and the leakage current when applying 40V voltage.According to this figure, when the high resistivity semiconductor layer when Doped GaN is not made, crystal growth rate need be 65nm/ minute or higher, makes that the leakage current when applying 40V voltage is 1 * 10 -8A or lower.
By Doped GaN not 968 /minute crystal growth rate under the high resistivity semiconductor layer 523 made have 1 * 10 8The high resistivity of Ω cm.
(to the evaluation of degree of crystallinity)
Simultaneously, when crystal growth rate for about 90nm/ minute or when higher, the degree of crystallinity of high resistivity semiconductor layer 523 progressively descends.When crystal growth rate for about 100nm/ minute or when higher, the rapid deterioration of the surface flatness of high resistivity semiconductor layer 523 is until the device property same deterioration of carrier mobility for example.Therefore, in order to make the field-effect transistor that has high-performance and comprise unadulterated GaN high resistivity semiconductor layer 523, crystal growth rate should be 100nm/ minute or lower.These trend for degree of crystallinity can be utilized the light microscope visual identification.
According to above-mentioned experimental result, the crystal growth rate of high resistivity semiconductor layer 523 can be preferably 65nm/ minute-100nm/ minute, and more preferably 70nm/ minute-90nm/ minute, thus obtain having high performance field-effect transistor at least.
(the 6th embodiment)
Figure 18 is the sectional view of the field-effect transistor 600 of the 6th embodiment.Field-effect transistor 600 is the semiconductor device that form by crystal growth sequential aggradation III group-III nitride compound semiconductor layer, and crystal growth substrate 601 is made by the carborundum (4H-SiC) of thick about 500 μ m.On crystal growth substrate 601, form the thick AlN layer 602 of about 200nm that AlN makes.
On AlN layer 602, form the thick not Doped GaN semiconductor layer 603 of about 2 μ m.Semiconductor layer 603 is corresponding to the semiconductor layer A among the present invention.And, on semiconductor layer 603, form the thick not doped with Al of about 40nm 0.25Ga 0.75N barrier layer 604.Determine the thickness on barrier layer 604, make the tunnel effect that enters the charge carrier (electronics) of the passage that the interface between semiconductor layer 603 upper surfaces and layer 604 forms from Ohmic electrode (605 and 607) become to determine and preferred.
605,606 and 607 represent source electrode (Ohmic electrode), gate electrode (Schottky electrode) and drain electrode (Ohmic electrode) respectively.Each Ohmic electrode (source electrode 605 and drain electrode 607) deposits thin metal layer that the titanium (Ti) of about 100  thickness makes and further deposits the metal level that the aluminium (Al) of about 3000  thickness makes by vapour deposition process by vapour deposition process and forms.These Ohmic electrodes adhere to and the alloying by the short annealing heat treatment that was less than for 1 second under 700 ℃ of-900 ℃ of temperature admirably mutually.Gate electrode 606 is Schottky electrodes, and it deposits metal level that the nickel (Ni) of about 100  thickness makes and further deposit the metal level that the gold (Au) of about 3000  thickness makes by vapour deposition process by vapour deposition process and forms.
A kind of method of making field-effect transistor 600 below is described, with reference to key property of the present invention (semiconductor layer 603: high resistivity semiconductor layer A).
Each semiconductor layer in the field-effect transistor 600 (semiconductor layer 602,603 and 604) is called gas phase epitaxy of metal organic compound (hereafter is MOVPE) again and forms by the vapour deposition crystal growth.Use following gas: carrier gas (H 2Or N 2), ammonia (NH 3), trimethyl gallium (Ga (CH 3) 3) and trimethyl aluminium (Al (CH 3) 3).
In vapor-phase growth processes, at first toast crystal growth substrate 601 down at 1140 ℃, and by on crystal growth substrate 601, form the thick AlN nucleating layer 602 of 200nm (being lattice constant difference relaxation layer) 1140 ℃ of following crystal growths.
Then, according to following crystal growth condition, form the semiconductor layer 603 of the about 2 μ m of thickness that make by Doped GaN crystal not.
(crystal growth condition of semiconductor layer 604)
(1) crystal growth temperature: 1140 ℃
(2) crystal growth rate: 80nm/ minute
Then, the not doped with Al of the about 40nm of deposit thickness thereon 0.25Ga 0.75N crystalline semiconductor layer (resilient coating) 604.The crystal growth temperature of this crystal growth is about 1000 ℃.
Field-effect transistor shown in Figure 180 600 by above-mentioned growing method manufacturing can be target field effect transistor (HFET), and it has high mobility, high electrical characteristics and low-leakage current.This field-effect transistor is not only very useful for improving device performance and reliability, and very useful to compare microminiaturization and the integrated level of improving device with existing device.
(the 7th embodiment)
Figure 19 is the sectional view according to the field-effect transistor 700 (MISFET) of seventh embodiment of the invention.Maximum not being both forms the dielectric film of being made by silicon nitride (SiN) 708 between field-effect transistor 700 and the above-mentioned field-effect transistor 600 between gate electrode 706 and barrier layer 704.Other each layer (701-707) forms identically with other each layer (601-607) in the above-mentioned field-effect transistor 600 in the field-effect transistor 700.
By adopting this structure, MISFET can obtain effect of the present invention and the effect according to the inventive method of similar and the 6th embodiment.And, the field-effect transistor that can obtain having fabulous breakdown field intensity.
(other improves embodiment)
Though the present invention illustrates the present invention with reference to above embodiment as most realistic and optimum embodiment, the invention is not restricted to this, can suitably improve and do not deviate from spirit of the present invention.
(improving embodiment 1)
For example, in the 6th embodiment, the substrate of field-effect transistor is made by carborundum (SiC).As selection, Sapphire Substrate also can be used as the crystal growth substrate.When the method by adopt forming low crystal growth temperature nucleating layer 522 in the 5th embodiment and high resistivity semiconductor layer 523 and crystal growth condition formed semiconductor layer 602 in the field-effect transistor shown in Figure 180 and semiconductor layer 603, field-effect transistor 600 can obtain effect of the present invention and the effect according to the inventive method.
At this moment, disclosed as the 6th embodiment, can preferably under about 400 ℃ low temperature, form AlN semiconductor layer as thick about 40nm of nucleating layer.Because high resistivity semiconductor layer A (semiconductor layer 603 among Figure 18) be included in the resilient coating, therefore not the Doped GaN crystal layer can be preferably under the crystal growth rate of 1150 ℃ of crystal growth temperatures and 90nm/ minute the thickness of the about 2 μ m of formation.
(improving embodiment 2)
Scheme as an alternative, each barrier layer for example semiconductor layer 604 and semiconductor layer 704 can be made by InAlN and InAlGaN.These barrier layers can be made by general III group-III nitride compound semiconductor, described III group-III nitride compound semiconductor have necessary with resilient coating for example semiconductor layer 603 compare enough big band-gap energy with semiconductor layer 703.
(improved embodiment 3)
Scheme can deposit the n-type semiconductor layer and substitute these barrier layers as an alternative.For example, can deposit the n-type semiconductor layer and substitute semiconductor layer 604 among Figure 18, this can make MESFET.
In brief, even pass through to improve each embodiment and improve embodiment, can make HFET, MISFET and MESFET.
Industrial applicibility
The present invention can be used for preventing that semiconductor surface is coarse. The present invention is used for keeping microminiaturization The possibility of electrode and semiconductor devices and easiness. And the present invention is used in passage The mobility of the carrier of middle transmission, described tunnel-shaped become so that by crystal growth deposition The interface of semiconductor layer on have general planar the surface.
Therefore, the present invention passes through III iii-v nitride compound semiconductor for Design and manufacture The field-effect transistor (comprising various FET and HEMT) that the crystal growth is made is very Useful. The present invention is for making various field-effect transistors microminiaturizations and improving its performance very Useful.
The present invention is useful, described for effective mobility of two-dimensional electron gas of improving in the channel layer Channel layer forms so that have roughly on the interface of the semiconductor layer by crystal growth deposition Smooth surface. Thereby the present invention passes through the III iii-v nitride compound for Design and manufacture The field-effect transistor (comprising various FET and HEMT) that growing semiconductor crystal is made Very useful.
In addition, the present invention can be used for the not doping semiconductor layer (high resistivity half among the present invention Conductor layer A), it has high resistivity and excellent insulating properties, with provide high insulating properties and Be not subjected to the impact of any impurity. Therefore, the present invention not only can be applicable to the field-effect transistor example Such as FET and HMET, and for example semiconductor is sharp can be applied to luminous semiconductor device Other semiconductor device of light device, light-receiving semiconductor device, pressure sensor and any type Part.

Claims (33)

1. field-effect transistor, it comprises resilient coating and barrier layer, and make by III group-III nitride compound semiconductor on each resilient coating and barrier layer, and described field-effect transistor has passage in described resilient coating to the interface internal on described barrier layer,
Wherein said barrier layer has sandwich construction, and it comprises:
The abrupt interface accommodating layer, it constitutes in the described barrier layer the semiconductor layer of below, and its form on the described interface of described resilient coating, change suddenly and
Electrode joint face accommodating layer, it constitutes the semiconductor layer of the top in the described barrier layer, and its upper surface forms smooth.
2. the field-effect transistor of claim 1 wherein is included in each semiconductor layer in the described barrier layer by unadulterated Al xGa 1-xN (0＜x≤1) makes.
3. claim 1 or 2 field-effect transistor wherein are included in each semiconductor layer in the described barrier layer by unadulterated Al xGa 1-xN (0.15≤x≤0.3) makes.
4. claim 2 or 3 field-effect transistor, the aluminium ratio of components x that wherein is included in each semiconductor layer in the described barrier layer are according to sedimentary sequence and basic monotone decreasing.
5. each field-effect transistor among the claim 1-4, wherein said barrier layer comprises:
Be formed on the ground floor on the described barrier layer of below; With
Be deposited on the second layer on the described barrier layer on the described ground floor upper surface on described barrier layer.
6. the field-effect transistor of claim 5, the thickness d of the described ground floor on wherein said barrier layer 1Thickness d with the described second layer on described barrier layer 2Satisfy following formula:
10nm≤d 1≤30nm，
10nm≤d 2≤ 30nm and
30nm≤d 1+d 2≤60nm。
7. each field-effect transistor among the claim 1-6, the superiors of wherein said resilient coating are made by unadulterated GaN.
8. method of making field-effect transistor, described field-effect transistor comprises resilient coating and barrier layer, make by III group-III nitride compound semiconductor on each resilient coating and barrier layer, and described field-effect transistor has passage in described resilient coating to the interface side on described barrier layer, and described method comprises:
The crystal growing process that is used for the described barrier layer of crystal growth,
Hydrogen (the H in the described carrier gas of carrying barrier material gas wherein 2) voltage ratio R is basic reduces continuously or gradually reduce substantially, and by formula r 1〉=R 〉=r 2(1 〉=r 1＞1/4,1/2＞r 2〉=0, r 1＞r 2) in the zone of representative, the basic monotone decreasing of t in time.
9. the method for the manufacturing field-effect transistor of claim 8, wherein said barrier layer comprises m+1 semiconductor layer altogether, each semiconductor layer by in described crystal growing process m time (m 〉=1) progressively reduce gas described voltage ratio R and by unadulterated Al xGa 1-xN (0＜x≤1) makes.
10. the method for the manufacturing field-effect transistor of claim 9, wherein said barrier layer has double-decker, comprises the at first ground floor on the described barrier layer of deposition, and it utilizes hydrogen (H 2) grow by crystal growth and the second layer on the described barrier layer that on the ground floor on described barrier layer, deposits as main carrier gas, it utilizes rare gas or comprises nitrogen (N 2) inert gas grow by crystal growth as main carrier gas.
11. a method of making field-effect transistor, described field-effect transistor comprises a plurality of semiconductor layers, and each semiconductor layer is made by crystal growth by III group-III nitride compound semiconductor, and described method comprises:
First crystal growing process is used to form the first semiconductor layer A, on the upper surface of the described first semiconductor layer A or the channel layer that deposits on every side and distil; With
Second crystal growing process is used to form the second semiconductor layer B that directly is deposited on the described first semiconductor layer A,
The band-gap energy E of the wherein said second semiconductor layer B BBand-gap energy E greater than the described first semiconductor layer A A, and the crystal growth condition of the described second semiconductor layer B is set to limit the crystal growth condition of the atom distillation that forms the described first semiconductor layer A upper surface at least at the commitment of described second crystal growing process.
12. the method for the manufacturing field-effect transistor of claim 11, the crystal growth temperature T of the wherein said second semiconductor layer B BBe lower than the crystal growth temperature T of the described first semiconductor layer A A
13. the method for the manufacturing field-effect transistor of claim 11 or 12, the crystal growth pressure P of the wherein said second semiconductor layer B BApproximate the crystal growth pressure P of the described first semiconductor layer A A
14. the method for each manufacturing field-effect transistor among the claim 11-13, the wherein said first semiconductor layer A is by binary or the unadulterated Al of ternary xGa 1-xN (0≤x＜1) makes, and the described second semiconductor layer B is by the unadulterated Al of ternary yGa 1-yN (x＜y≤1) makes
15. the method for the manufacturing field-effect transistor of claim 14, the crystal growth temperature T of wherein said first semiconductor layer A and the described second semiconductor layer B AAnd T BSatisfy 950 ℃≤T of formula respectively B＜T A, wherein aluminium ratio of components x is about 0, and aluminium ratio of components y is 0.15-0.30, and the crystal growth pressure P of described first semiconductor layer A and the described second semiconductor layer B AAnd P BBe respectively about normal pressure.
16. the method for each manufacturing field-effect transistor among the claim 11-15, the crystal growth temperature T of the wherein said first semiconductor layer A AIt is 1200 ℃ or lower.
17. the method for each manufacturing field-effect transistor among the claim 11-16, the crystal growth temperature T of the wherein said first semiconductor layer A ACrystal growth temperature T than the described second semiconductor layer B BHigh 50 ℃ or still less.
18. the method for each manufacturing field-effect transistor among the claim 15-17, the crystal growth temperature T of the wherein said second semiconductor layer B BSatisfy 950 ℃≤T of formula B＜1050 ℃.
19. the method for the manufacturing field-effect transistor of claim 18, the crystal growth temperature T of the wherein said first semiconductor layer A ASatisfy 1050 ℃＜T of formula A≤ 1150 ℃.
20. a field-effect transistor, it comprises a plurality of semiconductor layers, and each semiconductor layer is made by crystal growth by III group-III nitride compound semiconductor, and described field-effect transistor comprises:
The first semiconductor layer A, thereon on the interface or deposit on every side and distil channel layer and
The second semiconductor layer B, it directly is deposited on the described first semiconductor layer A,
The band-gap energy E of the wherein said second semiconductor layer B BBand-gap energy E greater than the described first semiconductor layer A A, and form the atom distillation of the described first semiconductor layer A upper surface by restriction, make the described first semiconductor layer A upper surface form substantially flat.
21. the field-effect transistor of claim 20, the wherein said first semiconductor layer A is by binary or the unadulterated Al of ternary xGa 1-xN (0≤x＜1) makes, and the described second semiconductor layer B is by the unadulterated Al of ternary yGa 1-yN (x＜y≤1) makes.
22. the field-effect transistor of claim 21, wherein said aluminium ratio of components x is about 0, and described aluminium ratio of components y is 0.15-0.30.
23. each field-effect transistor among the claim 20-22, the thickness of the wherein said second semiconductor layer B are 1nm or bigger.
24. one kind by Al xGa 1-xThe growing method of high resistivity semiconductor layer A on the growing semiconductor crystal face that N (0≤x≤1) makes by crystal growth, wherein said high resistivity semiconductor layer A is by unadulterated A1 xGa 1-xN (0≤x≤1) makes, and the crystal growth temperature of described high resistivity semiconductor layer A is set at 1120 ℃-1160 ℃ at the commitment of crystal growing process at least.
25. the growing method of claim 24, the crystal growth rate of wherein said high resistivity semiconductor layer A are 65nm/ minute or higher at the commitment of described crystal growing process at least.
26. the growing method of claim 24 or 25, wherein said high resistivity semiconductor layer A made by unadulterated GaN crystal.
27. each growing method among the claim 24-26, the crystal growth rate of wherein said high resistivity semiconductor layer A are 100nm/ minute or lower at the commitment of described crystal growing process at least.
28. each growing method among the claim 24-27, the crystal growth rate of wherein said high resistivity semiconductor layer A are 70nm/ minute-90nm/ minute at the commitment of described crystal growing process at least.
29. each growing method among the claim 24-28, the crystal growth temperature of wherein said high resistivity semiconductor layer A are set at 1130 ℃-1150 ℃ at the commitment of described crystal growing process at least.
30. each growing method among the claim 24-29, the V/III ratio of the crystalline material gas of wherein supplying in reative cell are 1400-1550 at the commitment of the described crystal growing process of described high resistivity semiconductor layer A at least.
31. one kind by unadulterated Al xGa 1-xThe III group-III nitride compound semiconductor that N (0≤x≤1) makes, its by according among the claim 24-30 each the growing method manufacturing and have 1 * 10 8Ω cm or higher resistivity.
32. a field-effect transistor comprises:
The crystal growth substrate;
Resilient coating and barrier layer, it is made by the III group-III nitride compound semiconductor that is formed on the described crystal growth substrate; With
Passage is formed on the interface side of described resilient coating towards described barrier layer,
Wherein comprise high resistivity semiconductor A to the described resilient coating of small part, described high resistivity semiconductor A is by unadulterated Al xGa 1-xN (0≤x≤1) makes and has 1 * 10 8Ω cm or higher resistivity.
33. a semiconductor device, it forms by a plurality of semiconductor layers of deposition, and each semiconductor layer is made by III group-III nitride compound semiconductor on the crystal growth substrate, and described semiconductor device comprises:
High resistivity layer, it prevents from or suppresses electric current to leak,
Wherein said high resistivity layer is made by high resistivity semiconductor layer A, and described high resistivity semiconductor layer A is by unadulterated Al xGa 1-xN (0≤x≤1) makes and has 1 * 10 8Ω cm or higher resistivity.
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