CN114660857A - Display panel and mobile terminal - Google Patents
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- CN114660857A CN114660857A CN202210286400.8A CN202210286400A CN114660857A CN 114660857 A CN114660857 A CN 114660857A CN 202210286400 A CN202210286400 A CN 202210286400A CN 114660857 A CN114660857 A CN 114660857A
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
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Abstract
The embodiment of the application provides a display panel and a mobile terminal; the display panel comprises a plurality of sub-pixels, each sub-pixel comprises a pixel electrode and a common electrode which is arranged in a different layer with the pixel electrode, wherein in the top view direction of the display panel, the orthographic projection of the common electrode on the pixel electrode is superposed with the pixel electrode; the display panel has the advantages that the orthographic projection of the common electrode in each sub-pixel on the pixel electrode is overlapped with the pixel electrode, the overlapping area of the common electrode and the pixel electrode in the direction perpendicular to the display panel is increased, the load capacitance of the pixel electrode is increased, the parasitic capacitance generated between the data line and the pixel electrode is further reduced, the vertical crosstalk phenomenon of the picture of the display panel is prevented, and the display effect of the display panel is further improved.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel and a mobile terminal.
Background
With the development of liquid crystal display technology, liquid crystal display devices such as liquid crystal display panels (Light Emitting Diode panels) have been widely used as display components in electronic products such as mobile phones, digital cameras, and personal digital assistants.
Currently, Thin Film transistors (Thin Film transistors) are widely used in liquid crystal display panels. However, due to the inevitable existence of the metal-to-metal lamination and the jumper structure in the panel design, some parasitic capacitance, such as the parasitic capacitance between the data line and the pixel electrode, inevitably exists, and the existence of the parasitic capacitance affects the display effect of the panel. When the parasitic capacitance between the data line and the pixel electrode is too large, the panel may have a vertical crosstalk problem.
Therefore, a display panel and a mobile terminal are needed to solve the above technical problems.
Disclosure of Invention
The embodiment of the application provides a display panel and a mobile terminal, so as to solve the technical problem that vertical crosstalk occurs in the picture of the display panel in the prior art.
The embodiment of the application provides a display panel, which comprises a plurality of sub-pixels, wherein each sub-pixel comprises a pixel electrode and a common electrode which is arranged in a different layer from the pixel electrode;
in a top view direction of the display panel, an orthographic projection of the common electrode on the pixel electrode coincides with the pixel electrode.
Optionally, in some embodiments of the present application, the pixel electrode includes a main electrode and a plurality of branch electrodes, and the main electrode divides the sub-pixel into a plurality of domains;
in each domain, the branch electrodes extend from the main electrode along different directions, and a plurality of first openings are formed at one ends of two adjacent branch electrodes far away from the main electrode.
Optionally, in some embodiments of the present application, the trunk electrode includes a first sub-electrode disposed along a first direction and a second sub-electrode disposed along a second direction, the second sub-electrode is electrically connected to the first sub-electrode, the first direction is perpendicular to the second direction, and the second direction is parallel to a length direction of a data line in the display panel;
wherein the width of the second sub-electrode is smaller than the width of the first sub-electrode.
Optionally, in some embodiments of the present application, the main electrode includes a third sub-electrode disposed along the first direction and a peripheral electrode disposed around the plurality of branch electrodes, and the third sub-electrode divides the sub-pixel into two domains;
the branch electrodes comprise a plurality of first sub-branch electrodes and a plurality of second sub-branch electrodes, one end of each first sub-branch electrode is electrically connected with the corresponding third sub-electrode, and the other end of each first sub-branch electrode is electrically connected with the corresponding peripheral electrode; one end of the second sub-branch electrode is electrically connected with the peripheral electrode.
Optionally, in some embodiments of the present application, two adjacent second sub-branch electrodes arranged along the first direction are electrically connected within the same domain.
Optionally, in some embodiments of the present application, a plurality of second openings are disposed between two adjacent second sub-branch electrodes disposed along the first direction in the same domain.
Optionally, in some embodiments of the present application, the display panel further includes a plurality of scan lines and a plurality of data lines, and intersection regions of the plurality of scan lines and the plurality of data lines form the sub-pixels;
wherein, in a top view direction of the display panel, a projection of the data line on the display panel is located outside the pixel electrode.
Optionally, in some embodiments of the present application, each of the sub-pixels further includes a substrate, a first metal layer disposed on the substrate, a gate insulating layer disposed on the first metal layer, a second metal layer disposed on the gate insulating layer and covering a part of the active layer, a passivation layer disposed on the second metal layer and covering the second electrode, and a pixel electrode disposed on the passivation layer;
the first metal layer includes the common electrode and the scan line, and the second metal layer includes the data line.
Optionally, in some embodiments of the present application, in a top view direction of the display panel, an orthographic projection area of the common electrode on the substrate is larger than an orthographic projection area of the pixel electrode on the substrate.
Correspondingly, the embodiment of the application also provides a mobile terminal, which comprises a terminal main body and the display panel, wherein the terminal main body and the display panel are combined into a whole.
The embodiment of the application provides a display panel and a mobile terminal; the display panel comprises a plurality of sub-pixels, each sub-pixel comprises a pixel electrode and a common electrode arranged in a different layer with the pixel electrode, wherein in the top view direction of the display panel, the orthographic projection of the common electrode on the pixel electrode is superposed with the pixel electrode; according to the display panel, the orthographic projection of the common electrode in each sub-pixel on the pixel electrode is superposed with the pixel electrode, so that the overlapping area of the common electrode and the pixel electrode in the direction perpendicular to the display panel is increased, the load capacitance of the pixel electrode is increased, the parasitic capacitance generated between the data line and the pixel electrode is further reduced, the vertical crosstalk phenomenon of the picture of the display panel is prevented, and the display effect of the display panel is further improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic view of a pixel structure of a display panel according to a first embodiment of the present disclosure;
fig. 2 is a schematic equivalent circuit diagram of a pixel structure in a display panel according to a first embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a first sub-pixel electrode in a display panel according to a first embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a first subpixel electrode in a display panel according to a second embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a first subpixel electrode in a display panel according to a third embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The embodiment of the application aims at the technical problem that vertical crosstalk occurs in the picture of the display panel in the prior art, and the embodiment of the application can solve the technical problem.
Referring to fig. 1 to 5, an embodiment of the present disclosure provides a display panel 100, where the display panel 100 includes a plurality of sub-pixels, each of the sub-pixels includes a pixel electrode 20 and a common electrode disposed in a different layer from the pixel electrode 20;
in a top view direction of the display panel 100, an orthogonal projection of the common electrode on the pixel electrode 20 coincides with the pixel electrode 20.
The display panel 100 provided in the embodiment of the present application increases the overlapping area of the common electrode and the pixel electrode 20 perpendicular to the display panel 100 in the direction through the orthographic projection of the common electrode in each sub-pixel on the pixel electrode 20 and the coincidence of the pixel electrode 20, and further increases the load capacitance of the pixel electrode 20, thereby further reducing the parasitic capacitance generated between the data line 102 and the pixel electrode 20, further preventing the vertical crosstalk phenomenon occurring on the picture of the display panel 100, and further improving the display effect of the display panel 100.
The technical solution of the present application will now be described with reference to specific embodiments.
Example one
Fig. 1 is a schematic diagram of a pixel structure of a display panel 100 according to a first embodiment of the present application; the display panel 100 includes a plurality of sub-pixels arranged in an array, and each sub-pixel has an eight-domain 2110 pixel structure.
The display panel 100 further includes a plurality of scan lines 101 and a plurality of data lines 102, and intersection regions of the plurality of scan lines 101 and the plurality of data lines 102 form the sub-pixels.
Fig. 2 is a schematic diagram of an equivalent circuit of a pixel structure in a display panel 100 according to a first embodiment of the present application; as can be seen from fig. 1 and fig. 2, each of the sub-pixels includes a tft area 11 and a pixel electrode area 12, and the pixel electrode area 12 includes a first sub-pixel electrode area 121 located at one side of the tft area 11 and a second sub-pixel electrode area 122 located at the other side of the tft area 11.
In the embodiment of the present application, each of the sub-pixels includes the pixel electrode 20 and the common electrode disposed in a different layer from the pixel electrode 20.
Further, in the embodiment of the present application, the thin film transistor region 11 includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a first storage capacitor Cst1, a second storage capacitor Cst2, a first liquid crystal capacitor Clc1, a second liquid crystal capacitor Clc2, and a shared circuit bar 103.
The source electrode of the first thin film transistor T1 is electrically connected to the data line 102, the gate electrode is electrically connected to the scan line 101, and the drain electrode is electrically connected to the first storage capacitor Cst1 and the first liquid crystal capacitor Clc 1;
the source electrode of the second thin film transistor T2 is electrically connected to the data line 102, the gate electrode is electrically connected to the scan line 101, and the drain electrode is electrically connected to the second storage capacitor Cst2 and the second liquid crystal capacitor Clc 2;
the source of the third thin film transistor T3 is electrically connected to the second storage capacitor Cst2 and the second liquid crystal capacitor Clc2, the gate thereof is electrically connected to the scan line 101, and the drain thereof is electrically connected to the common bar 103.
The first storage capacitor Cst1 includes a first electrode plate and a second electrode plate disposed opposite to the first electrode plate, the first electrode plate of the first storage capacitor Cst1 is the common electrode on the side of the array substrate, and the second electrode plate of the first storage capacitor Cst1 is the first subpixel electrode 21 in the first subpixel electrode region 121.
The second storage capacitor Cst2 includes the second electrode plate and a second electrode plate disposed opposite to the second electrode plate, the first electrode plate of the first storage capacitor Cst2 is a common electrode of the array substrate, and the second electrode plate of the second storage capacitor Cst2 is the second subpixel electrode 22 in the second subpixel electrode region 122.
The first liquid crystal capacitor Clc1 includes a third electrode plate and a fourth electrode plate disposed opposite to the third electrode plate, the third electrode plate of the first liquid crystal capacitor Clc1 is electrically connected to the common electrode, and the fourth electrode plate of the first liquid crystal capacitor Clc1 is electrically connected to the drain electrode of the first thin film transistor T1.
The third electrode plate of the second liquid crystal capacitor Clc2 is electrically connected to the common electrode, and the fourth electrode plate of the second liquid crystal capacitor Clc2 is electrically connected to the drain electrode of the second thin film transistor T2.
In the embodiment of the present application, the first and second sub pixel electrode regions 121 and 122 correspond to liquid crystal molecules of the four domains 2110, respectively. In the manufacturing process, the common electrode in the first sub-pixel electrode region 121 may be connected to the first sub-pixel electrode 21 through a via hole, and the common electrode in the second sub-pixel electrode region 122 may be connected to the second sub-pixel electrode 22 through a via hole.
In the embodiment of the present application, the common electrode, the gate electrode of the first thin film transistor T1, the gate electrode of the second thin film transistor T2, the gate electrode of the third thin film transistor T3, and the scan line 101 in the sub-pixel are made by a first metal layer M1; the source and drain electrodes of the first thin film transistor T1, the source and drain electrode of the second thin film transistor T2, the source and drain electrode of the third thin film transistor T3, the data line 102, and the shared circuit bar 103 are fabricated through a second metal layer M2.
With reference to fig. 1 and fig. 2, a driving principle of a pixel structure provided in the embodiment of the present application is specifically as follows:
when the scanning line 101 turns on 3 tfts in the sub-pixel, respectively, the signal of the data line 102 enters the corresponding first sub-pixel electrode region 121 and second sub-pixel electrode region 122 through the first tft T1 and the second tft T2, and discharges a part of the voltage of the second sub-pixel electrode region 122 to the shared circuit bar 103 through the third tft T3, thereby avoiding problems such as horizontal crosstalk in the sub-pixel.
In an embodiment of the present application, each of the sub-pixels further includes:
a substrate;
a first metal layer M1 disposed on the substrate;
a gate insulating layer disposed on the first metal layer M1;
an active layer disposed on the gate insulating layer;
the second metal layer is arranged on the grid insulating layer and covers part of the active layer;
a passivation layer disposed on the second metal layer;
a pixel electrode 20 disposed on the passivation layer, and including a first subpixel electrode 21 in the first subpixel electrode region 121 and a second subpixel electrode 22 in the second subpixel electrode region 122;
the first metal layer M1 includes the common electrode and the gate of the first thin film transistor T1, and the second metal layer includes the source and drain of the first thin film transistor T1.
In the embodiments of the present application, the substrate may be a glass substrate; the active layer comprises a channel region and doped regions, and the doped regions are located on two sides of the channel region. The active layer may be an oxide active layer or a low temperature polysilicon active layer. For example, in some embodiments, the material of the active layer is indium tin oxide, and Ln-IZO, ITZO, ITGZO, HIZO, IZO (InZnO), ZnO: F, In can be used2O3:Sn、In2O3:Mo、Cd2SnO4、ZnO:Al、TiO2Nb, Cd-Sn-O or other metalsAn oxide. The doped region can be a P-type doped region or an N-type doped region, and when the doped region is a P-type doped region, the doping element of the doped region is one or a mixture of two of boron and indium. When the doped region is an N-type doped region, the doping element of the doped region is one or a mixture of several of phosphorus, arsenic and antimony.
Further, the material of the gate insulating layer may be one of silicon nitride, silicon oxide, silicon oxynitride, or aluminum oxide, or any combination thereof.
Wherein the first metal layer M1 includes a gate electrode and a common electrode of the first thin film transistor T1; the first metal layer M1 may be made of Cr, W, Ti, Ta, Mo, Al, Cu, or other metals or alloys, and a gate metal layer made of multiple layers of metals may also meet the requirements.
The passivation layer covers the gate insulating layer and the gate, wherein the passivation layer may be an oxide or an oxynitride.
The second metal layer M2 includes a source and a drain of the first thin film transistor T1, and the source and the drain are electrically connected to the doped regions at both sides of the channel region, respectively. The second metal layer can be made of Cr, W, Ti, Ta, Mo, Al, Cu and other metals or alloys, and a grid metal layer consisting of multiple layers of metals can also meet the requirement. The second sub-electrode 2112 is disposed on the gate insulating layer and is in contact with the source and drain of the first thin film transistor T1.
The passivation layer can be made of SiOx、SiOx/SiNxLamination or SiOx/SiNx/Al2O3Laminated inorganic non-metal film layer material.
The first subpixel electrode 21 and the second subpixel electrode 22 may be made of Indium Tin Oxide (ITO).
Fig. 3 is a schematic structural diagram of a first sub-pixel electrode 21 in a display panel 100 according to a first embodiment of the present application; the first sub-pixel electrode 21 includes a main electrode 211 and a plurality of branch electrodes 212, wherein the main electrode 211 divides the sub-pixel into a plurality of domains 2110;
wherein, in each of the domains 2110, the branch electrodes 212 extend from the main electrode 211 in different directions.
In the embodiment of the present application, the main electrode 211 divides one sub-pixel into a plurality of domains 2110. In general, the trunk electrode 211 has a cross shape, and the trunk of the cross shape divides one sub-pixel into four domains 2110; of course, the main electrode 211 may have other shapes, and divide one sub-pixel into a larger number of domains 2110.
In the embodiment of the present application, the branch electrodes 212 extend from the main electrode 211 in different directions in each of the domains 2110, the branch electrodes 212 in one of the domains 2110 are parallel to each other and spaced apart from each other, and the extension directions of the branch electrodes 212 in two adjacent domains 2110 are different.
Preferably, the branch electrodes 212 are thin stripe-shaped, and the branch electrodes 212 in each domain 2110 extend along directions which form angles of 45 °, 135 °, -135 °, and-45 ° with the horizontal direction (the direction parallel to the scan line 101); the plurality of branch electrodes 212 and the main electrode 211 are matched to form a 'meter' -shaped pattern.
Further, in the embodiment of the present application, the first sub-pixel electrode 21 further includes a closed frame electrode 213 disposed around the plurality of branch electrodes 212, and the closed frame connects the ends of all the branch electrodes 212 (taking the end of the branch electrode 212 away from the main electrode 211 as the end) and the main electrode 211.
Preferably, the closed frame electrode 213 is rectangular in shape, and forms a structure of a shape like a Chinese character 'hui'.
The shape of the closed frame electrode 213 is regular, so that the peripheral edges of the first subpixel electrode 21 are regular, the electric field at the edges of the first subpixel electrode 21 is regular, the orientations of the liquid crystal molecules at the edges of the subpixels are uniform, and the dark fringes at the peripheral edges of the subpixels can be eliminated.
In the embodiment of the present application, in the top view direction of the display panel 100, the orthogonal projection of the common electrode on the pixel electrode 20 coincides with the pixel electrode 20. In the above design, the pixel electrode 20 can shield an electric field between the common electrode on the array substrate side and the common electrode on the color filter substrate side, so that display of a picture is not affected, and the common electrode on the array substrate side and the pixel electrode 20 form a storage capacitor, so that a load capacitance of the pixel electrode 20 is increased. Since the load capacitance of the pixel electrode 20 is in inverse proportion to the parasitic capacitance formed between the data line 102 and the pixel electrode 20, the magnitude of the parasitic capacitance between the data line 102 and the pixel electrode 20 can be reduced, thereby preventing the vertical crosstalk phenomenon from occurring on the picture of the display panel 100, and further improving the display effect of the display panel 100.
The reason why the load capacitance of the pixel electrode 20 is in inverse proportion to the parasitic capacitance formed between the data line 102 and the pixel electrode 20 is given by the following formula:
ΔV＝(Vgh-Vgl)*Cgs/(Cst+Clc+Cgs)
where Δ V is a feed-through voltage of the sub-pixel, Vgh is a gate high potential voltage of the driving thin film transistor in the sub-pixel, Vgl is a gate low potential voltage of the driving thin film transistor in the sub-pixel, Cgs is a parasitic capacitance between the gate and the source of the driving thin film transistor in the sub-pixel, Cst is a load capacitance of the pixel electrode 20, and Clc is a liquid crystal capacitance. Therefore, when the load capacitance of the pixel electrode 20 increases, the feedthrough voltage Δ V of the sub-pixel decreases, resulting in a decrease in the parasitic capacitance formed between the data line 102 and the pixel electrode 20.
When the parasitic capacitance between the data line 102 and the pixel electrode 20 is too large, the display panel 100 may have a vertical crosstalk problem. This is because the operating voltage on the data line 102 forms a diffusion electric field, and a parasitic electric field is formed in addition to the pixel voltage, which causes misalignment in the alignment direction of the liquid crystal near the data line 102. The liquid crystal in these disclination regions can not only be precisely controlled by the pixel voltage, but also have a larger liquid crystal transmission amount than that in the central region of the pixel, forming a longitudinal light leakage region along the data line 102. When the parasitic capacitance between the data line 102 and the pixel electrode 20 is large, the diffusion electric field of the corresponding data line 102 is large, the larger the area of the light leakage to the fault is, and the more obvious the vertical crosstalk is.
Further, the main electrode 211 includes a first sub-electrode 2111 disposed along a first direction D1 and a second sub-electrode 2112 disposed along a second direction D2, the second sub-electrode 2112 is electrically connected to the first sub-electrode 2111, the first direction D1 is perpendicular to the second direction D2, and the second direction D2 is parallel to a length direction of the data line 102 in the display panel 100;
wherein the width of the second sub-electrode 2112 is smaller than the width of the first sub-electrode 2111. The design can reduce the facing area between the pixel electrode 20 and the data line 102, and further reduce the parasitic capacitance between the data line 102 and the pixel electrode 20.
Further, in a top view direction of the display panel 100, a projection of the data line 102 on the display panel 100 is located outside the pixel electrode 20. The design can further reduce the facing area between the pixel electrode 20 and the data line 102, and further reduce the parasitic capacitance between the data line 102 and the pixel electrode 20.
Further, in the top view direction of the display panel 100, an orthographic projection area of the common electrode on the substrate is larger than an orthographic projection area of the pixel electrode 20 on the substrate. The design can ensure that the common electrode can completely cover the pixel electrode 20, so that the pixel electrode 20 can shield an electric field between the common electrode on the array substrate side and the common electrode on the color film substrate side, and further reduce the parasitic capacitance between the data line 102 and the pixel electrode 20.
For the technical problem of vertical crosstalk occurring in the picture of the display panel 100 in the prior art, the present embodiment can solve the above technical problem, and the present embodiment provides a display panel 100; the display panel 100 includes a plurality of sub-pixels, each of which includes a pixel electrode 20 and a common electrode disposed in a different layer from the pixel electrode 20, wherein, in a top view direction of the display panel 100, an orthogonal projection of the common electrode on the pixel electrode 20 coincides with the pixel electrode 20; in the display panel 100, the orthographic projection of the common electrode in each sub-pixel on the pixel electrode 20 coincides with the pixel electrode 20, so that the overlapping area of the common electrode and the pixel electrode 20 in the direction perpendicular to the display panel 100 is increased, and the load capacitance of the pixel electrode 20 is increased, thereby further reducing the parasitic capacitance generated between the data line 102 and the pixel electrode 20, further preventing the vertical crosstalk phenomenon from occurring on the picture of the display panel 100, and further improving the display effect of the display panel 100.
Example two
Fig. 4 is a schematic structural diagram of a first sub-pixel electrode 20 in a display panel 100 according to a second embodiment of the present application; the structure of the display panel 100 in the second embodiment of the present disclosure is the same as or similar to the structure of the display panel 100 in the first embodiment of the present disclosure, except that, in each of the domains 2110, the branch electrodes 212 extend from the main electrode 211 in different directions, and a plurality of first openings 2121 are formed at one end of each of two adjacent branch electrodes 212 away from the main electrode 211 (that is, the pixel electrode 20 is not provided with the first closed frame electrode 213).
Compared with the display panel 100 provided in the first embodiment of the present application, the display panel 100 provided in the second embodiment of the present application further reduces the area of the pixel electrode 20, thereby further reducing the parasitic capacitance generated between the data line 102 and the pixel electrode 20, further preventing the vertical crosstalk phenomenon from occurring on the picture of the display panel 100, and further improving the display effect of the display panel 100. This is because according to the formula: c ═ S/d (where ∈ is the dielectric constant of the interpolar medium, S is the plate area, d is the distance between the plates, and C plate area) shows that when the area of the pixel electrode 20 is reduced, the parasitic capacitance generated between the data line 102 and the pixel electrode 20 can be effectively reduced.
Aiming at the technical problem of vertical crosstalk occurring in the picture of the display panel 100 in the prior art, the embodiment of the present application can solve the technical problem, and provides a display panel 100; the display panel 100 includes a plurality of sub-pixels, each of which includes a pixel electrode 20 and a common electrode disposed in a different layer from the pixel electrode 20, wherein, in a top view direction of the display panel 100, an orthographic projection of the common electrode on the pixel electrode 20 coincides with the pixel electrode 20; in the display panel 100, the orthographic projection of the common electrode in each sub-pixel on the pixel electrode 20 coincides with the pixel electrode 20, so that the overlapping area of the common electrode and the pixel electrode 20 in the direction perpendicular to the display panel 100 is increased, and the load capacitance of the pixel electrode 20 is increased, thereby further reducing the parasitic capacitance generated between the data line 102 and the pixel electrode 20, further preventing the vertical crosstalk phenomenon from occurring on the picture of the display panel 100, and further improving the display effect of the display panel 100. Meanwhile, in the display panel 100 provided in the second embodiment of the present application, compared to the display panel 100 provided in the first embodiment of the present application, the area of the pixel electrode 20 is further reduced by removing the closed frame electrode 213 of the pixel electrode 20.
EXAMPLE III
Fig. 5 is a schematic structural diagram of a first sub-pixel electrode 20 in a display panel 100 according to a third embodiment of the present application; the structure of the display panel 100 in the third embodiment of the present application is the same as or similar to the structure of the display panel 100 in the first embodiment of the present application, except that the main electrode 211 includes a third sub-electrode 2113 disposed along the first direction D1 and a peripheral electrode 2114 disposed around the plurality of branch electrodes 212, and the third sub-electrode 2113 divides the sub-pixel into two domains 2110;
the branch electrode 212 includes a plurality of first sub-branch electrodes 212 and a plurality of second sub-branch electrodes 212, one end of the first sub-branch electrode 212 is electrically connected to the third sub-electrode 2113, and the other end of the first sub-branch electrode 212 is electrically connected to the peripheral electrode 2114; one end of the second sub branch electrode 212 is electrically connected to the peripheral electrode 2114.
In the embodiment of the present application, a plurality of second openings 2122 are disposed between two adjacent second sub-branch electrodes 212 disposed along the first direction D1 in the same domain 2110. By such an arrangement, the area of the pixel electrode 20 can be further reduced, so that the parasitic capacitance generated between the data line 102 and the pixel electrode 20 is further reduced, the vertical crosstalk phenomenon occurring on the picture of the display panel 100 is prevented, and the display effect of the display panel 100 is further improved.
In another embodiment of the present application, in the same domain 2110, two adjacent second sub-branch electrodes 212 disposed along the first direction D1 are electrically connected.
Compared with the display panel 100 provided in the first embodiment of the present application, in the display panel 100 provided in the third embodiment of the present application, the third sub-electrode 2113 provided along the first direction D1 is only arranged in the main electrode 211, so that the area of the pixel electrode 20 is further reduced, thereby further reducing the parasitic capacitance generated between the data line 102 and the pixel electrode 20, further preventing the vertical crosstalk phenomenon occurring in the picture of the display panel 100, and further improving the display effect of the display panel 100.
For the technical problem of vertical crosstalk occurring in the picture of the display panel 100 in the prior art, the present embodiment can solve the above technical problem, and the present embodiment provides a display panel 100; the display panel 100 includes a plurality of sub-pixels, each of which includes a pixel electrode 20 and a common electrode disposed in a different layer from the pixel electrode 20, wherein, in a top view direction of the display panel 100, an orthogonal projection of the common electrode on the pixel electrode 20 coincides with the pixel electrode 20; in the display panel 100, the orthographic projection of the common electrode in each sub-pixel on the pixel electrode 20 coincides with the pixel electrode 20, so that the overlapping area of the common electrode and the pixel electrode 20 in the direction perpendicular to the display panel 100 is increased, and the load capacitance of the pixel electrode 20 is increased, thereby further reducing the parasitic capacitance generated between the data line 102 and the pixel electrode 20, further preventing the vertical crosstalk phenomenon from occurring on the picture of the display panel 100, and further improving the display effect of the display panel 100.
For the technical problem of vertical crosstalk occurring in the picture of the display panel 100 in the prior art, the present embodiment can solve the above technical problem, and the present embodiment provides a display panel 100; the display panel 100 includes a plurality of sub-pixels, each of which includes a pixel electrode 20 and a common electrode disposed in a different layer from the pixel electrode 20, wherein, in a top view direction of the display panel 100, an orthogonal projection of the common electrode on the pixel electrode 20 coincides with the pixel electrode 20; in the display panel 100, the orthographic projection of the common electrode in each sub-pixel on the pixel electrode 20 coincides with the pixel electrode 20, so that the overlapping area of the common electrode and the pixel electrode 20 in the direction perpendicular to the display panel 100 is increased, and the load capacitance of the pixel electrode 20 is increased, thereby further reducing the parasitic capacitance generated between the data line 102 and the pixel electrode 20, further preventing the vertical crosstalk phenomenon from occurring on the picture of the display panel 100, and further improving the display effect of the display panel 100. Meanwhile, in the display panel 100 provided in the third embodiment of the present application, compared to the display panel 100 provided in the first embodiment of the present application, by removing a portion of the trunk electrode 211 in the pixel electrode 20, the area of the pixel electrode 20 is further reduced.
Correspondingly, an embodiment of the present application further provides a mobile terminal, including the display panel 100 as described in any one of the above. The mobile terminal is mainly applied to an active matrix organic electroluminescent display panel 100, and has a wide application space in vehicle-mounted, mobile phone, tablet, computer and television products.
The display panel 100 and the mobile terminal provided in the embodiments of the present application are described in detail above, and specific examples are applied herein to illustrate the principles and embodiments of the present application, and the description of the embodiments is only used to help understand the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A display panel is characterized by comprising a plurality of sub-pixels, wherein each sub-pixel comprises a pixel electrode and a common electrode which is arranged in a different layer from the pixel electrode;
in a top view direction of the display panel, an orthographic projection of the common electrode on the pixel electrode coincides with the pixel electrode.
2. The display panel according to claim 1, wherein the pixel electrode comprises a main electrode and a plurality of branch electrodes, the main electrode dividing the sub-pixels into a plurality of domains;
in each domain, the branch electrodes extend from the main electrode along different directions, and a plurality of first openings are formed at one ends of two adjacent branch electrodes far away from the main electrode.
3. The display panel according to claim 2, wherein the trunk electrode includes a first sub-electrode arranged in a first direction and a second sub-electrode arranged in a second direction, the second sub-electrode being electrically connected to the first sub-electrode, the first direction being perpendicular to the second direction, the second direction being parallel to a length direction of a data line in the display panel;
wherein the width of the second sub-electrode is smaller than the width of the first sub-electrode.
4. The display panel according to claim 2, wherein the main electrode includes a third sub-electrode arranged in a first direction and a peripheral electrode arranged around the plurality of branch electrodes, the third sub-electrode dividing the sub-pixel into two domains;
the branch electrodes comprise a plurality of first sub-branch electrodes and a plurality of second sub-branch electrodes, one end of each first sub-branch electrode is electrically connected with the corresponding third sub-electrode, and the other end of each first sub-branch electrode is electrically connected with the corresponding peripheral electrode; one end of the second sub-branch electrode is electrically connected with the peripheral electrode.
5. The display panel according to claim 4, wherein adjacent two of the second sub-branch electrodes arranged in the first direction are electrically connected in the same domain.
6. The display panel according to claim 4, wherein a plurality of second openings are provided between two adjacent second sub-branch electrodes arranged in the first direction in the same domain.
7. The display panel according to claim 1, wherein the display panel further comprises a plurality of scan lines and a plurality of data lines, and intersection regions of the plurality of scan lines and the plurality of data lines form the sub-pixels;
in a top view direction of the display panel, a projection of the data line on the display panel is located outside the pixel electrode.
8. The display panel according to claim 7, wherein each of the sub-pixels further comprises:
a substrate;
a first metal layer disposed on the substrate;
the grid insulation layer is arranged on the first metal layer;
an active layer disposed on the gate insulating layer;
the second metal layer is arranged on the grid insulating layer and covers part of the active layer;
a passivation layer disposed on the second metal layer; and
the pixel electrode is arranged on the passivation layer;
wherein the first metal layer includes the common electrode and the scan line, and the second metal layer includes the data line.
9. The display panel according to claim 8, wherein an area of an orthographic projection of the common electrode on the substrate is larger than an area of an orthographic projection of the pixel electrode on the substrate in a top view direction of the display panel.
10. A mobile terminal characterized by comprising a terminal body and the display panel according to any one of claims 1 to 9, the terminal body being integrated with the display panel.
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| CN202210286400.8A CN114660857A (en) | 2022-03-22 | 2022-03-22 | Display panel and mobile terminal |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210286400.8A CN114660857A (en) | 2022-03-22 | 2022-03-22 | Display panel and mobile terminal |
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