CN114640323A - Single-ended input differential output radio frequency active phase shifter - Google Patents
Single-ended input differential output radio frequency active phase shifter Download PDFInfo
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- CN114640323A CN114640323A CN202210281001.2A CN202210281001A CN114640323A CN 114640323 A CN114640323 A CN 114640323A CN 202210281001 A CN202210281001 A CN 202210281001A CN 114640323 A CN114640323 A CN 114640323A
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- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
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- H03H11/02—Multiple-port networks
- H03H11/16—Networks for phase shifting
Abstract
A single-ended input differential output radio frequency active phase shifter relates to electronic systems such as radio frequency transceiving and phased arrays, and is particularly suitable for the field of broadband active and high-precision phased arrays. The invention forms the orthogonal coupler by the coupling line; an amplitude adjusting module is formed by a common grid NMOS transistor array, and the phase shifting function is realized through a digital control unit array; an active inductance module is formed by a common-grid NMOS transistor array, so that phase fine adjustment is realized, and input matching is realized; an output module is formed by an inductor and a resistor network, and broadband matching is realized. The invention is suitable for CMOS process, eliminates phase precision error caused by fixed digital algorithm of active phase shifter, realizes input end matching and reduces power transmission reflection. Finally, 360-degree phase adjustment and 6-bit phase shift are realized, precision correction can be carried out, and the active radio frequency phase shifter is high in broadband.
Description
Technical Field
The invention belongs to the field of radio frequency integrated circuits, relates to a single-ended input differential output radio frequency active phase shifter, and particularly relates to the technical field of high-precision phased array systems.
Background
The CMOS process technology has advanced dramatically driven by factors such as cost, integration, and power consumption. The cut-off frequency of the CMOS transistor can meet the integrated circuit design of a frequency band above several GHz. With the development of 5G phased array technology, the active phase shifter is widely concerned due to the advantages of flexible design, high phase shifting precision, convenience in calibration and the like. As the multi-array antenna and the beam forming technology become the key technologies of 5G communication, the phased array communication system is developed rapidly.
The phase shifter is used as a key module of the phased array system, and the electronic beam scanning function is realized by the phase of the antenna transmitting and receiving signals of the phased array unit. With the higher requirements of users on insertion loss and phase shift precision and the requirements on integration level and system area, the active phase shifter is developed greatly. The active phase shifter generally comprises a quadrature network, an amplitude control array unit and a vector synthesis adder. Radio frequency integrated circuits, particularly millimeter wave integrated circuits, are typically implemented using chemical compounds. However, the compound process is expensive, difficult to implement a complex logic control unit, and is not compatible with the CMOS process. In the civil markets of 5G mobile communication, vehicle-mounted and unmanned airborne radars and the like in the future, the silicon-based active phase shifter with excellent performance is promoted to meet the requirements on small size, high precision and low cost.
At present, for a higher frequency band, the amplitude of an orthogonal signal is realized by adopting a switch array technology, so that the phase shift is realized, but the current technology mainly has the following problems: the leakage current of the non-ideal characteristic of the switch in the microwave frequency band can cause the deviation of the amplitude of the orthogonal signal, thereby causing additional phase shift and causing the reduction of the phase shift precision. Secondly, in the vector synthesis adder, the resistance of the inductance and capacitance devices changes along with the frequency change, so that the system gain changes along with the frequency, and the directional power of a user changes along with the frequency, so that the beam power or the phase angle shifts along with the change of the working frequency. The common method is to change the phase shifter into single-ended output by adopting a transformer, design the rear-stage driving amplifier into single-ended, and carry out cascade matching, and the design method can sacrifice the chip area. Vector networks are usually realized in a differential mode, so for single-ended input, balun is usually adopted to convert differential signals, a rear stage adopts a double transformer to convert two pairs of orthogonal differential signals (as described in patent CN 110212887A), and the double-transformer orthogonal networks are mutually coupled in a microwave band to cause that the design is very difficult, and the design is almost guaranteed by the precision of electromagnetic simulation software. Currently, the phase shift precision is improved by adopting an array current fine adjustment technology, the parasitic capacitance introduced at the input end of the vector adder can deteriorate the input matching, and the shift precision is limited to be greatly improved.
Disclosure of Invention
The purpose of the invention is as follows: aiming at the technical defects, the invention provides the active phase shifter which is suitable for the CMOS process, has a 360-degree phase shift range, 6-bit phase shift, single-ended input, differential output, high gain flatness and high precision.
In order to achieve the purpose, the invention adopts the following technical scheme:
a single-ended input differential output radio frequency active phase shifter comprises a quadrature coupler and a balun network 100, a first amplitude control module 200 and a second amplitude control module 300 which are formed by transistor arrays for respectively controlling amplitudes of two quadrature paths of signals, a first active inductance module 500 and a second active inductance module 600 which are formed by transistor arrays for respectively carrying out phase fine adjustment, and an output load matching network 400; the input signal is connected with the signal input ends of the quadrature coupler and the balun network 100, and the quadrature differential signal output ends of the quadrature coupler and the balun network 100 are respectively connected with the signal input ends of the first active inductance module 500, the first amplitude control module 200, the second active inductance module 600 and the second amplitude control module 300; the signal output ends of the first active inductance module 500, the first amplitude control module 200, the second active inductance module 600 and the second amplitude control module 300 are respectively connected to the signal input end of the output load matching network 400.
Further, the quadrature coupler and balun network 100 includes a first quadrature coupler 101, a first transformer 102, a second transformer 103, a first transistor 104, a second transistor 105, and a first resistor 106;
the input end of the first orthogonal coupler 101 is connected with a signal RF _ IN, the isolation end is connected with a first resistor 106, the coupling end is connected with one end of a primary coil of a first transformer 102, and the through end is connected with one end of a primary coil of a second transformer 103; the other end of the primary coil of the first transformer 102 is grounded, one end of the secondary coil is connected with VIN +, the other end of the secondary coil is connected with VIN-, and a center tap is connected with a drain electrode of the first transistor 104; the other end of the primary coil of the second transformer 103 is grounded, one end of the secondary coil is connected with VQN +, the other end of the secondary coil is connected with VQN-, and a center tap is connected with the drain electrode of the second transistor 105; the sources of the first transistor 104 and the second transistor 105 are grounded, and the gates are connected with a bias voltage Vbias。
Further, the first amplitude control module 200 and the second amplitude control module 300 respectively include 20 parallel-connected common-gate transistor array units, each common-gate transistor array unit includes a third transistor 201, a fourth transistor 202, a fifth transistor 203, a sixth transistor 204, a first inverter 205, a second inverter 206, a second resistor 207, and a third resistor 208;
the sources of the third transistor 201 and the fourth transistor 202 are connected to the positive end of the differential signal input terminal in common; the sources of the fifth transistor 203 and the sixth transistor 204 are connected to the negative terminal of the differential signal input terminal; the input end of the first inverter 205 is connected with the digital control signal, the output end is connected with one end of the second resistor 207, the other end of the second resistor 207 is connected with the input end of the second inverter 206, and the input end of the second inverter 206 is simultaneously connected with the gates of the third transistor 201 and the sixth transistor 204; the output end of the second inverter 206 is connected to one end of a third resistor 208, and the other end of the third resistor 208 is connected to the gates of the fourth transistor 202 and the fifth transistor 203; the drains of the third transistor 201 and the fifth transistor 203 are commonly connected VOUT +, and the drains of the fourth transistor 202 and the sixth transistor 204 are commonly connected VOUT-.
Further, the first active inductor module 500 and the second active inductor module 600 respectively include 20 switch-controlled common-gate transistor array units; each common-gate transistor array unit comprises a seventh transistor 501, an eighth transistor 502, a third inverter 503 and a fourth resistor 504;
the input end of the third inverter 503 is connected to the digital control signal, the output end is connected to one end of the fourth resistor 504, and the other end of the fourth resistor 504 is connected to the gates of the seventh transistor 501 and the eighth transistor 502, respectively; the drains of the seventh transistor 501 and the eighth transistor 502 are respectively connected to the power supply voltage, the source of the seventh transistor 501 is connected to the positive terminal of the differential signal input terminal, and the source of the eighth transistor 502 is connected to the negative terminal of the differential signal input terminal.
Further, the fourth resistor 504 is an in-process radio frequency resistor, and when the output end of the third inverter 503 is at a high level, the seventh transistor 501, the eighth transistor 502, the third inverter 503, and the fourth resistor 504 form an active inductor.
Further, the output load matching network 400 includes a first inductor 401, a second inductor 402, a fifth resistor 403, a sixth resistor 404, a third inductor 405, and a fourth inductor 406; the first inductor 401, the fifth resistor 403, the third inductor 405, the second inductor 402, the sixth resistor 404 and the fourth inductor 406 respectively form a differential load; one end of the first inductor 401 and one end of the second inductor 402 are connected to the power supply VDD, and the other ends of the first inductor 401 and the second inductor 402 are respectively connected to one end of the fifth resistor 403 and one end of the sixth resistor 404; the other ends of the fifth resistor 403 and the sixth resistor 404 are respectively and correspondingly connected with output signal ends VoutP and VoutN; the output signal terminals VoutP and VoutN are respectively connected to one ends of the third inductor 405 and the fourth inductor 406, and the other ends of the third inductor 405 and the fourth inductor 406 are respectively and correspondingly connected to VOUT-and VOUT +.
By the novel phase shifter structure, the phase shifting precision is effectively improved, and the gain flatness is improved. At 8Ghz-12Ghz, the phase shift precision is better than 3 degrees, and the phase shift amplitude modulation is less than 0.5 dB.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
fig. 1 is a schematic diagram of an active phase shifter circuit according to the present invention;
FIG. 2 is an active inductor equivalent circuit of a phase trimmed transistor array cell;
FIG. 3 shows a 64-state phase shift simulation result of the active phase shifter according to the present invention;
FIG. 4 shows the simulation result of 64-state phase-shift RMS error of the active phase shifter according to the present invention;
fig. 5 shows simulation results of phase shifting and amplitude modulation of phase shift of the active phase shifter according to the present invention.
Detailed Description
To further illustrate the technical solutions disclosed in the present invention, the following detailed description is made with reference to the accompanying drawings and specific embodiments. It should be understood by those skilled in the art that the optimization design and modification method without departing from the spirit of the invention falls into the protection scope of the present invention, and the detailed description is not given to the technical skill in the art in this embodiment.
Example 1
As shown in fig. 1, the single-ended input differential output rf active phase shifter provided by the present invention is composed of a quadrature coupler and a balun network 100, a first amplitude control module 200 and a second amplitude control module 300 composed of transistor arrays for respectively controlling amplitudes of two quadrature signals, a first active inductance module 500 and a second active inductance module 600 composed of transistor arrays for respectively performing phase fine tuning, and an output load matching network 400.
The quadrature coupler and balun network 100 includes a first quadrature coupler 101, a first transformer 102, a second transformer 103, a first transistor 104, a second transistor 105, and a first resistor 106. The input end of the first orthogonal coupler 101 is connected with a signal RF _ IN, the isolation end is connected with a first resistor 106, the coupling end is connected with one end of a primary coil of a first transformer 102, and the through end is connected with one end of a primary coil of a second transformer 103; the other end of the primary coil of the first transformer 102 is grounded, one end of the secondary coil is connected with VIN +, the other end is connected with VIN-, and a center tap is connected with the drain electrode of the first transistor 104; the other end of the primary winding of the second transformer 103 is grounded, and one end of the secondary winding is connected toVQN +, the other end is connected to VQN-, the center tap is connected to the drain of the second transistor 105; the sources of the first transistor 104 and the second transistor 105 are grounded, and the gates are connected with a bias voltage Vbias。
The first amplitude control module 200 and the second amplitude control module 300 respectively formed by the transistor arrays for respectively controlling the amplitudes of the two orthogonal signals respectively comprise 20 parallel common-gate transistor array units. Each common-gate transistor array unit comprises a third transistor 201, a fourth transistor 202, a fifth transistor 203, a sixth transistor 204, a first inverter 205, a second inverter 206, a second resistor 207 and a third resistor 208; the sources of the third transistor 201 and the fourth transistor 202 are connected to the positive end of the differential signal input terminal in common; the sources of the fifth transistor 203 and the sixth transistor 204 are connected to the negative terminal of the differential signal input terminal; the input end of the first inverter 205 is connected with the digital control signal, the output end is connected with one end of the second resistor 207, the other end of the second resistor 207 is connected with the input end of the second inverter 206, and the input end of the second inverter 206 is simultaneously connected with the gates of the third transistor 201 and the sixth transistor 204; the output end of the second inverter 206 is connected to one end of a third resistor 208, and the other end of the third resistor 208 is connected to the gates of the fourth transistor 202 and the fifth transistor 203; the drains of the third transistor 201 and the fifth transistor 203 are commonly connected VOUT +, and the drains of the fourth transistor 202 and the sixth transistor 204 are commonly connected VOUT-.
In the further invention there are 63 phase-shifted states. Can realize 360-degree phase shift, and the stepping precision is 5.625 degrees. By controlling the numbers of the switching transistors of the first amplitude control block 200 and the second amplitude control block 300, amplitude variation of the quadrature signals can be achieved, and vector summation through the vector adder can generate different phase-shifted states. Taking an array unit of the first amplitude control module as an example, when the digital control bit connected with the first inverter is at a high level, the number of unit currents is 1; when the digital control bit connected to the first inverter is low, the number of unit currents is-1. The magnitude control module current number is the vector sum of the array currents. Meanwhile, the positive and negative of the orthogonal signal on the coordinate axis can be easily realized by controlling the positive and negative directions of the switches of the first amplitude control module and the second amplitude control module, and the tangent is complementary with the cotangent function, so that the current numbers of the first amplitude control module and the second amplitude control module are only given when the phase of the first quadrant is changed from 0 degree to 45 degrees, and other phase angles can be easily obtained.
TABLE 1 number of currents and phase angles achieved
The first active inductor module 500 and the second active inductor module 600 respectively include 20 common-gate transistor array units controlled by switches. Each common-gate transistor array unit comprises a seventh transistor 501, an eighth transistor 502, a third inverter 503 and a fourth resistor 504; the input end of the third inverter 503 is connected to the digital control signal, the output end is connected to one end of the fourth resistor 504, and the other end of the fourth resistor 504 is connected to the gates of the seventh transistor 501 and the eighth transistor 502, respectively; the drains of the seventh transistor 501 and the eighth transistor 502 are respectively connected to the power supply voltage, the source of the seventh transistor 501 is connected to the positive terminal of the differential signal input terminal, and the source of the eighth transistor 502 is connected to the negative terminal of the differential signal input terminal. The I path VIN +, VIN-is consistent with the first active inductor module 500, the first amplitude control module 200, and the Q path VQN +, VQN-is consistent with the second active inductor module 600 and the second amplitude control module 300. When a digital control signal connected with a signal input end of the first phase inverter is in a low level, the active inductance module shunts the first amplitude control module and the second amplitude control module, so that the amplitude of an output orthogonal signal of the amplitude control module is changed, and the phase shifting precision is slightly influenced. Compared with a common amplitude calibration unit, the unit simultaneously forms an active inductance and offsets parasitic capacitance. When the active inductance network is conducted, the equivalent circuit of the half-circuit of the phase-trimmed transistor array unit in the system is shown in fig. 2.
Looking up at VIN + labeled in FIG. 2, the resulting input impedance
Wherein R issRepresents the resistance value of the resistor 504, cgsRepresents the gate-source capacitance, g, of the transistor 501mRepresents the transconductance value, V, of transistor 5011Representing the gate-source voltage of transistor 501. At low frequencies, ZoutIs approximately equal to 1/gm(ii) a At high frequency, ZoutIs approximately equal to Rs. In general, 1/g is takenm<Rs. The phase-trimmed transistor array cell thus exhibits inductive characteristics.
When the inductance value is equal to the parasitic capacitance of the array transistor, the parasitic capacitance of the array transistor is represented by resistance which does not change along with frequency, and the technology ensures good broadband matching characteristic of the input end of the amplitude control module and simultaneously realizes fine adjustment of the phase.
The output load matching network 400 includes a first inductor 401, a second inductor 402, a fifth resistor 403, a sixth resistor 404, a third inductor 405, and a fourth inductor 406; the first inductor 401, the fifth resistor 403, the third inductor 405, the second inductor 402, the sixth resistor 404 and the fourth inductor 406 respectively form a differential load; one end of the first inductor 401 and one end of the second inductor 402 are connected to the power supply VDD, and the other ends of the first inductor 401 and the second inductor 402 are respectively connected to one end of the fifth resistor 403 and one end of the sixth resistor 404; the other ends of the fifth resistor 403 and the sixth resistor 404 are respectively and correspondingly connected with output signal ends VoutP and VoutN; the output signal terminals VoutP and VoutN are respectively connected to one ends of the third inductor 405 and the fourth inductor 406, and the other ends of the third inductor 405 and the fourth inductor 406 are respectively and correspondingly connected to VOUT-and VOUT +.
The output terminal adopts the parallel inductance resonance technology, and the current flowing through the load resistor is prolonged due to the effect of the inductor 401/402, so that the charging rate of the load capacitor can be reduced. The effect of the inductor 405/406 is to further delay the flow of current into other networks, thereby increasing system bandwidth. Here we only give the final conclusions:
in the above formula, L represents 401/402/403/404 value, R represents resistance 403/404 value, and ClRepresenting the output load capacitance. k is a reference coefficient, and the maximum flatness delay of the system is influenced by the value of k, and generally k is about 0.5.
In fig. 1, both the NMOS transistor and the PMOS transistor adopt rf transistors supported by a CMOS process, and a gate length selection process can support a minimum size; the inductor adopts a common on-chip plane spiral structure, the resistor is a polysilicon resistor, and the capacitor is an MOM capacitor. Table 2 lists the parameter values for the critical devices in the corresponding embodiment of fig. 1.
TABLE 2 active phase shifter example device parameters
Fig. 3-5 show the simulation results of 64-state phase shift of the active phase shifter according to the present invention; a 64-state phase-shifting root-mean-square error simulation result of the active phase shifter; and phase shifting and amplitude modulation simulation results of the active phase shifter.
Claims (6)
1. A single-ended input differential output radio frequency active phase shifter is characterized in that: the radio frequency active phase shifter comprises a quadrature coupler, a balun network (100), a first amplitude control module (200) and a second amplitude control module (300) which are formed by transistor arrays for respectively controlling amplitudes of two quadrature signals, a first active inductance module (500) and a second active inductance module (600) which are formed by the transistor arrays for respectively carrying out phase fine adjustment, and an output load matching network (400); the input signal is connected with the signal input ends of the quadrature coupler and the balun network (100), and the quadrature differential signal output ends of the quadrature coupler and the balun network (100) are respectively connected with the signal input ends of the first active inductance module (500), the first amplitude control module (200), the second active inductance module (600) and the second amplitude control module (300); the signal output ends of the first active inductance module (500), the first amplitude control module (200), the second active inductance module (600) and the second amplitude control module (300) are respectively connected with the signal input end of the output load matching network (400).
2. The single-ended input differential output radio frequency active phase shifter of claim 1, wherein: the quadrature coupler and balun network (100) comprises a first quadrature coupler (101), a first transformer (102), a second transformer (103), a first transistor (104), a second transistor (105) and a first resistor (106);
the input end of the first orthogonal coupler (101) is connected with a signal RF _ IN, the isolation end is connected with a first resistor (106), the coupling end is connected with one end of a primary coil of a first transformer (102), and the through end is connected with one end of a primary coil of a second transformer (103); the other end of the primary coil of the first transformer (102) is grounded, one end of the secondary coil is connected with VIN +, the other end of the secondary coil is connected with VIN-, and a center tap is connected with a drain electrode of the first transistor (104); the other end of the primary coil of the second transformer (103) is grounded, one end of the secondary coil is connected with VQN +, the other end of the secondary coil is connected with VQN-, and a center tap is connected with the drain electrode of the second transistor (105); the sources of the first transistor (104) and the second transistor (105) are grounded respectively, and the grids are simultaneously connected with a bias voltage Vbias。
3. The single-ended input differential output radio frequency active phase shifter of claim 1, wherein: the first amplitude control module (200) and the second amplitude control module (300) respectively comprise 20 parallel-connected common-gate transistor array units, and each common-gate transistor array unit comprises a third transistor (201), a fourth transistor (202), a fifth transistor (203), a sixth transistor (204), a first inverter (205), a second inverter (206), a second resistor (207) and a third resistor (208);
the sources of the third transistor (201) and the fourth transistor (202) are connected with the positive end of the differential signal input end in common; the sources of the fifth transistor (203) and the sixth transistor (204) are connected with the negative end of the differential signal input end in common; the input end of the first inverter (205) is connected with a digital control signal, the output end of the first inverter is connected with one end of the second resistor (207), the other end of the second resistor (207) is connected with the input end of the second inverter (206), and the input end of the second inverter (206) is simultaneously connected with the grid electrodes of the third transistor (201) and the sixth transistor (204); the output end of the second inverter (206) is connected with one end of a third resistor (208), and the other end of the third resistor (208) is connected with the gates of the fourth transistor (202) and the fifth transistor (203); the third transistor (201) is connected to the drain of the fifth transistor (203) in common, and the fourth transistor (202) is connected to the drain of the sixth transistor (204) in common, VOUT-.
4. The single-ended input differential output radio frequency active phase shifter of claim 1, wherein: the first active inductance module (500) and the second active inductance module (600) respectively comprise 20 switch-controlled common-gate transistor array units; each common-gate transistor array unit comprises a seventh transistor (501), an eighth transistor (502), a third inverter (503) and a fourth resistor (504);
the input end of the third inverter (503) is connected with the digital control signal, the output end of the third inverter is connected with one end of a fourth resistor (504), and the other end of the fourth resistor (504) is respectively connected with the grids of a seventh transistor (501) and an eighth transistor (502); the drains of the seventh transistor (501) and the eighth transistor (502) are connected to the power supply voltage, respectively, the source of the seventh transistor (501) is connected to the positive electrode of the differential signal input terminal, and the source of the eighth transistor (502) is connected to the negative electrode of the differential signal input terminal.
5. The single-ended input differential output radio frequency active phase shifter of claim 4, wherein: the fourth resistor (504) is a radio frequency resistor in the process, and when the output end of the third inverter (503) is at a high level, the seventh transistor (501), the eighth transistor (502), the third inverter (503) and the fourth resistor (504) form an active inductor.
6. The single-ended input differential output radio frequency active phase shifter of claim 1, wherein: the output load matching network (400) comprises a first inductor (401), a second inductor (402), a fifth resistor (403), a sixth resistor (404), a third inductor (405) and a fourth inductor (406); the first inductor (401), the fifth resistor (403), the third inductor (405), the second inductor (402), the sixth resistor (404) and the fourth inductor (406) respectively form a differential load; one ends of the first inductor (401) and the second inductor (402) are simultaneously connected with a power supply VDD, and the other ends of the first inductor and the second inductor are correspondingly connected with one end of the fifth resistor (403) and one end of the sixth resistor (404), respectively; the other ends of the fifth resistor (403) and the sixth resistor (404) are respectively and correspondingly connected with an output signal end VoutP and a output signal end VoutN; the output signal terminals VoutP and VoutN are respectively connected with one ends of the third inductor (405) and the fourth inductor (406), and the other ends of the third inductor (405) and the fourth inductor (406) are respectively and correspondingly connected with VOUT-and VOUT +.
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