CN116598733A - Millimeter wave phase shifter - Google Patents
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- H01P1/18—Phase-shifters
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Abstract
The millimeter wave phase shifter provided by the present disclosure includes: a power distribution network; two paths of matching balun connected to the output end of the power distribution network respectively convert one path of single-ended signals provided by the power distribution network into corresponding paths of differential signals; the two paths of interstage matching balun are respectively used for synthesizing one path of differential signals into a corresponding path of single-ended output signals; two paths of variable gain amplifiers with redundancy bits, wherein each path of variable gain amplifier is connected between a matching balun of a corresponding path and an interstage matching balun and is used for controlling the amplitude of a single-ended output signal of the corresponding path in a mode of adding the redundancy bit with the weight of 1; and the orthogonal signal generating network is connected with the two paths of interstage matching balun output ends and is used for carrying out orthogonal synthesis on the two paths of single-end output signals to obtain radio frequency output signals. The amplitude of the I/Q two-path signal is finely adjusted by reasonably controlling the redundant bit state, so that the amplitude and phase error of the millimeter wave phase shifter are improved.
Description
Technical Field
The present disclosure relates to the field of radio frequency integrated circuits, and in particular, to a millimeter wave phase shifter.
Background
With the increasing demands for bandwidth and data transmission rates in wireless communication and other fields, the use of millimeter wave (30 GHz-300 GHz) technology is considered to be a viable solution to the current problems of microwave communication, such as small bandwidth, low transmission rates, and the like. The millimeter wave frequency band has very rich frequency spectrum resources, and can support a communication system to carry out high data rate transmission and a radar system to carry out high-resolution imaging. Phased array technology, defined as "electronically controlled radioelectromagnetics", provides a good solution for achieving high data rates and high bandwidths. The method is characterized in that a plurality of antennas are arranged at fixed distances, signals are generated at different times, when the waves are overlapped and mutually interfered, the signals are mutually long in one direction and mutually destructive in the other direction, so that the purpose of wave beam shaping is achieved, the output power of the signals is increased, and the range of the wave beam can be increased. Phase shifters are an indispensable module in phased array systems.
Among a plurality of circuit structures capable of realizing the phase shifting function, the phase shifter of the vector interpolation structure is a good choice, and has larger phase shifting precision and phase shifting range. The classical vector interpolation phase shifter consists of a quadrature signal generation network, a I, Q two-path variable gain amplifier and a power synthesis network, and the phase shifting precision of the phase shifter can be adjusted by adjusting the gain gear of the variable gain amplifier, so that the chip area is more compact.
The traditional digital system variable gain amplifier directly calculates the gain gear according to the required phase shifting precision, so that the vector interpolation phase shifter formed by the digital system variable gain amplifier has larger amplitude and phase errors caused by insufficient adjustment capability near the critical position (0 DEG, 90 DEG, 180 DEG and 270 DEG) of four quadrants of a rectangular coordinate system.
The traditional phase shifter structure often adopts a quadrature signal generating network formed by unbalanced transformers, and natural asymmetry exists on a path between two paths of I, Q, so that phase and amplitude errors are deteriorated. The traditional phase shifter connection mode also often adopts the sequence of connecting the quadrature signal generating network, the variable gain amplifier and the power synthesis network in sequence, and the phase error is larger.
Disclosure of Invention
The present disclosure is directed to solving at least one of the technical problems existing in the prior art.
Therefore, the millimeter wave phase shifter based on redundant bit design is provided, so that the problem that a vector interpolation phase shifter formed by the existing digital variable gain amplifier introduces larger amplitude and phase errors in a specific interval is solved. The gain adjusting range of the variable gain amplifier is enlarged by adding the redundant bit group with the same weight as the 1bit MOS tube group into the digital system variable gain amplifier, so that the amplitude and phase errors of the phase shifter are reduced. The millimeter wave phase shifter provided by the present disclosure includes:
the power distribution network is used for dividing the radio frequency input signal into two paths of single-end signals with the same phase;
the power distribution network comprises an I-path matching balun and a Q-path matching balun, wherein the I-path matching balun and the Q-path matching balun are connected to the output end of the power distribution network, the I-path matching balun is used for converting one path of single-ended signals provided by the power distribution network into I-path differential signals, and the Q-path matching balun is used for converting the other path of single-ended signals provided by the power distribution network into Q-path differential signals;
the I-path interstage matching balun and the Q-path interstage matching balun are used for synthesizing the I-path differential signals into I-path single-end output signals, and the Q-path interstage matching balun is used for synthesizing the Q-path differential signals into Q-path single-end output signals;
the variable gain amplifier is connected between the matching balun and used for controlling the amplitude of the single-end output signal of the Q path in a manner of adding the redundancy bit with the weight of 1, and the variable gain amplifier is connected between the matching balun and the matching balun of the Q path and used for controlling the amplitude of the single-end output signal of the Q path in a manner of adding the redundancy bit with the weight of 1; and
the orthogonal signal generating network is connected to the output ends of the I-path interstage matching balun and the Q-path interstage matching balun and is used for carrying out orthogonal synthesis on the I-path single-end output signals and the Q-path single-end output signals to obtain radio frequency output signals.
In some embodiments, each path of the variable gain amplifier is formed by connecting a half-bit weight unit, a redundant bit weight unit and N bit weight units, and n+2 normal phase control bits and n+2 reverse phase control bits are provided in total, where n=log 2 (360/x), x is the required phase shift step, wherein the weights of the normal and reverse phase control bits provided by the half-bit weight unit are respectively 1 and 0, the weights of the normal and reverse phase control bits provided by the redundant bit weight unit are respectively + -1, and the rest n bits are respectivelyThe weight x of the positive and negative phase control bit provided by the weight unit n The relation with the number n of bits is x n ＝±2 n-1 ，n∈[1,N]。
In some embodiments, the redundant bit weight unit and each n bit weight unit are respectively formed by connecting a differential cascode amplifier with a tail current tube and an inverter; the differential cascode amplifier comprises 7 transistors, transistor M 1 And M 2 Forms a group of switching transistors, transistors M 3 And M 4 Constitute another group of switching transistors, transistors M 5 And M 6 Constituting differential pair transistors, transistors M 7 As a tail current tube; wherein the transistor M 7 Is grounded, transistor M 7 Drain terminal of transistor M 5 And transistor M 6 Source terminal of transistor M 7 Is connected with the bias voltage V Bias The method comprises the steps of carrying out a first treatment on the surface of the Transistor M 5 And transistor M 6 The gate ends of the two paths of the matching balun are respectively connected with the differential output ends of the corresponding path of matching balun; transistor M 1 And transistor M 2 Source terminal of (2) and transistor M 5 Drain terminal of transistor M 3 And transistor M 4 Source terminal of (2) and transistor M 6 Drain terminal of transistor M 1 Transistor M 2 Transistor M 3 And transistor M 4 The drain terminal of the transistor M is differentially connected with the differential input terminal of the corresponding one-way interstage matching balun 1 And transistor M 4 The gate terminal of the transistor M is connected with the output terminal of the inverter 2 And transistor M 3 The gate terminal of which is connected to the input terminal of the inverter.
In some embodiments, the transistors are all MOS transistors.
In some embodiments, the half-bit weight unit is formed by connecting a differential cascode amplifier with a tail current tube and an inverter; the differential cascode amplifier comprises 7 transistors, transistor M 1 And M 2 Forms a group of switching transistors, transistors M 3 And M 4 Constitute another group of switching transistors, transistors M 5 And M 6 Constituting differential pair transistors, transistors M 7 As a tail current tube; wherein the transistor M 7 Is grounded, transistor M 7 Drain terminal of transistor M 5 And transistor M 6 Source terminal of transistor M 7 Is connected with the bias voltage V Bias The method comprises the steps of carrying out a first treatment on the surface of the Transistor M 5 And transistor M 6 The gate ends of the two paths of the matching balun are respectively connected with the differential output ends of the corresponding path of matching balun; transistor M 1 And transistor M 2 Source terminal of (2) and transistor M 5 Drain terminal of transistor M 3 And transistor M 4 Source terminal of (2) and transistor M 6 Drain terminal of transistor M 1 And transistor M 4 The drain terminal of the transistor M is differentially connected with the differential input terminal of the corresponding one-way interstage matching balun 2 And M 3 The drain terminal of (2) is connected to the power supply voltage VDD, the transistor M 1 And transistor M 4 The gate terminal of the transistor M is connected with the output terminal of the inverter 2 And transistor M 3 The gate terminal of which is connected to the input terminal of the inverter.
In some embodiments, the transistors are all MOS transistors.
In some embodiments, the quadrature signal generation network includes a transformer whose primary and secondary windings are formed by metal stacking, and paths through which the metals forming the primary and secondary windings of the transformer pass are the same.
In some embodiments, the quadrature signal generating network further includes an isolation resistor and two adjusting capacitors, the input end of the primary coil of the transformer is connected with the output end of the I, Q interstage matching balun, one end of the secondary coil of the transformer is connected with the isolation resistor, the other end of the secondary coil of the transformer is used for outputting a radio frequency output signal, and the two adjusting capacitors are connected between the primary coil and the secondary coil in a bridging mode.
In some embodiments, the primary coil and the secondary coil of the transformer are respectively composed of square metal coils formed by stacking two layers, paths of the metal layers of the primary coil and the secondary coil of the transformer are completely consistent, a 1/2 circumference outer ring and a 1/2 circumference inner ring of the metal coil of the first layer in the primary coil are composed of a first metal, and a 1/2 circumference outer ring and a 1/2 circumference inner ring of the metal coil of the second layer in the primary coil are composed of a second metal; the first metal forms a 1/2 circumference outer ring and a 1/2 circumference inner ring of a first layer metal coil of the secondary coil, and the second metal forms a 1/2 circumference outer ring and a 1/2 circumference inner ring of a second layer metal coil of the secondary coil.
In some embodiments, the first metal employs a 65nm CMOS process self-contained metal layer M9 and the first metal employs a 65nm CMOS process self-contained metal layer M8.
The technical characteristics and beneficial effects of the present disclosure:
1. improving amplitude and phase errors. The gain adjusting range of the variable gain amplifier is enlarged by adding a redundant bit group with the same weight as the 1bit MOS tube group into the digital variable gain amplifier, so that the amplitude and phase errors of the phase shifter are reduced; the unbalanced transformer is changed into a balanced transformer through layout adjustment, so that phase and amplitude errors are improved; by changing the connection order inside the phase shifter, the phase error is improved.
2. Without adding additional power consumption and chip area. The added redundancy bit has weight of 1 in the digital variable gain amplifier, no obvious influence on the overall power consumption, the area of the MOS tube is almost negligible compared with the area of a passive device required by matching, the connection sequence is changed, and the addition of one redundancy bit does not cause the increase of the layout area.
Drawings
Fig. 1 is a schematic circuit diagram of a millimeter wave phase shifter based on redundant bit design according to an embodiment of the present disclosure;
fig. 2 (a) is a schematic circuit diagram of an nth bit weight unit in a millimeter wave phase shifter according to an embodiment of the present disclosure;
fig. 2 (b) is a schematic circuit diagram of a half-bit weight unit in a millimeter wave phase shifter according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a balance transformer in a millimeter wave phase shifter according to an embodiment of the present disclosure;
fig. 4 is a comparison of the amplitude phase error of a vector interpolation phase shifter of an embodiment of the present disclosure with the root mean square value of the amplitude and phase error of a conventional phase shifter using the same 65nm cmos process.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
On the contrary, the application is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the application as defined by the appended claims. Further, in the following detailed description of the present application, certain specific details are set forth in order to provide a better understanding of the present application. The present application will be fully understood by those skilled in the art without the details described herein.
Referring to fig. 1, a millimeter wave phase shifter provided in an embodiment of the present disclosure includes:
power distribution network for RF input signals IN Dividing the signal into two paths of single-end signals with the same phase;
the power distribution network comprises an I-path matching balun and a Q-path matching balun, wherein the I-path matching balun and the Q-path matching balun are connected to the output end of the power distribution network, the I-path matching balun is used for converting one path of single-ended signals provided by the power distribution network into I-path differential signals, and the Q-path matching balun is used for converting the other path of single-ended signals provided by the power distribution network into Q-path differential signals;
the system comprises an I-path interstage matching balun and a Q-path interstage matching balun, wherein the I-path interstage matching balun is used for synthesizing an I-path differential signal into an I-path single-end output signal, and the Q-path interstage matching balun is used for synthesizing a Q-path differential signal into a Q-path single-end output signal;
an I-path variable gain amplifier with a redundancy bit and a Q-path variable gain amplifier, wherein the I-path variable gain amplifier is connected between an I Lu Pipei balun and an I-path interstage matching balun and is used for controlling the amplitude of an I-path single-end output signal in a manner of adding the redundancy bit with the weight of 1, and the Q-path variable gain amplifier is connected between the Q-path matching balun and the Q-path interstage matching balun and is used for controlling the amplitude of a Q-path single-end output signal in a manner of adding the redundancy bit with the weight of 1; and
the quadrature signal generation network is connected to the output ends of the I-path interstage matching balun and the Q-path interstage matching balun and is used for carrying out quadrature synthesis on the I-path Q-path single-end output signals to obtain radio frequency output signals RF OUT 。
In some embodiments, the power distribution network is formed by a 0 ° power divider, which divides the radio frequency input signal RF IN The input end of the 0 degree power divider is connected with the radio frequency input signal, the first output end is connected with the I path matching balun, and the second output end is connected with the Q path matching balun.
In some embodiments, the two paths of I/Q each have a matching balun, each matching balun has a primary coil (L1, L3) and a secondary coil (L2, L4), one end of the primary coil is connected to the output end of the power distribution network, the other end of the primary coil is grounded, two ends of the secondary coil are differentially connected to the non-inverting input end and the inverting input end of a corresponding one of the variable gain amplifiers, and the center tap of the secondary coil is connected to a bias voltage (VB_I, VB_Q) for providing a determined static operating point for the corresponding one of the variable gain amplifiers.
In some embodiments, the two paths of I/Q are provided with one variable gain amplifier, and the variable gain amplifiers of the two paths of I/Q have the same structure, and one path of variable gain amplifier is taken as an example for illustration. The variable gain amplifier is composed of a half bit weight unit (in fig. 1, the half bit weight unit is represented by an upper triangle symbol with 1/0 filled therein), a redundant bit weight unit (in fig. 1, the redundant bit weight unit is represented by an upper triangle symbol with + -1 filled therein and a thickened outer frame), and N N bit weight units (in fig. 1, the rest triangles except the half bit weight unit and the redundant bit weight unit are represented) connected in parallel, and n+2 normal phase control bits and n+2 reverse phase control bits are provided in total, n=log 2 (360/x), z is the required phase shift step, wherein the weights of the normal and reverse phase control bits provided by the half-bit weight units are respectively 1 and 0, and the weights of the normal and reverse phase control bits provided by the redundant bit weight units are respectively + -1 (0 DEG corresponds to normal phase)For positive output, 180 ° corresponding to opposite phase, for negative output), the weights x of the positive and negative phase control bits provided by the rest n-bit weight units n The relation with the number n of bits is x n ＝±2 n-1 ，n∈[1,N]。
Further, each weight unit is formed by connecting a differential cascode amplifier with a tail current tube and an inverter respectively. The redundant bit weight unit and the N bit weight units have the same structure and connection mode, and the N th bit weight unit in the I-way will be described as an example. Referring to fig. 2 (a), the nth bit weight unit includes a differential cascode amplifier composed of 7 MOS transistors and an inverter INV. Of the 7 MOS transistors, transistor M 7 As a tail current tube, transistor M 5 And M 6 Make up differential pair transistor, transistor M 1 ～M 4 Two groups form two groups of switching tubes. Transistor M 7 Is grounded, transistor M 7 Drain terminal of transistor M 5 And M 6 Source terminal of transistor M 7 Is connected with the bias voltage V Bias The method comprises the steps of carrying out a first treatment on the surface of the Transistor M 5 And M 6 Source-terminated transistor M of (1) 7 Drain terminal of transistor M 5 And M 6 The gate terminals of the two transistors are respectively connected with the positive and negative phases of the differential output terminals of the secondary coil (L2 or L4) of the matching balun, namely the secondary coil of the matching balun is taken as a transistor M 5 And M 6 Is provided with a bias voltage VB_I at the gate terminal of the transistor M 5 And M 6 The drain terminals of the two groups of switch tubes are connected with the source terminals of the two groups of switch tubes, in particular, the transistor M 5 Is connected with the drain terminal of the transistor M 1 And M 2 Source terminal of transistor M 6 Is connected with the drain terminal of the transistor M 3 And M 4 Is a source terminal of (2); transistor M 1 And M 2 As a group of switching transistors, transistor M 3 And M 4 As a group of switching transistors, transistor M 1 And M 2 Source terminal of (2) and transistor M 5 Drain terminal of transistor M 3 And M 4 Source terminal of (2) and transistor M 6 Drain terminal of transistor M 1 ～M 4 The drain terminal of (a) is differentially connected to the differential input terminal of the corresponding one-way interstage matching balun, specifically, the transistor M 1 And transistor M 3 The drain terminal of the transistor M is connected with the inverting terminal of the differential input terminal of the corresponding interstage matching balun 2 And transistor M 4 The drain terminal of the transistor M is connected with the positive terminal of the differential input terminal of the corresponding interstage matching balun 1 And M 4 A gate terminal connected to the output terminal of the inverter INV, a transistor M 2 And M 3 The gate terminal of the inverter INV. The half-bit weight unit is constructed to be slightly different from the redundant bit weight unit, but the transistors of the two are connected in a slightly different manner, see FIG. 2 (b), in which the transistor M 7 Is grounded, transistor M 7 Drain terminal of transistor M 5 And M 6 Source terminal of transistor M 7 Is connected with the bias voltage V Bias The method comprises the steps of carrying out a first treatment on the surface of the Transistor M 5 And M 6 Source-terminated transistor M of (1) 7 Drain terminal of transistor M 5 And M 6 The gate terminals of the two circuits are connected with the positive and negative phases of the differential output terminals of the secondary coil (L2 or L4) of the corresponding one-circuit matching balun, namely the secondary coil of the matching balun is taken as a transistor M 5 And M 6 Is provided with a bias voltage VB_I at the gate terminal of the transistor M 5 And M 6 The drain terminals of the two groups of switch tubes are connected with the source terminals of the two groups of switch tubes, in particular, the transistor M 5 Is connected with the drain terminal of the transistor M 1 And M 2 Source terminal of transistor M 6 Is connected with the drain terminal of the transistor M 3 And M 4 Is a source terminal of (2); transistor M 1 And M 2 As a group of switching transistors, transistor M 3 And M 4 As a group of switching transistors, transistor M 1 And M 2 Source terminal of (2) and transistor M 5 Drain terminal of transistor M 3 And M 4 Source terminal of (2) and transistor M 6 Drain terminal of transistor M 1 And M 4 The drain terminal of the transistor M is differentially connected with the differential input terminal of the corresponding interstage matching balun 2 And M 3 The drain terminal of (2) is connected to the power supply voltage VDD, the transistor M 1 And M 4 A gate terminal connected to the output terminal of the inverter INV, a transistor M 2 And M 3 The gate terminal of the inverter INV.
In some embodiments, each of the I/Q paths has an inter-stage matching balun, each of the inter-stage matching balun having a primary coil (L5, L7) and a secondary coil (L6, L8), the input terminals of the primary coils being connected to the differential output terminals of a corresponding one of the variable gain amplifiers, the center tap of the primary coils being connected to a supply voltage VDD to power the variable gain amplifiers, one end of the secondary coil (as the output terminal of the secondary coil) being connected to the input terminal of the quadrature signal generating network, and the other end of the secondary coil being grounded.
In some embodiments, the quadrature signal generating network is composed of a transformer, two regulating capacitors C1 and C2 and an isolation resistor Res, wherein two input ends of a primary coil L10 of the transformer are respectively connected with output ends of secondary coils L6 and L8 of I, Q-path interstage matching balun, one end of a secondary coil L9 of the transformer is connected with the isolation resistor Res, and the other end of the secondary coil L9 is used for outputting a radio frequency output signal RF OUT Two regulating capacitors C1 and C2 are connected across the primary winding L10 and the secondary winding L9.
Further, in order to improve the problem of deterioration of amplitude phase performance due to the difference in resistance loss in the conventional structure, the primary coil L10 and the secondary coil L9 of the transformer in this embodiment are connected in a balanced manner, specifically, the primary coil and the secondary coil of the transformer are formed by stacking metals, and paths through which the metals forming the primary coil and the secondary coil of the transformer pass are the same. As shown in fig. 3, a quadrilateral transformer is taken as an example, wherein a solid line represents a primary coil L10, a broken line represents a secondary coil L9, a thickened portion uses M9 layer metal of a 65nm CMOS process, a thin line portion is M8 layer metal of the 65nm CMOS process, and the primary coil L10 and the secondary coil L9 pass through the identical metal paths.
Embodiments of the present disclosure are described below with reference to the accompanying drawings:
the millimeter wave phase shifter provided by the embodiment of the disclosure has a circuit structure shown in fig. 1, and comprises a power distribution network, two paths of matching balun, two paths of variable gain amplifier with redundancy bits, two paths of interstage matching balun and a quadrature signal generating network which are connected in sequence; wherein:
the power distribution network, in this embodiment,the input end of the power distribution network is connected with the radio frequency input signal RF by adopting a 0-degree power divider formed by a 65nm CMOS process self-contained metal layer M9 IN The differential output ends of the power distribution network are respectively connected with the signal input ends of the matching balun of the I path and the Q path.
In this embodiment, the matching balun is octagonal in shape, the primary coil (L1, L3) of the matching balun is formed by a metal layer M9 of the 65nm CMOS process, and the secondary coil (L2, L4) of the matching balun is formed by a metal layer M8 of the 65nm CMOS process. The primary coils (L1, L3) have no center tap, one end is connected with a power distribution network, the other end is grounded, the secondary coils (L2, L4) are respectively connected with a non-inverting input end and an inverting input end of the I/Q path variable gain amplifier, and the center taps of the secondary coils (L2, L4) provide bias VB_I or VB_Q for the variable gain amplifier.
Variable gain amplifier, in this embodiment, one for each of the I/Q paths, each path being 7 log 2 (360/x)+2]Each MOS transistor and the control signals thereof form a weight unit, seven groups are formed by every 7 transistors, 7 pairs of control signals are formed in total, seven positive control signals are given through positive control bits S+, and the corresponding seven reverse bias S-are used for realizing reverse operation through the inverter INV inside each weight unit. With n (n E [1,5 ]]) For example, seven transistors of a bit, M 1 ，M 2 ，M 3 ，M 4 ，M 5 ，M 6 ，M 7 Are NMOS transistors, are biased in saturation region, and have transistors M 1 ，M 2 ，M 3 ，M 4 Used as a switching tube, transistor M 5 And M 6 Make up differential pair transistor, transistor M 7 As a tail current tube, 7 transistors share a radio frequency guard ring. Transistor M 7 The source end of the pair of the differential pair transistors M is grounded, and the drain end is connected with the differential pair transistor M by M4 layers of metal 5 ，M 6 The source end of the gate is connected with the external bias V by M4 layer metal Bias Serving as gain adjustment. Transistor M 5 ，M 6 M4 layer metal for source terminal and transistor M 7 Drain terminal of transistor M 5 Is connected with transistor M by M4-layer metal 1 ，M 2 Source terminal of transistor M 5 The gate terminal of the variable gain amplifier of the I/Q circuit is connected with the non-inverting input terminal of the variable gain amplifier of the I/Q circuit by M8 layers of metal, and the transistor M 6 Is connected with transistor M by M4-layer metal 3 ，M 4 Source terminal of transistor M 6 The gate end of the (C) is connected with the inverting input end of the variable gain amplifier of the I/Q circuit by M9 layers of metal, and the switch tube M 1 ，M 2 Is connected with transistor M by M4-layer metal at source end 5 Drain terminal of (C), switch tube M 1 ，M 3 The drain terminal of the (B) is connected with the reverse output terminal of the I/Q circuit by M8 layers of metal, and the switch tube M 2 ，M 4 The drain terminal of the (B) is connected with the positive output terminal of the I/Q circuit by M9 layers of metal, and the switch tube M 1 ，M 4 The gate end of the (B) is connected with the output end of the inverter INV by M2-layer metal, and the switch tube M 2 ，M 3 The gate terminal of the inverter INV is connected with the input terminal of the inverter INV by M3 layers of metal, and the input terminal of the inverter INV is connected with the n-th Bit control signal Bitn_I or Bit_Q. The constitution of the other six groups of MOS tubes in each path is the same as that of the fifth bit weight unit. The MOS tube size binary weights are respectively as follows: 0 control bit: 1 (provided by a half bit weight unit), redundancy bits: 1 (provided by the redundant bit weight unit), 1 control bits: 1 (provided by bit 1 weight unit), 2 control bits: 2 (provided by the 2 nd bit weight unit), 3 control bits: 4 (provided by the 3 rd bit weight unit), 4 control bits: 8 (provided by the 4 th bit weight unit), 5 control bits: 16 (provided by the 5 th bit weight element). The size of the MOS transistor with weight 1 is valued as follows: m is M 1 ，M 2 ，M 3 ，M 4 ：4μm/1μm，M 5 ，M 6 ：2μm/1μm，M 7 :1 μm/1 μm; the size of the transistor MOS transistor with weight 2 is as follows: m is M 1 ，M 2 ，M 3 ，M 4 ：8μm/1μm，M 5 ，M 6 ：4μm/1μm，M 7 :2 μm/1 μm; the size of the MOS transistor with weight 4 is taken as follows: m is M 1 ，M 2 ，M 3 ，M 4 ：16μm/1μm，M 5 ，M 6 ：8μm/1μm，M 7 :4 μm/1 μm; the size of the MOS transistor with weight 8 is valued as follows: m is M 1 ，M 2 ，M 3 ，M 4 ：32μm/1μm，M 5 ，M 6 ：16μm/1μm，M 7 :8 μm/1 μm; the size of the MOS transistor with a weight of 16 is given by: m is M 1 ，M 2 ，M 3 ，M 4 ：64μm/1μm，M 5 ，M 6 ：32μm/1μm，M 7 :16 μm/1 μm. All tail current tubes are isolated from the signal wiring by a ground plane formed by metal layers M5 and M6 and through holes between the tail current tubes, and gate ends of all tail current tubes are connected together by M4 layers of metal; all differential pair tubes M 5 The gate terminals of (2) are connected by M8 layers of metal, all M 6 The gate terminals of (2) are connected by M9 layers of metal, all M 1 ，M 4 The output ends of the switching tubes are connected together by M8 layers of metal, all M 2 ，M 3 The output ends of the switching tubes are connected together by M9 layers of metal.
The interstage matching balun has one I/Q path, in this embodiment, the interstage matching balun is octagonal, the primary coil (L5, L7) is composed of M9 layers of metal, and the secondary coil (L6, L8) is composed of M8 layers of metal. The two ends of the primary coil are respectively connected with the positive output end and the negative output end of the variable gain amplifier, the center tap is connected with the power supply voltage VDD to supply power to the variable gain amplifier, one end of the secondary coil is connected with the input end of the orthogonal signal generating network, the other end of the secondary coil is grounded, and the secondary coil has no center tap.
In the present embodiment, the primary coil L9 and the secondary coil L10 in the orthogonal signal generating network are each formed by two stacked regular quadrilateral metal coils, and paths of the respective layers of metal of the primary coil L9 and the secondary coil L10 are completely identical, see fig. 3, and in order to clearly illustrate the specific configuration of the primary coil L9 and the secondary coil L10, fig. 3 illustrates one layer of metal coil of each of the primary coil L9 and the secondary coil L10 in an exploded form, and in actual use, the primary coil L9 and the secondary coil L10 are in stacked relation. Wherein the metal layer M9 of the 65nm CMOS process constitutes the 1/2 circumference outer ring (see thick solid line segment in FIG. 3) and the 1/2 circumference inner ring (see thin solid line segment in FIG. 3) of the upper metal coil (or lower metal coil) in the primary coil L9, and the metal layer M8 of the 65nm CMOS process constitutes the lower metal coil (or upper metal coil) in the primary coil L9Coil) and 1/2 perimeter outer ring and 1/2 perimeter inner ring, and the two ends of the primary coil L9 are connected with the output ends of the I, Q two-path interstage matching balun. The 1/2 circumference outer ring (see thick dotted line in figure 3) and 1/2 circumference inner ring (see thin dotted line in figure 3) of the upper layer metal coil (or lower layer metal coil) in the secondary coil L10 are formed by the metal layer M9 of the 65nm CMOS process, the 1/2 circumference outer ring and 1/2 circumference inner ring of the lower layer metal coil (or upper layer metal coil) in the secondary coil L10 are formed by the metal layer M8 of the 65nm CMOS process, one end of the secondary coil L10 is connected with a matching resistor, and the other end is connected with an output radio frequency output signal RF OUT 。
In the millimeter wave phase shifter based on the redundant bit design provided by the embodiment of the disclosure, the tail current tube of each bias voltage is biased at 0.5V, the bias of the differential pair tube is 1V, the control signal provided when the switching tube is opened is 1.2V, and the control signal provided when the switching tube is closed is 0V.
The working principle of the millimeter wave phase shifter based on the redundant bit design provided by the embodiment of the disclosure is as follows:
after being divided into two paths of signals with equal amplitude and same phase through a 0-degree power distribution network, the signals are converted into differential signals through two paths of self-matching balun, the differential signals pass through a digital variable gain amplifier, the amplitudes of the two paths of signals are adjusted I, Q through adjusting control bits, and the relation between the initial value of the I path control bit and the required phase shift angle theta and the phase shift bit number n is as follows: i-way control bit is 2 n cos θ—1) rounded binary representation, the relationship between the initial value of the Q-way control bit and the required phase shift angle θ and phase shift number n is: q-way control bit is (2) n sin theta-1), the redundant bit does not output a signal at the moment, and due to the influence of parasitic parameters in the layout, the gain phase performance cannot be well achieved by only using the initial control bit, and the gain phase performance can be improved by fine tuning the control bit at the moment, but when the input of the I path or the Q path is about to be 2 at the four quadrant transition positions of 0 DEG, 90 DEG, 180 DEG and 270 DEG n -1, limited regulation capability, redundant bits can output-2, 0 or 2 weight signals as needed, assisting circuit performance optimization. Wherein, when the redundant bits of the I, Q two paths output +1 and-1 signals simultaneously, the redundant bitsThe resulting signal amplitude is 0 and an output of either +2 or-2 may be produced overall when either a +1 or-1 signal is output. And sending the adjusted signals to 0-degree and 90-degree input ends of an orthogonal signal generating network for orthogonal synthesis to generate a phase shifting effect.
Since in order to reduce the resistive losses, in the design of passive components, thicker top layer metal is often used, in the traditional transformer model, the primary coil is drawn with M9 layer metal, the secondary coil is drawn with M8 layer metal, since in the 65-nm CMOS process provided by TSMC company, the thickness of M9 layer metal is 3.4 μm, and the thickness of M8 layer metal is only 0.9 μm, this directly results in that the resistive losses in the primary coil will be smaller than those in the secondary coil, and there is necessarily a natural symmetry problem in the I, Q path, thus deteriorating the amplitude and phase characteristics of the network. In the design, the balance type transformer uses AP layer metal and M7 layer metal for short-distance bridging, so that in each current path, a form of connecting a circle of M9 metal and a circle of M8 layer metal in series with the same length exists. The improved balance transformer has the same path loss of the primary coil and the secondary coil from the physical structure, and solves the problem of deterioration of amplitude phase performance caused by different resistance losses in the traditional structure.
In the layout design of the phase shifter, the balun shifts the phase, so that the variable gain amplifier is not fully ideal, some phase offset can be introduced, the adjusting range of the variable gain amplifier is limited, the phase error of the phase shifter can be relatively large when the phase error is switched between four quadrants, and the deterioration of the phase performance of the phase shifter is caused, therefore, a redundant bit with the weight of 1 is added to the variable gain amplifier, the drain end difference of a switch pair tube is connected to the output end of the amplifier, the adjusting range of the amplifier is changed from-31 to +31 to-32 to +32, and the performance of the phase shifter is optimized under the condition that the circuit power consumption is not increased remarkably.
In this embodiment, a millimeter wave phase shifter based on redundant bit design is prepared by using a 65nm CMOS process (which is a conventional preparation process in the art), and the simulation result is given in fig. 4. Fig. 4 shows a comparison of the root mean square value of the amplitude error and the phase error of the phase shifter before and after the network design using the redundant bit design and balanced quadrature signal generation.
In summary, the present disclosure may improve the amplitude error and the phase error of a phase shifter.
The above examples verify the correctness and effectiveness of the present disclosure. The above description is only a millimeter wave vector interpolation phase shifter circuit designed based on redundancy bits under a specific CMOS process and a specific frequency band, and is not intended to limit the protection scope of the present disclosure.
Claims (10)
1. A millimeter wave phase shifter, comprising:
the power distribution network is used for dividing the radio frequency input signal into two paths of single-end signals with the same phase;
the power distribution network comprises an I-path matching balun and a Q-path matching balun, wherein the I-path matching balun and the Q-path matching balun are connected to the output end of the power distribution network, the I-path matching balun is used for converting one path of single-ended signals provided by the power distribution network into I-path differential signals, and the Q-path matching balun is used for converting the other path of single-ended signals provided by the power distribution network into Q-path differential signals;
the I-path interstage matching balun and the Q-path interstage matching balun are used for synthesizing the I-path differential signals into I-path single-end output signals, and the Q-path interstage matching balun is used for synthesizing the Q-path differential signals into Q-path single-end output signals;
the variable gain amplifier is connected between the matching balun and used for controlling the amplitude of the single-end output signal of the Q path in a manner of adding the redundancy bit with the weight of 1, and the variable gain amplifier is connected between the matching balun and the matching balun of the Q path and used for controlling the amplitude of the single-end output signal of the Q path in a manner of adding the redundancy bit with the weight of 1; and
the orthogonal signal generating network is connected to the output ends of the I-path interstage matching balun and the Q-path interstage matching balun and is used for carrying out orthogonal synthesis on the I-path single-end output signals and the Q-path single-end output signals to obtain radio frequency output signals.
2. The millimeter wave phase shifter of claim 1, wherein each of the variable gain amplifiers is formed by connecting a half bit weight unit, a redundant bit weight unit and N bit weight units, and n+2 normal phase control bits and n+2 reverse phase control bits are provided in total, n=log 2 (360/x), x is the required phase shift step, wherein the weights of the normal and reverse phase control bits provided by the half-bit weight units are respectively 1 and 0, the weights of the normal and reverse phase control bits provided by the redundant bit weight units are respectively + -1, and the weights of the normal and reverse phase control bits provided by the rest n bit weight units are respectively x n The relation with the number n of bits is x n ＝±2 n-1 ，n∈[1,N]。
3. The millimeter wave phase shifter according to claim 2, wherein the redundant bit weight unit and each n-bit weight unit are respectively formed by connecting a differential cascode amplifier with a tail current tube and an inverter; the differential cascode amplifier comprises 7 transistors, transistor M 1 And M 2 Forms a group of switching transistors, transistors M 3 And M 4 Constitute another group of switching transistors, transistors M 5 And M 6 Constituting differential pair transistors, transistors M 7 As a tail current tube; wherein the transistor M 7 Is grounded, transistor M 7 Drain terminal of transistor M 5 And transistor M 6 Source terminal of transistor M 7 Is connected with the bias voltage V Bias The method comprises the steps of carrying out a first treatment on the surface of the Transistor M 5 And transistor M 6 The gate ends of the two paths of the matching balun are respectively connected with the differential output ends of the corresponding path of matching balun; transistor M 1 And transistor M 2 Source terminal of (2) and transistor M 5 Drain terminal of transistor M 3 And transistor M 4 Source terminal of (2) and transistor M 6 Drain terminal of transistor M 1 Transistor M 2 Transistor M 3 And transistor M 4 The drain terminal of the transistor is differentially connected with the differential input terminal of the corresponding one-way interstage matching balunM 1 And transistor M 4 The gate terminal of the transistor M is connected with the output terminal of the inverter 2 And transistor M 3 The gate terminal of which is connected to the input terminal of the inverter.
4. The millimeter wave phase shifter of claim 3, wherein the transistors are MOS transistors.
5. The millimeter wave phase shifter according to claim 2, wherein the half-bit weight unit is formed by connecting a differential cascode amplifier with a tail current tube and an inverter; the differential cascode amplifier comprises 7 transistors, transistor M 1 And M 2 Forms a group of switching transistors, transistors M 3 And M 4 Constitute another group of switching transistors, transistors M 5 And M 6 Constituting differential pair transistors, transistors M 7 As a tail current tube; wherein the transistor M 7 Is grounded, transistor M 7 Drain terminal of transistor M 5 And transistor M 6 Source terminal of transistor M 7 Is connected with the bias voltage V Bias The method comprises the steps of carrying out a first treatment on the surface of the Transistor M 5 And transistor M 6 The gate ends of the two paths of the matching balun are respectively connected with the differential output ends of the corresponding path of matching balun; transistor M 1 And transistor M 2 Source terminal of (2) and transistor M 5 Drain terminal of transistor M 3 And transistor M 4 Source terminal of (2) and transistor M 6 Drain terminal of transistor M 1 And transistor M 4 The drain terminal of the transistor M is differentially connected with the differential input terminal of the corresponding one-way interstage matching balun 2 And M 3 The drain terminal of (2) is connected to the power supply voltage VDD, the transistor M 1 And transistor M 4 The gate terminal of the transistor M is connected with the output terminal of the inverter 2 And transistor M 3 The gate terminal of which is connected to the input terminal of the inverter.
6. The millimeter wave phase shifter of claim 5, wherein the transistors are MOS transistors.
7. The millimeter wave phase shifter according to any one of claims 1 to 6, wherein the orthogonal signal generating network comprises a transformer whose primary coil and secondary coil are formed by metal stacking, and paths through which metals forming the primary coil and secondary coil of the transformer pass are the same.
8. The millimeter wave phase shifter according to claim 7, wherein the quadrature signal generation network further comprises an isolation resistor and two adjusting capacitors, the input end of the primary coil of the transformer is connected with the output ends of the I, Q interstage matching balun, one end of the secondary coil of the transformer is connected with the isolation resistor, the other end of the secondary coil of the transformer is used for outputting a radio frequency output signal, and the two adjusting capacitors are connected across the primary coil and the secondary coil.
9. The millimeter wave phase shifter according to claim 7, wherein the primary coil and the secondary coil of the transformer are each composed of square metal coils formed by stacking two layers, and paths through which the respective layers of metals of the primary coil and the secondary coil of the transformer pass are completely identical, and 1/2-circumference outer ring and 1/2-circumference inner ring of the first layer of metal coil in the primary coil are composed of a first metal, and 1/2-circumference outer ring and 1/2-circumference inner ring of the second layer of metal coil in the primary coil are composed of a second metal; the first metal forms a 1/2 circumference outer ring and a 1/2 circumference inner ring of a first layer metal coil of the secondary coil, and the second metal forms a 1/2 circumference outer ring and a 1/2 circumference inner ring of a second layer metal coil of the secondary coil.
10. The millimeter wave phase shifter of claim 9, wherein the first metal is a 65nm CMOS process self-contained metal layer M9 and the first metal is a 65nm CMOS process self-contained metal layer M8.
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