CN117767913A - Broadband active phase shifter circuit - Google Patents
Broadband active phase shifter circuit Download PDFInfo
- Publication number
- CN117767913A CN117767913A CN202311423357.6A CN202311423357A CN117767913A CN 117767913 A CN117767913 A CN 117767913A CN 202311423357 A CN202311423357 A CN 202311423357A CN 117767913 A CN117767913 A CN 117767913A
- Authority
- CN
- China
- Prior art keywords
- signal
- output
- path
- capacitor
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 82
- 101150110971 CIN7 gene Proteins 0.000 claims description 9
- 101150110298 INV1 gene Proteins 0.000 claims description 9
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 claims description 9
- 238000011161 development Methods 0.000 abstract description 3
- 238000013461 design Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000003780 insertion Methods 0.000 description 3
- 230000037431 insertion Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000306 component Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
The invention discloses a broadband active phase shifter circuit, which comprises an input balun, a quadrature signal generator and a vector modulator, wherein the input balun is connected with the quadrature signal generator; the input balun is used for receiving an externally input single-ended signal, converting the single-ended signal into a differential signal and outputting the differential signal to the quadrature signal generator; the quadrature signal generator is used for receiving the differential signal input by the input balun, generating a quadrature signal with 90-degree phase difference by utilizing the differential signal, and outputting the quadrature signal to the vector modulator; the vector modulator receives the quadrature signal input by the quadrature signal generator, performs polarity selection and gain control on the quadrature signal, and outputs a phase-shifted differential radio frequency signal. The broadband active phase shifter circuit has the advantages of high phase shifting precision, wide working frequency, low cost and high reliability, and can promote the performance of a phased array radar system and promote the development of miniaturization and low cost.
Description
Technical Field
The invention belongs to the technical field of radio frequency integrated circuit design, and relates to a broadband active phase shifter circuit.
Background
In recent years, phased array radars are widely used in the military and civil fields, and phase shifters are core components of the phased array radars, and through proper signal control, signals with adjustable phases can be obtained at output ends. The performance of the phase shifter affects the performance of the entire phased array system, wherein the phase accuracy of the phase shifter directly determines the accuracy of the antenna beam pointing angle, affects the energy transmission efficiency and spatial filtering performance in a communication system, and directly affects the accuracy of target identification in a target tracking radar. At present, the active phase shifter has been widely used in mainstream monolithic phased array T/R chips by virtue of high gain, high precision and wide bandwidth.
With the continuous progress of silicon-based semiconductor technology, particularly the appearance of SiGe BiCMOS technology enables more choices to be made for radio frequency microwave frequency band design circuits, and the SiGe technology combines the advantages of low cost and high integration of the traditional CMOS technology with excellent radio frequency performance of the SiGe technology, so that a phase shifter chip based on the SiGe technology has the characteristics of small size, low cost, high reliability and strong compatibility of digital circuits, and the development of miniaturization and low cost of a phased array system is promoted, so that the phase shifter chip is widely applied to the military and civil fields.
The silicon-based active phase shifter of the current radio frequency band has the advantages of narrow working bandwidth, large phase shifting error and low gain, and how to expand the working bandwidth, improve the phase shifting precision and reduce the loss of devices is a design difficulty and key point of the current phase shifter.
Disclosure of Invention
The invention aims to overcome the defects and provide a broadband active phase shifter circuit which solves the technical problems of narrow working bandwidth, large phase shift error and low gain of the traditional silicon-based active phase shifter.
In order to achieve the above purpose, the present invention provides the following technical solutions:
a broadband active phase shifter circuit comprises an input balun, a quadrature signal generator and a vector modulator;
the input balun is used for receiving an externally input single-ended signal, converting the single-ended signal into a differential signal and outputting the differential signal to the quadrature signal generator;
the quadrature signal generator is used for receiving the differential signal input by the input balun, generating a quadrature signal with 90-degree phase difference by utilizing the differential signal, and outputting the quadrature signal to the vector modulator;
the vector modulator receives the quadrature signal input by the quadrature signal generator, performs polarity selection and gain control on the quadrature signal, and outputs a phase-shifted differential radio frequency signal.
Further, the input balun comprises capacitors C1, C2, C3, C4, C5, C6 and C7 and inductors L1 and L2 which are mutually coupled;
one end of the capacitor C1 is a single-ended signal RFIN input end, and the other end of the capacitor C1 is connected with one end of the capacitor C4 and one end of the inductor L1; the other end of the capacitor C4 and the other end of the inductor L1 are grounded; the inductor L2 is coupled with the inductor L1, one end of the inductor L2 is connected with one end of the capacitor C2 and one end of the capacitor C6, the other end of the inductor L2 is connected with one end of the capacitor C3 and one end of the capacitor C7, and a middle tap of the inductor L2 is grounded through the capacitor C5; the other end of the capacitor C2 is connected with the output end V+, and the other end of the capacitor C3 is connected with the output end V-; the other end of the capacitor C6 and the other end of the capacitor C7 are grounded.
Further, the quadrature signal generator comprises inductances L3, L4, capacitances C8, C9 and resistances R1, R2, R3, R4, R5, R6;
the differential signal output by the output end V+ of the input balun is divided into two paths, one path is output from the end I+ through a capacitor C8 and a resistor R1, and the other path is output from the end Q+ through an inductor L3 and a resistor R3 orange peel; the differential signal output by the output end V-of the input balun is divided into two paths, one path is output from the I-end after passing through a capacitor C9 and a resistor R2, and the other path is output from the Q-end after passing through an inductor L4 and a resistor R4; resistor R5 is connected across output I+ and output Q-, and resistor R6 is connected across output I+ and output Q+.
Further, the vector modulator circuit comprises an I-path VGA array, a Q-path VGA array and an output stage;
the I-path VGA array and the Q-path VGA array are respectively in a structure formed by connecting five Gilbert units with current rudders in parallel;
the single-channel VGA array comprises two groups of digital control input signal ends, two channels of direct current bias input signal ends, two channels of radio frequency differential signal input ends and two channels of differential signal output ends; the output stage comprises NPN triodes Q1 and Q2, inductors L5, L6, L7 and L8, resistors R7 and R8 and capacitors C10 and C11;
the bases of Q1 and Q2 are connected with a direct current bias signal VBIAS3, the emitters of Q1 and Q2 are respectively connected with the positive end and the negative end of two paths of VGA array differential output signals, the collector of Q1 is connected with one end of L5 and one end of R7, the other end of L5 is connected with C10 to be used as the output end of a phase-shifted differential radio frequency signal, and the other end of L5 is connected with L7 at the same time and then connected to a power supply voltage VDD; the collector of Q2 is connected with one end of L6 and one end of R8, the other end of L6 is connected with C11 to be used as the output end of the differential radio frequency signal after phase shifting, the other path is connected with L8 and then connected to the power supply voltage VDD, and the other ends of R6 and R8 are connected with the power supply voltage VDD.
Further, the single VGA array includes NPN transistors Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, inverter INV1, capacitors C12, C13, resistors R9, R10, R11, R12;
the bases of Q3 and Q8 are connected with control signals, as shown in FIG. 4, for the I-path VGA array and the Q-path VGA array, the control signals are VB1 and VB2 respectively; the bases of Q4 and Q7 are connected with control signals VB1, Q3 and Q8 through INV1, and the bases of Q4 and Q7 are the first group of digital control input signal terminals; the bases of Q6 and Q10 are connected with a control signal VB3 and are the second group of digital control input signal ends;
the collectors of Q3 and Q7 are the first path of differential signal output ends; the collectors of Q4 and Q8 are the second path differential signal output ends;
the emitters of Q3 and Q4 are connected to the collector of Q5 and the emitter of Q6, and the emitters of Q7 and Q8 are connected to the collector of Q9 and the emitter of Q10;
one path of the base electrode of the Q5 is connected with an output end I+ and an output end Q+ of the quadrature signal generator (200) through a C12, and is a first path of radio frequency differential signal input end, and the other path of the base electrode of the Q5 is connected with a resistor R9 and then is connected with a direct current bias signal VBIAS1; one path of the base electrode of the Q9 is connected with an output end I-and an output end Q-of the quadrature signal generator (200) through a C13, and is a second path of radio frequency differential signal input end, and the other path of the base electrode of the Q9 is connected with a resistor R11 and then is connected with a direct current bias signal VBIAS1; the other path of the base electrode of the Q5 and the other path of the base electrode of the Q9 are the first path of direct current bias input signal ends;
the emitters of Q5 and Q9 are respectively connected with resistors R10 and R12 and then grounded, and the collectors of Q6 and Q10 are connected with a DC bias signal VBIAS2 to form a second path of DC bias input signal end.
Further, the inductors L1 and L2 adopt a structure that two layers of inductance coils overlap, and the turns of the inner inductance coil and the outer inductance coil are 1:1.
Further, the inductance value of L3 and L4 is 0.34 to 0.54nH (preferably 0.44 nH), the capacitance value of C8 and C9 is 250 to 286fF (preferably 268 fF), the resistance values of R5 and R6 are 90 to 110Ω (preferably 100deg.C), and the resistance values of R1, R2, R3 and R4 are 27 to 33Ω (preferably 31Ω).
Further, the single VGA cell array contains five sets of NPN transistors of lengths 6.6 μm, 3.4 μm, 1.8 μm, 1 μm and 0.6 μm, respectively. Each group of NPN triodes comprises Q3, Q4, Q5, Q6, Q7, Q8, Q9 and Q10, and the lengths of the NPN triodes in each group of NPN triodes are equal.
Further, NPN triodes Q3, Q4, and Q5 constitute Gilbert cell circuits, and Q7, Q8, and Q9 constitute Gilbert cell circuits; q3 and Q8 are turned on when VB1 is high, Q4 and Q7 are turned on when VB1 is low, and Q3 and Q8 are turned on and Q4 and Q7 are turned on, so that the phases of the output radio frequency signals are opposite.
Further, the capacitor C10, the inductor L5 and the inductor L7 form a T-shaped load;
the capacitor C11, the inductor L6 and the inductor L8 constitute a T-type load.
Compared with the prior art, the invention has at least one of the following beneficial effects:
(1) The invention creatively provides a broadband active phase shifter circuit which has the characteristics of high phase shifting precision, wide working frequency, low cost and high reliability, and can promote the performance of a phased array radar system and promote the development of miniaturization and low cost of the phased array radar system;
(2) According to the balun structure of the transformer, the performance parameters such as the coupling coefficient and the insertion loss of the balun are improved by optimizing the geometric parameters of the coil; the two mutually coupled spiral inductors are connected with the ground capacitor in parallel, so that the working bandwidth of the balun is widened; and the intermediate tap of the balun differential end is grounded, so that good amplitude-phase consistency of the balun differential end is ensured.
(3) The R-L-C all-pass filter structure based on charged compensation achieves the effects of improving the isolation between output ports, reducing the influence of load parasitic capacitance on quadrature signal amplitude and phase balance and expanding the working bandwidth of a circuit by designing the value of the compensation resistor;
(4) According to the invention, the Gilbert cell array with the current rudder is designed, and the accurate current gain is obtained by optimizing the size of the transistor, so that the accuracy of the phase shifter is improved; the structural design of the transistor with the current rudder can ensure the constant total current and ensure the consistency of the amplitude of each phase shifting state;
(5) The invention has the function of programmable bias current, and can reduce the power consumption of the system under the condition of ensuring the completion of high-precision phase shifting.
Drawings
FIG. 1 is a schematic diagram of a wideband active phase shifter circuit according to the present invention;
FIG. 2 is a schematic diagram of the input balun circuit of the present invention;
FIG. 3 is a schematic diagram of a circuit structure of the quadrature signal generator of the present invention;
FIG. 4 is a schematic circuit diagram of a vector modulator according to the present invention;
fig. 5 is a schematic circuit configuration of a single VGA of the present invention.
Detailed Description
The features and advantages of the present invention will become more apparent and clear from the following detailed description of the invention.
The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
The invention provides a broadband active phase shifter circuit, which adopts a SiGe BiCMOS process to realize a phase shifting function with high precision and low loss in the whole wave bands of X and Ku.
The invention relates to a broadband active phase shifter circuit, which comprises an input balun for converting a single-ended signal into a differential signal, a quadrature signal generator for generating signals with 90-degree phase difference and a vector modulator for performing polarity selection and gain control on the quadrature signals, wherein the input balun, the quadrature signal generator and the vector modulator are connected in sequence; . The input balun adopts a passive transformer type balun, and has a main structure of two mutually coupled on-chip spiral inductors, and a radio frequency signal can be converted into two paths of differential signals through the input balun; the quadrature signal generator adopts a structure of an R-L-C all-pass filter with charge compensation, and can convert two paths of differential signals into two pairs of mutually orthogonal differential signals; the vector modulator adopts VGA formed by Gilbert cell arrays with current rudders to adjust the gain of vector signals and select the polarity, and finally adds the vector signals to output signals with different phases.
In a specific embodiment, the input balun 100 comprises capacitances C1, C2, C3, C4, C5, C6, C7 and inductances L1, L2 coupled to each other; the quadrature signal generator 200 comprises inductances L3, L4, capacitances C8, C9, resistances R1, R2, R3, R4, R5, R6; the vector modulator 300 circuit comprises an I-path VGA array, a Q-path VGA array and an output stage, wherein the I-path VGA array and the Q-path VGA array are of the same structure formed by connecting five groups of Gilbert units with current rudders in parallel; the single-channel VGA array comprises two groups of digital control input signal ends, two channels of direct current bias input signal ends, two channels of radio frequency differential signal input ends and two channels of differential signal output ends; the output stage comprises NPN triodes Q1 and Q2, inductors L5, L6, L7 and L8, resistors R7 and R8 and capacitors C10 and C11; the single VGA unit comprises NPN triodes Q3, Q4, Q5, Q6, Q7, Q8, Q9 and Q10, an inverter INV1, capacitors C12 and C13 and resistors R9, R10, R11 and R12;
for the input balun 100 circuit, a radio frequency input signal RFIN is input to one end of L1 through C1, L2 and L1 are mutually coupled, a radio frequency differential output signal is output from V+ and V-ends through C2 and C3, a middle tap of L2 is grounded through C5, and C4, C6 and C7 are respectively connected with L1 and L2 in parallel;
for the quadrature signal generator 200 circuit, the input of the radio frequency differential signal from the V+ end is divided into two paths, one path is connected with C8 and R1 and output from the I+ end, the other path is connected with L3 and R3 and output from the Q+ end; the differential radio frequency signal is input from the V-end and divided into two paths, wherein one path is connected with C9 and R2 and output from the I-end, and the other path is connected with L4 and R4 and output from the Q-end; r5 is connected between the output end I+ and the output end Q-, and R6 is connected between the output end I-and the output end Q+;
for the vector modulator 300 circuit, the bases of Q1 and Q2 are connected with a direct current bias signal VBIAS3, the emitters are respectively connected with the positive end and the negative end of two paths of VGA array differential output signals, the collector of Q1 is respectively connected with L5 and R7, one path of the other end of L5 is connected with C10 to serve as a radio frequency signal output end, and the other path of the other end of L5 is connected with L7 to be connected with a power supply voltage VDD; the collector of Q2 is connected with L6 and R8 respectively, one path of the other end of L6 is connected with C10 to be used as a radio frequency signal output end, the other path of the other end of L6 is connected with L8 to be connected with power supply voltage, and the other ends of R6 and R8 are connected with power supply voltage VDD.
In a specific embodiment, the single VGA unit includes NPN triodes Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, an inverter INV1, capacitors C12, C13, resistors R9, R10, R11, R12, bases of Q3 and Q8 are connected to the control signal VB1, bases of Q4 and Q7 are connected to the radio frequency output terminal through INV1, collectors of Q3 and Q7 are connected to the radio frequency output terminal, collectors of Q4 and Q8 are connected to the differential radio frequency output terminal, emitters of Q3 and Q4 are connected to the emitters of Q5 and Q6, emitters of Q7 and Q8 are connected to the emitters of Q9 and Q10, bases of Q5 and Q9 are equally divided, one capacitor is connected to the radio frequency input signal, one resistor is connected to the dc bias signal, emitters of Q5 and Q9 are connected to the resistor ground, and collectors of Q6 and Q10 are connected to the dc bias signal.
In a specific embodiment, the inductors L1 and L2 adopt a structure in which two layers of inductor coils overlap, the top layer thick metal realizes the main part of the inductor coils, the secondary top layer metal connects the inner ring and the outer ring, and the number of turns of the coils is designed to be 1:1.
In a specific embodiment, L3 and L4 have a inductance of 0.44nH, C8 and C9 have a capacitance of 268fF, R5 and R6 have a resistance of 100deg.OMEGA, and R1, R2, R3 and R4 have a resistance of 31Ω.
In a specific embodiment, the single-pass VGA array comprises five sets of NPN transistors having lengths of 6.6 μm, 3.4 μm, 1.8 μm, 1 μm and 0.6 μm, respectively.
Examples:
the present invention will be described in detail with reference to the accompanying drawings.
As shown in fig. 1, the present invention discloses a wideband active phase shifter circuit comprising a passive Shan Zhuaicha balun 100, a quadrature signal generator 200 formed by an RLC all-pass filter, and a vector modulator 300 formed by an array of gilbert cells. The radio frequency signal output by the front-stage circuit is converted into a differential signal I+ and I-through the single-slip balun 100, and then is decomposed into two in-phase components I+ and I-and two quadrature components Q+ and Q-through the quadrature signal generator 200, the vector modulator 300 performs symbol selection and amplitude control on the quadrature signal, and differential signal output of different phases is realized after synthesis. The connection relation of each part is described as follows:
the input end of the input balun 100 is connected with a radio frequency input signal (i.e. single-ended signal), two paths of differential signals V+ and V-are output and are connected to the input end of the quadrature signal generator 200, four paths of mutually orthogonal radio frequency signals I+, I-, Q+ and Q-are output by the quadrature signal generator 200 and are connected to the input end of the vector modulator 300, and the vector modulator 300 finally outputs two paths of phase-shifted differential radio frequency signals under the control of a digital circuit.
As shown in fig. 2, the input balun part circuit provided by the invention adopts a passive transformer type balun, and the specific circuit structure and connection relation are as follows:
the input balun 100 comprises a capacitor C1, a capacitor C2, a capacitor C3, a grounding capacitor C4, a grounding capacitor C5, a grounding capacitor C6, a grounding capacitor C7, an inductor L1 and an inductor L2 which are mutually coupled, wherein one end of the capacitor C1 is connected with an input end RFIN, and the other end is connected with the capacitor C4 and the inductor L1; the other ends of the capacitor C4 and the inductor L1 are grounded; the inductor L2 is coupled with the inductor L1, one end of the inductor L is connected with the capacitor C2 and the capacitor C6, the other end of the inductor L is connected with the capacitor C3 and the capacitor C7, and the middle tap is grounded through the capacitor C5; the other end of the capacitor C2 is connected with the output end V+, and the other end of the capacitor C3 is connected with the output end V-; the other ends of the capacitor C6 and the capacitor C7 are grounded.
The capacitors C1, C2, and C3 are blocking capacitors for preventing dc crosstalk, and the capacitors C4, C5, C6, and C7 are grounding capacitors for resonating with the inductors L1 and L2, so as to widen the working bandwidth. The inductors L1 and L2 are mutually coupled, and the inductor coil overlapped structure is adopted, so that the miniaturization is realized by the multi-turn structural design.
The input balun provided by the invention has the advantages that the insertion loss is less than 2dB in the range of 8-16GHz, and the phase error between differential ports is less than 1.5 degrees.
As shown in fig. 3, the quadrature signal generator circuit provided by the invention adopts an R-L-C all-pass filter structure with charge compensation, and the specific circuit structure and connection relation are as follows:
the quadrature signal generator 200 comprises an inductor L3, an inductor L4, a capacitor C8, a capacitor C9, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5 and a resistor R6, wherein the radio frequency signal is input from a v+ end and divided into two paths, one path is connected with the capacitor C8 and the resistor R1 and output from an i+ end, and the other path is connected with the inductor L3 and the resistor R3 and output from a q+ end; the differential radio frequency signal is input from the V-end and divided into two paths, one path is connected with a capacitor C9 and a resistor R2 and output from the I-end, and the other path is connected with an inductor L4 and a resistor R4 and output from the Q-end; resistor R5 is connected across output I+ and output Q-, and resistor R6 is connected across output I+ and output Q+.
The quadrature signal generator circuit adopts an R-L-C all-pass filter structure, the values of the capacitor C and the inductor L determine the central frequency of the circuit, and the resistors R5 and R6 have the functions of widening the working frequency band and improving the amplitude fluctuation of the quadrature signal at different frequencies. The R-L-C all-pass filter with the traditional structure is sensitive to parasitic capacitance of a load, so that the problem that errors exist in amplitude and phase of an output quadrature signal is caused. According to the invention, the structural design of the compensation resistors R1, R2, R3 and R4 is added to the capacitive and inductive branches, so that the load sensitivity is reduced, the error is eliminated, and the isolation between output ports is improved.
Through design optimization, the value of the inductors L3 and L4 is 0.44nH, the value of the capacitors C8 and C9 is 268fF, the value of the resistors R5 and R6 is 100 omega, and the value of the resistors R1, R2, R3 and R4 is 31 omega.
The quadrature signal generator circuit has the advantages that the phase error is smaller than 4 degrees, the gain imbalance is smaller than 1.5dB, and the insertion loss is smaller than 6dB in the working range of 8-16 GHz.
As shown in fig. 4, the vector modulator circuit provided by the invention comprises an I-path VGA array, a Q-path VGA array and an output stage, wherein the I-path VGA array and the Q-path VGA array both adopt the same structure formed by parallel connection of five Gilbert units with current rudders in different sizes, and the specific circuit structure and connection relation are as follows:
the single-channel VGA array comprises two groups of digital control input signal ends, two channels of direct current bias input signal ends, two channels of radio frequency differential signal input ends and two channels of differential signal output ends; the output stage comprises an NPN triode Q1, an NPN triode Q2, an inductor L5, an inductor L6, an inductor L7, an inductor L8, a resistor R7, a resistor R8, a capacitor C10 and a capacitor C11, wherein the bases of the triode Q1 and the triode Q2 are connected with a direct current bias signal VBIAS3, the emitters are respectively connected with the positive end and the negative end of two paths of VGA array differential output signals, the collector of the triode Q1 is respectively connected with the inductor L5 and the resistor R7, one path of the other end of the inductor L5 is connected with the capacitor C10 to serve as a radio frequency signal output end, and the other path of the triode is connected with the inductor L7 to serve as a power supply voltage VDD; the collector of the triode Q2 is respectively connected with an inductor L6 and a resistor R8, one path of the other end of the inductor L6 is connected with a capacitor C11 to serve as a radio frequency signal output end, and the other path of the other end of the inductor L6 is connected with a power supply voltage; the other ends of the resistor R6 and the resistor R8 are connected with the power supply voltage VDD.
Wherein VB1<4:0> and VB2<4:0> are two paths of Gilbert unit digital control signals, VB3<4:0> and VB4<4:0> are two paths of digital control signals of the current rudders, and VBIAS1 and VBIAS2 are two paths of direct current bias input ends. And the output stage part, NPN triodes Q1 and Q2 are common-base stage amplifying circuits, are used as isolation stages and are mainly used for stabilizing output impedance, so that output matching is facilitated, resistors R7 and R8 are direct-current bias resistors, a capacitor C10 (C11), an inductor L5 (L6) and an inductor L7 (L8) form a T-shaped load, and single-ended output impedance is matched to 50Ω.
VBIAS1 is a variable current bias, and can realize high-low power consumption switching of the amplifying circuit.
The single-channel VGA array comprises five groups of NPN triodes, the lengths of the triodes are designed according to binary weight values, simulation optimization is carried out aiming at parasitic effects, and the optimized lengths are 6.6 mu m, 3.4 mu m, 1.8 mu m, 1 mu m and 0.6 mu m respectively.
As shown in fig. 5, the specific circuit structure and connection relationship of the single VGA unit circuit proposed by the present invention are as follows:
the single VGA unit comprises an NPN triode Q3, an NPN triode Q4, an NPN triode Q5, an NPN triode Q6, an NPN triode Q7, an NPN triode Q8, an NPN triode Q9, an NPN triode Q10, a phase inverter INV1, a capacitor C12, a capacitor C13, a resistor R9, a resistor R10, a resistor R11 and a resistor R12, bases of the triode Q3 and the triode Q8 are connected with a control signal VB1, bases of the triode Q4 and the triode Q7 are connected with a control signal VB1 through the phase inverter INV1, collectors of the triode Q3 and the triode Q7 are connected with a radio frequency output end, collectors of the triode Q4 and the triode Q8 are connected with a differential radio frequency output end, emitters of the triode Q3 and the triode Q4 are connected with an emitter of the triode Q5 and an emitter of the triode Q6, emitters of the triode Q7 and the triode Q8 are connected with an emitter of the triode Q9 and an emitter of the triode Q10, bases of the triode Q5 and the triode Q9 are connected with a bias signal, the capacitor is connected with a path of the collector of the triode Q9, and the collector of the triode Q10 is connected with a bias signal of the triode Q10.
The NPN triodes Q3 (Q7), Q4 (Q8) and Q5 (Q9) form a Gilbert unit circuit, when VB1 is in a high level, Q3 and Q8 are conducted, when VB1 is in a low level, Q4 and Q7 are conducted, phases of output radio frequency signals are opposite, and therefore the function of phase quadrant selection is achieved. Meanwhile, the function of controlling the signal gain is realized by controlling the number of the transistors of the access circuit, so that vector addition is carried out at the output end, and corresponding phase-shifted signals are obtained. NPN triodes Q6 and Q10 are used as current steering tubes, gain is precisely controlled by changing current of an injection circuit, and phase shifting precision of the circuit is improved. Through the integrated digital control circuit on the chip, a redundant state (the redundant state is realized through VB3 in FIG. 5, when VB3 is 1, VBIAS2 current is injected into the circuit, so that gain is changed, the state is increased, errors caused by PVT and the like are reduced), the optimal 128 states are selected, 7-bit phase shifting precision is realized, and the phase shifting resolution is 2.8 degrees.
The broadband active phase shifter can work in a broadband frequency range of 8-16GHz, the phase shifting precision of 7 bits is realized, the phase shifting resolution is 2.8 degrees, the phase error is less than 2.0 degrees, the amplitude error is less than 0.5dB, and the gain is not less than 0dB. The circuit can work in the temperature range of-55 ℃ to 85 ℃, meets the high-precision phase shifting requirement, and has good reliability.
The invention has been described in detail in connection with the specific embodiments and exemplary examples thereof, but such description is not to be construed as limiting the invention. It will be understood by those skilled in the art that various equivalent substitutions, modifications or improvements may be made to the technical solution of the present invention and its embodiments without departing from the spirit and scope of the present invention, and these fall within the scope of the present invention. The scope of the invention is defined by the appended claims.
What is not described in detail in the present specification is a well known technology to those skilled in the art.
Claims (10)
1. A broadband active phase shifter circuit comprising an input balun (100), a quadrature signal generator (200) and a vector modulator (300);
the input balun (100) is used for receiving an externally input single-ended signal, converting the single-ended signal into a differential signal and outputting the differential signal to the quadrature signal generator (200);
the quadrature signal generator (200) is used for receiving the differential signal input by the input balun (100), generating a quadrature signal with 90 degrees phase difference by utilizing the differential signal, and outputting the quadrature signal to the vector modulator (300);
a vector modulator (300) receives the quadrature signal input from the quadrature signal generator (200), performs polarity selection and gain control on the quadrature signal, and outputs a phase-shifted differential RF signal.
2. A broadband active phase shifter circuit according to claim 1, characterized in that the input balun (100) comprises capacitors C1, C2, C3, C4, C5, C6, C7 and mutually coupled inductances L1, L2;
one end of the capacitor C1 is a single-ended signal RFIN input end, and the other end of the capacitor C1 is connected with one end of the capacitor C4 and one end of the inductor L1; the other end of the capacitor C4 and the other end of the inductor L1 are grounded; the inductor L2 is coupled with the inductor L1, one end of the inductor L2 is connected with one end of the capacitor C2 and one end of the capacitor C6, the other end of the inductor L2 is connected with one end of the capacitor C3 and one end of the capacitor C7, and a middle tap of the inductor L2 is grounded through the capacitor C5; the other end of the capacitor C2 is connected with the output end V+, and the other end of the capacitor C3 is connected with the output end V-; the other end of the capacitor C6 and the other end of the capacitor C7 are grounded.
3. A wideband active phase shifter circuit as claimed in claim 2, wherein the quadrature signal generator (200) comprises inductances L3, L4, capacitances C8, C9 and resistances R1, R2, R3, R4, R5, R6;
the differential signal output by the output end V+ of the input balun (100) is divided into two paths, one path is output from the I+ end after passing through a capacitor C8 and a resistor R1, and the other path is output from the Q+ end after passing through an inductor L3 and a resistor R3 orange peel; the differential signal output by the output end V-of the input balun (100) is divided into two paths, one path is output from the I-end after passing through a capacitor C9 and a resistor R2, and the other path is output from the Q-end after passing through an inductor L4 and a resistor R4; resistor R5 is connected across output I+ and output Q-, and resistor R6 is connected across output I+ and output Q+.
4. A wideband active phase shifter circuit as claimed in claim 3, wherein the vector modulator (300) circuit comprises an I-way VGA array, a Q-way VGA array and an output stage;
the I-path VGA array and the Q-path VGA array are respectively in a structure formed by connecting five Gilbert units with current rudders in parallel;
the single-channel VGA array comprises two groups of digital control input signal ends, two channels of direct current bias input signal ends, two channels of radio frequency differential signal input ends and two channels of differential signal output ends; the output stage comprises NPN triodes Q1 and Q2, inductors L5, L6, L7 and L8, resistors R7 and R8 and capacitors C10 and C11;
the bases of Q1 and Q2 are connected with a direct current bias signal VBIAS3, the emitters of Q1 and Q2 are respectively connected with the positive end and the negative end of two paths of VGA array differential output signals, the collector of Q1 is connected with one end of L5 and one end of R7, the other end of L5 is connected with C10 to be used as the output end of a phase-shifted differential radio frequency signal, and the other end of L5 is connected with L7 at the same time and then connected to a power supply voltage VDD; the collector of Q2 is connected with one end of L6 and one end of R8, the other end of L6 is connected with C11 to be used as the output end of the differential radio frequency signal after phase shifting, the other path is connected with L8 and then connected to the power supply voltage VDD, and the other ends of R6 and R8 are connected with the power supply voltage VDD.
5. The broadband active phase shifter circuit according to claim 4, wherein the single VGA array comprises NPN transistors Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, inverter INV1, capacitors C12, C13, resistors R9, R10, R11, R12;
the bases of Q3 and Q8 are connected with control signals, the bases of Q4 and Q7 are connected with control signals VB1 through INV1, and the bases of Q3 and Q8 and the bases of Q4 and Q7 are the first group of digital control input signal terminals; the bases of Q6 and Q10 are connected with a control signal VB3 and are the second group of digital control input signal ends;
the collectors of Q3 and Q7 are the first path of differential signal output ends; the collectors of Q4 and Q8 are the second path differential signal output ends;
the emitters of Q3 and Q4 are connected to the collector of Q5 and the emitter of Q6, and the emitters of Q7 and Q8 are connected to the collector of Q9 and the emitter of Q10;
one path of the base electrode of the Q5 is connected with an output end I+ and an output end Q+ of the quadrature signal generator (200) through a C12, and is a first path of radio frequency differential signal input end, and the other path of the base electrode of the Q5 is connected with a resistor R9 and then is connected with a direct current bias signal VBIAS1; one path of the base electrode of the Q9 is connected with an output end I-and an output end Q-of the quadrature signal generator (200) through a C13, and is a second path of radio frequency differential signal input end, and the other path of the base electrode of the Q9 is connected with a resistor R11 and then is connected with a direct current bias signal VBIAS1; the other path of the base electrode of the Q5 and the other path of the base electrode of the Q9 are the first path of direct current bias input signal ends;
the emitters of Q5 and Q9 are respectively connected with resistors R10 and R12 and then grounded, and the collectors of Q6 and Q10 are connected with a DC bias signal VBIAS2 to form a second path of DC bias input signal end.
6. The broadband active phase shifter circuit of claim 2, wherein the inductors L1 and L2 are in a structure in which two layers of inductor coils overlap, and the number of turns of the inner inductor coil and the outer inductor coil is 1:1.
7. A wideband active phase shifter circuit as claimed in claim 3 wherein L3 and L4 have inductance values of 0.34 to 0.54nh, C8 and C9 have capacitance values of 250 to 284 ff, R5 and R6 have resistance values of 90 to 110 Ω, and R1, R2, R3 and R4 have resistance values of 27 to 34 Ω.
8. The wideband active phase shifter circuit of claim 5, wherein the single array of VGA cells comprises five NPN transistors having lengths of 6.6 μm, 3.4 μm, 1.8 μm, 1 μm, and 0.6 μm, respectively.
9. A wideband active phase shifter circuit as recited in claim 5, wherein NPN transistors Q3, Q4, and Q5 form Gilbert cell circuits, and Q7, Q8, and Q9 form Gilbert cell circuits; q3 and Q8 are turned on when VB1 is high, Q4 and Q7 are turned on when VB1 is low, and Q3 and Q8 are turned on and Q4 and Q7 are turned on, so that the phases of the output radio frequency signals are opposite.
10. A wideband active phase shifter circuit as claimed in claim 5 wherein the capacitor C10, inductor L5 and inductor L7 form a T-load;
the capacitor C11, the inductor L6 and the inductor L8 constitute a T-type load.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311423357.6A CN117767913A (en) | 2023-10-30 | 2023-10-30 | Broadband active phase shifter circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311423357.6A CN117767913A (en) | 2023-10-30 | 2023-10-30 | Broadband active phase shifter circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117767913A true CN117767913A (en) | 2024-03-26 |
Family
ID=90312864
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311423357.6A Pending CN117767913A (en) | 2023-10-30 | 2023-10-30 | Broadband active phase shifter circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117767913A (en) |
-
2023
- 2023-10-30 CN CN202311423357.6A patent/CN117767913A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110212887B (en) | Radio frequency active phase shifter structure | |
| US7526256B2 (en) | Transformer-based multi-band RF front-end architecture | |
| CN110380707B (en) | On-chip vector modulation phase shifter | |
| CN109687839B (en) | Active and passive mixed microwave phase shifter | |
| CN107863949B (en) | X-band 5-phase shifter based on combination of active phase shifter and passive phase shifter | |
| Zhu et al. | A 21 to 30-GHz merged digital-controlled high resolution phase shifter-programmable gain amplifier with orthogonal phase and gain control for 5-G phase array application | |
| EP4080765A1 (en) | Ultra-wideband two-phase phase shifter | |
| WO2017128678A1 (en) | Capacitive load-based ultra wide band constant value phase shifter | |
| CN114070261A (en) | High-precision low-insertion-loss low-additional-phase-shift numerical control attenuator for W wave band | |
| CN110798171B (en) | Hybrid broadband high-precision phase shifter integrated circuit | |
| CN111130488B (en) | Ultra-wideband phase shift circuit | |
| CN116598733A (en) | Millimeter wave phase shifter | |
| Yu et al. | A 60-GHz vector summing phase shifter with digital tunable current-splitting and current-reuse techniques in 90 nm CMOS | |
| CN117767913A (en) | Broadband active phase shifter circuit | |
| CN114499456B (en) | Broadband orthogonal signal generator based on two-stage hybrid | |
| CN114499454A (en) | Silicon-based millimeter wave differential reflection type phase shifter with novel structure | |
| US8275342B2 (en) | Downconversion mixer | |
| CN113783550A (en) | High-precision numerical control phase shifter for K wave band and phase shifting method thereof | |
| Yang et al. | A Dual-Band Vector-Sum Phase Shifter for 28-GHz and 60-GHz Phased Arrays in 65-nm CMOS | |
| CN117081545B (en) | Ultra-wideband digital phase shifter | |
| CN217445328U (en) | Single-ended input differential output radio frequency active phase shifter | |
| CN113810022B (en) | 5-bit vector modulation type phase shifter based on X-type phase inverter | |
| CN221240342U (en) | Ultra-wideband vector modulation phase shifter and phased array system | |
| CN113328728B (en) | High-precision active phase shifter based on time-varying vector synthesis | |
| CN115694423A (en) | 6-bit low-root-mean-square phase error high-linearity active phase shifter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |