JP6474131B2 - Vector synthesis type phase shifter and control method of vector synthesis type phase shifter - Google Patents

Description

  The present invention relates to a vector synthesis type phase shifter that controls the passing phase of a high-frequency signal used for wireless communication and the like, and a control method for the vector synthesis type phase shifter.

In recent years, with the increase in communication capacity in wireless communication systems, the frequency band has become tight in the frequency band of several GHz, and the quasi-millimeter wave band and millimeter wave band that can secure the bandwidth and transmit information at high speed are used. Wireless communication technology is drawing attention.
The radio waves in the quasi-millimeter wave band and the millimeter wave band are highly directional, and communication using a diffracted radio wave cannot be performed like a radio signal of several GHz or less conventionally used in mobile communication. There is also a problem that attenuation during propagation is large. In view of this, a method has been studied in which the directivity of the antenna is increased and the radiation pattern of the antenna of the wireless communication apparatus is controlled using a beamforming technique so that the main beam is directly directed to the target user or apparatus.
As one of the methods for controlling the radiation pattern of the radio wave output from the transmitter of the wireless communication apparatus, the phase of the signal transmitted from each antenna element is controlled by using an array antenna in which a plurality of antennas are arranged. A method of changing the radiation pattern is mentioned.

  As the radio frequency is tight, a full-duplex communication method has been proposed in which a transmission signal and a reception signal are simultaneously transmitted and received using the same frequency channel. In order to use the same frequency channel at the same time, it is necessary to cancel the transmission signal of the signal issued by the terminal itself at the reception part of the terminal itself, and if the leakage from the transmission amplifier is large, the canceller circuit must be performed in the radio frequency band There is. The canceller circuit includes a delay circuit, a variable attenuation circuit, and a phase shifter (see Non-Patent Document 1).

  Analog circuits are often used as phase shifters in the radio frequency band. Monolithic microwave integrated circuits (MMIC) are being developed for miniaturization. A typical example is a reflective phase shifter using a 90-degree hybrid circuit and a variable capacitance element (see Non-Patent Document 2). There are merits such that only one bias is required for phase control and power consumption can be reduced to almost zero, and mounting on an integrated circuit in the microwave and millimeter wave bands is easy. However, when obtaining a continuous phase shift amount of 0 to 360 degrees, there are problems such as a large insertion loss, a large amplitude fluctuation, and a narrow frequency band.

  There has also been proposed a bit phase shifter that discretely controls passing phase shift by switching paths having different line lengths with a switch (see Non-Patent Document 3). In this case, when the phase shift is controlled with a small change amount step, the circuit needs to be multi-staged, and there is a problem that the circuit scale and area when integrated are increased. In addition, there is a problem that a frequency range in which a desired phase amount can be obtained becomes a narrow band.

  In addition, the desired signals are distributed into four, and each of them is given a difference of 0 degrees, 90 degrees, 180 degrees, and 270 degrees, which are orthogonal phase differences, and then the amplitudes of the two signals are adjusted and combined. Thus, there has been proposed a vector synthesis type phase shifter that obtains an arbitrary amount of phase shift between 0 degrees and 360 degrees. (Refer nonpatent literature 4 and nonpatent literature 5.). As described in the literature, a 90-degree hybrid or transmission line is not required, and since it can be composed of transistors, resistors, and capacitors, there is an advantage that the area when mounted on an integrated circuit can be reduced. .

As an example, a circuit of a synthesizer unit used in a conventional vector synthesis type phase shifter is shown in FIG. 5 (see Non-Patent Document 4). Four orthogonal signals (0 degrees, 180 degrees, 90 degrees, and 270 degrees) are input to the gate terminals of the transistors M ₁₂ , M ₂₂ , M ₃₂ , and M ₄₂ . Further, in order to obtain a desired passing phase value in the range of 0 to 360 degrees, the transistors M ₁₁ , M ₂₁ , M ₃₁ , and M ₄₁ are cascode-connected to select a vector to be synthesized.

FIG. 6 shows a circuit of a synthesizer unit used in another conventional vector synthesis type phase shifter (see Non-Patent Document 5). Two orthogonal signals (0 degrees and 90 degrees) are input to the gate terminals of the transistors M ₁ and M ₂ . Gate voltage _V c2i of the transistors _M 1, _{M 2} for adjusting the amplitude of the input _signal, for controlling the _{V c2q.} In order to obtain a desired passing phase value in the range of 0 to 360 degrees, the transistors M ₃ , M ₄ , M ₅ , and M ₆ are cascode-connected to select a vector to be synthesized. A balun is connected to the output terminal side, and a desired passing phase value in the range of 0 to 360 degrees is obtained by shifting 180 degrees.

Zhaojun He, Shihai Shao, Ying Shen, Chaojin Qing, and Youxi Tang, “Performance Analysis of RF Self-interference Cancellation in Full-Duplex Wireless Communications” IEEE WIRELESS COMMUNICATIONS LETTERS, VOL. 3, NO. 4, AUGUST 2014. Jen-Chieh Wu, Ting-Yueh Chin, Sheng-Fuh Chang, and Chia-Chan Chang, “2.45-GHz CMOS Reflection-Type Phase-Shifter MMICs With Minimal Loss Variation Over Quadrants of Phase-Shift Range” IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 56, NO. 10, OCTOBER 2008. Wei-Tsung Li, Yun-Chieh Chiang, Jeng-Han Tsai, Hong-Yuan Yang, Jen-Hao Cheng, and Tian-Wei Huang, “60-GHz 5-bit Phase Shifter With Integrated VGA Phase-Error Compensation” IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 61, NO. 3, MARCH 2013. You Zheng, and Carlos E. Saavedra, “Full 360 ° Vector-Sum Phase-Shifter for Microwave System Applications” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS―I: REGULAR PAPERS, VOL. 57, NO. 4, APRIL 2010. Yan-Yu Huang, Hamhee Jeon, Youngchang Yoon, Wangmyong Woo, Chang-Ho Lee, and J. Stevenson Kenney, “An Ultra-Compact, Linearly-Controlled Variable Phase Shifter Designed With a Novel RC Poly-Phase Filter” IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO. 2, FEBRUARY 2012.

  However, when the configuration of the conventional vector synthesizing phase shifter as shown in FIGS. 5 and 6 is applied to a frequency of a quasi-millimeter wave band or more, a desired phase shift amount is reduced due to the influence of the drain-source capacitance of the transistor. In order to obtain four vector combinations of 0 degree, 90 degrees, 180 degrees, and 270 degrees, the D / U ratio between the vector signal (D) to be passed and the vector signal (U) to be suppressed is not good. There is a problem of becoming sufficient. For this reason, there is a problem that a leakage component of the signal of the vector desired to be suppressed occurs and an error occurs in the phase shift amount desired to be set (see FIG. 3).

  In addition, when the conventional vector composition type phase shifter configuration is applied to frequencies above the quasi-millimeter wave band, the desired amount of phase shift can be obtained due to the influence of the drain-source capacitance and the gate-drain capacitance of the transistor. Therefore, when switching the combination of four vectors of 0 degree, 90 degrees, 180 degrees, and 270 degrees, there is a problem that the ON / OFF ratio cannot be increased as compared with the microwave band. In addition, there is a problem that a large amount of attenuation cannot be obtained even in a transistor that performs amplitude control of a vector to be used. For this reason, there is a problem that a leakage component of the signal of the vector desired to be suppressed occurs and an error occurs in the phase shift amount desired to be set (see FIG. 3).

That is, in the configuration of the conventional vector synthesis type phase shifter, there is a problem that a leakage component of the signal of the vector to be suppressed occurs and an error occurs in the phase shift amount to be set.
The present invention has been made in view of such circumstances, and it is an object of the present invention to provide a highly accurate vector synthesis type phase shifter and a vector synthesis type phase shifter control method that reduce the setting error of the phase shift amount. To do.

One embodiment of the present invention includes a transistor M _n1 , a transistor M _n2 , and a transistor M _n3 (n is an integer from 1 to 4), the transistors M _n1 and M _n2 are cascode-connected, and the source terminal of the transistor M _{n1 Are} connected to the drain terminal of the transistor M _n3 , the source terminals of the transistor M _n3 and the transistor M _n2 are grounded, and the drain terminals of the transistors M ₁₁ , M ₂₁ , M ₃₁ , and M ₄₁ are one of the load and the output A vector composition type phase shifter connected to a terminal and having the other of the loads connected to a drain voltage source, and connected to the gate terminals of the transistors M ₁₂ , M _22, M ₃₂ , M ₄₂ , a series capacitor C ₁ , 0 degrees through _{C 2, C 3, C 4} , 180 degrees, 90 degrees, where having a phase difference of 270 degrees Signal is input, the gate terminal of the transistor _{M 11} and _{M 23,} the gate terminal of the transistor _{M 21} and _{M 13,} the gate terminal of the transistor _{M 31} and _{M 43,} respectively gate terminals of the transistors _{M 41} and _{M 33} a first control voltage for which, to select a vector to synthesize hand, the second control voltage, the third control voltage, the fourth control voltage is input, a gate terminal of the transistor M ₁₂ and M _22, the for each gate terminal of the transistor M ₃₂ and M _42, the fifth control voltage to adjust the amplitude of the output signal is a vector sum phase shifter control voltage of the 6 are input.

Another embodiment of the present invention is a vector sum phase shifter described above, the transistor M ₁₄ to the drain and source terminals are connected between the gate terminal of the transistor M ₁₂ and M _22, the transistor M _And a transistor M ₃₄ having a drain and a source terminal connected between the gate terminals of ₃₂ and M ₄₂ , and a seventh control which is a fixed voltage for each of the gate terminals of the transistors M ₁₄ and M _34. A voltage is input.

One embodiment of the present invention is the above-described vector synthesis type phase shifter, in which the gate lengths of the transistors M ₁₂ , M ₂₂ , M ₃₂ , M ₄₂ , M ₁₄ , and M ₃₄ are the same as the transistor M ₁₂ , The gate length is such that the threshold voltages of M ₂₂ , M ₃₂ , M ₄₂ , M ₁₄ , and M ₃₄ are the same.

Another embodiment of the present invention includes a transistor M _n1 , a transistor M _n2 , and a transistor M _n3 (n is an integer from 1 to 4). The transistors M _n1 and M _n2 are cascode-connected, and the transistor M _n1 The drain terminal of the transistor M _n3 is connected to the source terminal, the source terminals of the transistor M _n3 and the transistor M _n2 are grounded, and the drain terminals of the transistors M ₁₁ , M ₂₁ , M ₃₁ , and M ₄₁ are one of the loads. And a method of controlling a vector synthesizing phase shifter in which the other of the loads is connected to a drain voltage source, to the gate terminals of the transistors M ₁₂ , M _22, M ₃₂ , M ₄₂ , 0 degree through a series capacitor _{C 1, C 2, C 3} , C 4, 180 degrees, 90 degrees, 270 degrees Enter the desired signals having a phase difference, the gate terminal of the transistor _{M 11} and _{M 23,} the gate terminal of the transistor _{M 21} and _{M 13,} the gate terminal of the transistor _{M 31} and _{M 43,} the transistors _{M 41} and _{M 33} A first control voltage, a second control voltage, a third control voltage, and a fourth control voltage for selecting a vector to be combined are input to each of the gate terminals of the transistors M ₁₂ and M _22. a gate terminal of said for each gate terminal of the transistor M ₃₂ and M _42, the fifth control voltage to adjust the amplitude of the output signal, control of the vector sum phase shifter which receives the control voltage of the sixth Is the method.

In one embodiment of the present invention, a drain and a source terminal are connected between the gate terminals of the transistor M _n1 , the transistor M _n2 , the transistor M _n3 (n is an integer from 1 to 4), and the transistors M ₁₂ and M _22. Transistor M ₁₄ , a transistor M ₃₄ having a drain and a source terminal connected between the gate terminals of the transistors M ₃₂ and M ₄₂ , the transistors M _n1 and M _n2 are cascode-connected, and the transistor M _n1 The drain terminal of the transistor M _n3 is connected to the source terminal, the source terminals of the transistor M _n3 and the transistor M _n2 are grounded, and the drain terminals of the transistors M ₁₁ , M ₂₁ , M ₃₁ , and M ₄₁ are one of the loads. And the load connected to the output terminal A method of controlling a vector sum phase shifter other is connected to a drain voltage source, wherein the transistor _{M 12,} the gate terminal of _{M 22, M 32, M 42} , series capacitor _{C 1,} C 2, _{C 3} , 0 degrees through _{C 4,} 180 degrees, 90 degrees, and input a desired signal having a phase difference of 270 degrees, the gate terminal of the transistor _{M 11} and _{M 23,} the gate terminal of the transistor _{M 21} and _{M 13,} A first control voltage, a second control voltage, and a third control for selecting a vector to be combined with respect to the gate terminals of the transistors M ₃₁ and M _{43 and} the gate terminals of the transistors M ₄₁ and M ₃₃ , respectively. voltage, the fourth control voltage input, the gate terminal of the transistor _{M 12} and _{M 22,} the gate terminal of the transistor _{M 32} and _{M 42} Relative respectively, the fifth control voltage to adjust the amplitude of the output signal, a sixth control voltage inputs, to each gate terminal of the transistor M ₁₄ and M _34, is fixed voltage It is a control method of a vector composition type phase shifter which inputs the 7th control voltage.

Another aspect of the present invention is a method for controlling the above-described vector synthesis type phase shifter, in which the gate lengths of the transistors M ₁₂ , M ₂₂ , M ₃₂ , M ₄₂ , M ₁₄ , and M ₃₄ The gate length is such that the threshold voltages of M ₁₂ , M ₂₂ , M ₃₂ , M ₄₂ , M ₁₄ , and M ₃₄ are the same.

  According to the present invention, a high-accuracy vector synthesis type phase shifter with reduced phase shift amount setting error by reducing a leakage component of a vector signal to be suppressed in a vector synthesis type phase shifter in a radio frequency band, and A control method of the vector synthesis type phase shifter can be provided.

It is a block diagram which shows the structure of the vector synthetic | combination type phase shifter in 1st Embodiment of this invention. It is a block diagram which shows the structure of the vector synthetic | combination type phase shifter in 2nd Embodiment of this invention. It is a figure which shows that the leak component of the signal of the vector which it wants to suppress arises, and an error arises in the amount of phase shift to set. It is a figure which shows that a phase setting cannot be performed in the value of the phase obtained by passing only one path | route, by the influence of the leak from another 1 path | route. It is a block diagram which shows the structure of the conventional vector composition type | mold phase shifter. It is a block diagram which shows the structure of the conventional vector composition type | mold phase shifter. It is a figure which shows the result of having simulated the passage gain of the signal (D) to pass through in the vector composition type phase shifter, and the passage gain of the signal (U) to suppress. It is a figure which shows the result of having simulated the change with respect to the passage gain and control voltage _Vc2i of a 0 degree vector signal in a vector synthetic | combination type phase shifter. The case where the vector sum phase shifter in this embodiment, the control voltage _{V c1i, V c1q, / V} c1i, / V c1q, a diagram showing an example of values of _{V fix.}

Hereinafter, the vector synthesis type phase shifter in the embodiment will be described with reference to the drawings.
(First embodiment)
Hereinafter, the vector synthesis type phase shifter in the first embodiment will be described with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of a vector synthesis type phase shifter in the first embodiment of the present invention.

As shown in FIG. 1, the vector synthesis type phase shifter has a total of 12 NMOS transistors including a transistor M _n1 , a transistor M _n2 , and a transistor M _n3 (n is an integer from 1 to 4).
The two transistors M _n1 and M _n2 are cascode-connected, the drain terminal of the transistor M _n3 is connected to the source terminal of the transistor M _n1 , and the source terminals of the transistors M _n3 and M _n2 are grounded.
The drain terminals of the four transistors M ₁₁ , M ₂₁ , M ₃₁ , and M ₄₁ are connected to one of the loads and the output terminal, and the other of the loads is connected to the drain voltage source.
In this vector synthesis type phase shifter, 0 degrees, 180 degrees, and 90 degrees are connected to the gate terminals of the transistors M ₁₂ , M _22, M ₃₂ , and M ₄₂ via series capacitors C ₁ , C ₂ , C ₃ , and C _4. A desired signal having a phase difference of 270 degrees is input.
The gate terminals of the transistors _{M 11} and _{M 23,} the gate terminal of the transistor _{M 21} and _{M 13,} the gate terminal of the transistor _{M 31} and _{M 43,} the respective gate terminals of the transistors _{M 41} and _{M 33,} 0 to 360 degrees Control voltage V _c1i (first control voltage), / V _c1i (second control voltage), V _c1q (third control voltage) for selecting a vector to be combined to obtain a desired passing phase value in the range of Control voltage) / V _c1q (fourth control voltage). For example, control voltages V _c1i , / V _c1i , V _c1q , / V _c1q are input, and two vector signals are selected from 0 degree, 180 degrees, 90 degrees, and 270 degrees, and desired in the range of 0 to 360 degrees The selected vector signal is synthesized (see FIG. 9).
Moreover, (the control voltage of the _fifth) control voltage _{V c2i} for adjusting the gate terminal of the transistor _{M 12} and _{M 22,} the respective gate terminals of the transistors _{M 32} and _{M 42,} the amplitude of the output _{signal, V C2q} ( 6th control voltage) is input. For example, the control voltage _{V c2i,} V c2q is input, 0 degrees, 180 degrees, 90 degrees, the amplitude of the selected two vector signals of 270 degrees is adjusted, the amplitude of the synthesized vector signal is adjusted The

That is, the vector synthesis type phase shifter inputs four orthogonal signals (0 degrees, 180 degrees, 90 degrees, and 270 degrees) to the gate terminals of the transistors M ₁₂ , M ₂₂ , M ₃₂ , and M ₄₂ . And the gate voltage _V c2i of the transistors _{M 12, M 22, M 32} , M 42 for adjusting the amplitude of the output _signal to control the _{V c2q.} In addition, in order to obtain a desired passing phase value in the range of 0 to 360 degrees, a vector to be synthesized is selected. In order to perform this selection, the transistors M ₁₁ , M ₂₁ , M ₃₁ , M ₄₁ and the transistors M ₁₃ , M ₂₃ , M ₃₃ , M ₄₃ are connected and their gate voltages V _c1i , V _c1q , / V _c1i , / V _c1q To control.

Here, for example, a transistor to lower the gate voltage of M ₁₁ drain - to increase the source resistance value, if the attenuating the signal transmitted to the drain side, the drain of the transistor M ₁₃ is raised gate voltage of the transistor M ₁₃ is at the same time - Source By lowering the resistance value, the RF signal is grounded, and the signal passing to the output terminal can be suppressed.
The vector composition type phase shifter in the present embodiment realizes highly accurate phase setting by greatly attenuating the pass gain of a cascode amplifier that amplifies a vector signal to be suppressed when switching vector combinations.

FIG. 7 is a diagram showing a result of simulating the pass gain of the signal (D) to be passed and the pass gain of the signal (U) to be suppressed in the vector synthesis type phase shifter. Here, as an example, the result of a signal of 0 degree is shown as a vector signal (D) to be passed, and a signal of 180 degree is shown as a vector signal (U) to be suppressed.
FIG. 7A shows the result of simulating the pass gain of the signal (D) to be passed and the pass gain of the signal (U) to be suppressed in the conventional vector synthesis type phase shifter shown in FIG.
On the other hand, FIG. 7B is a result of simulating the pass gain of the signal desired to pass and the pass gain of the signal desired to be suppressed in the vector synthesis type phase shifter in the present embodiment.
As shown in FIG. 7B, the vector synthesis type phase shifter in the present embodiment obtains 55 dB in D / U ratio at 10 GHz. As shown in FIG. 7A, the D / U ratio of the conventional vector synthesis type phase shifter is 47 dB at 10 GHz, and it can be seen that the vector synthesis type phase shifter in this embodiment is improved by 8 dB. .

As described above, when the configuration of the vector synthesizing phase shifter of the present embodiment is applied to a frequency of the quasi-millimeter wave band or higher, in order to obtain a desired phase shift amount, 0 degrees, 90 degrees, 180 degrees, and 270 degrees. When switching the combination of the four vectors, by having the transistors M ₁₃ , M ₂₃ , M ₃₃ , M ₄₃ , the D / U ratio between the vector signal (D) to be passed and the vector signal (U) to be suppressed Enough.
As a result, the leakage component of the vector signal to be suppressed can be reduced, and the error in the phase shift amount to be set can be reduced. That is, according to the vector synthesis type phase shifter of the present embodiment, by reducing the leakage component of the vector signal to be suppressed in the vector synthesis type phase shifter in the radio frequency band, the phase shift amount setting error is reduced. It is possible to provide a highly accurate vector synthesis type phase shifter and a method for controlling the vector synthesis type phase shifter.

Further, in the vector synthesis type phase shifter of the present embodiment, even if the transistors M ₁₃ , M ₂₃ , M ₃₃ , and M ₄₃ are added to the conventional vector synthesis type phase shifter, the control voltages are the transistors M ₁₁ , M _21. , M ₃₁ and M ₄₁ operate in a complementary manner, and there is an advantage that the DC current value hardly increases.

(Second Embodiment)
Hereinafter, the vector synthesis type phase shifter in the second embodiment will be described with reference to the drawings.
FIG. 2 is a block diagram showing a configuration of a vector synthesis type phase shifter in the second embodiment of the present invention.

In the vector synthesis type phase shifter of this embodiment shown in FIG. 2, two NMOS transistors M ₁₄ and M ₃₄ are added to the vector synthesis type phase shifter of the first embodiment shown in FIG.
In the vector synthesis type phase shifter of this embodiment, the drains and source terminals of the transistors M ₁₄ and M ₃₄ are connected between the gate terminals of the transistors M ₁₂ and M ₂₂ and M ₃₂ and M ₄₂ , respectively. The gate terminals of the transistors M ₁₄ and M ₃₄ are connected to a fixed voltage V _fix (seventh control voltage).
In _the case of _{V fix} ≒ _{V c2i} (or _{V c2q),} the drain of the transistor _{M 14, M 34} - source resistance value is increased, the impedance becomes high when viewed from the input signal, the signal is output without significant attenuation Is done. On the other hand, if the _{V fix> V c2i} (or _{V c2q),} the drain of the transistor _{M 14, M 34} - source resistance becomes small, 0 and 180 degrees of the input signal and the 90 ° and 270 ° of the input signal, respectively Since they are connected and cancel each other because they are in opposite phases, the signals are attenuated and output.

Therefore, setting the fixed voltage _{V fix} minimum value larger than 0V of _{V c2i} (or _{V c2q),} for example, 1V. In this way, since the drain-source resistance values of the transistors M ₁₄ and M ₃₄ are reduced, the input signals of 0 ° and 180 ° and the input signals of 90 ° and 270 ° are connected, respectively. Since they are in opposite phases, they cancel each other out, so that the attenuation when the gate voltage of the common source transistor of the cascode amplifier that passes the vector signal to be attenuated is lowered can be increased.

In the synthesizer unit used in the conventional vector synthesis type phase shifter shown in FIG. 5, the pass gain is controlled by the gate voltages of the transistors M ₁₂ , M ₂₂ , M ₃₂ , and M ₄₂ , but the frequency is high. Then, even if the gate voltage is 0V, there is a problem that the signal passes through without being greatly attenuated due to the influence of the gate-drain capacitance.
Similarly, the conventional vector synthesizing phase shifter shown in FIG. 6 also controls the pass gain by the gate voltages of the transistors M ₁ and M ₂ , and the gate-drain even if the gate voltage is set to 0 V as the frequency increases. There is a problem that it passes through without being greatly attenuated due to the inter-space capacity.
Therefore, in the conventional vector composition type phase shifter, as shown in FIG. 4, in particular, in the phase value obtained by passing only one path such as 0 °, 90 °, 180 °, and 270 °, the other 1 Phase setting may not be possible due to leakage from the route.

On the other hand, the vector synthesis type phase shifter of the present embodiment compensates for the shortage of attenuation when the gate voltage of the source-grounded transistor of the cascode amplifier that passes the vector signal to be attenuated is passed, so that the relationship of the antiphase Canceling transistors M ₁₄ and M ₃₄ to which a fixed voltage V _fix is input between the gate terminals of the transistors M ₁₂ and M ₂₂ to which two signals are input and between the gate terminals of the transistors M ₃₂ and M ₄₂ are respectively provided. Connecting.

FIG. 8 is a diagram showing the result of simulating changes in the pass gain of the vector signal of 0 degree and the control voltage V _c2i in the vector synthesis type phase shifter. FIG. 8 shows the amplitude control characteristic of a 0 degree vector signal at 10 GHz.
FIG. 8A shows a result of simulating changes in the pass gain of the vector signal of 0 degree and the control voltage V _c2i in the circuit of the conventional vector synthesis type phase shifter shown in FIG. The input is input as I ^{+ in} FIG. 5, and the output is the result calculated from the output in the figure through an ideal DC block.
On the other hand, FIG. 8B is a result of simulating changes in the pass gain of the vector signal of 0 degree and the control voltage V _{c2i in} the vector synthesis type phase shifter of the present embodiment shown in FIG. V _fix was 1 V and the frequency was 10 GHz.
Comparing the ON / OFF ratio when passing (V _c2i = 1.0V) and decaying (V _c2i = 0V), the conventional vector composition type phase shifter is 35 dB as shown in FIG. 8 (a). On the other hand, it can be seen that the vector synthesizing type phase shifter of this embodiment is improved by 43 dB and 8 dB as shown in FIG.

As described above, when the configuration of the vector synthesizing phase shifter of the present embodiment is applied to a frequency of the quasi-millimeter wave band or higher, in order to obtain a desired phase shift amount, 0 degrees, 90 degrees, 180 degrees, and 270 degrees. When switching the combination of the four vectors, by having the transistors M ₁₄ and M ₃₄ , the ON / OFF ratio can be increased compared to the microwave band, and a large amount of attenuation can be obtained even in the transistor that controls the amplitude of the vector to be used. be able to.
As a result, the leakage component of the vector signal to be suppressed can be reduced, and the error in the phase shift amount to be set can be reduced. That is, according to the vector synthesis type phase shifter of the present embodiment, by reducing the leakage component of the vector signal to be suppressed in the vector synthesis type phase shifter in the radio frequency band, the phase shift amount setting error is reduced. It is possible to provide a highly accurate vector synthesis type phase shifter and a method for controlling the vector synthesis type phase shifter.

Further, in the vector synthesis type phase shifter of the present embodiment, transistors M ₁₃ , M ₂₃ , M ₃₃ , and M ₄₃ are added to the conventional vector synthesis type phase shifter as in the vector synthesis type phase shifter of the first embodiment. Even if it is added, the control voltage operates in a complementary manner with the transistors M ₁₁ , M ₂₁ , M ₃₁ , and M ₄₁ , so that the DC current value hardly increases. Further, since the transistors M ₁₄ and M ₃₄ do not consume DC current, the current consumption of the vector synthesis type phase shifter of this embodiment is substantially the same as that of the conventional vector synthesis type phase shifter.

(Third embodiment)
Hereinafter, the vector synthesis type phase shifter in the third embodiment will be described.

The vector composition type phase shifter in the present embodiment is the same as the vector composition type phase shifter in the second embodiment, and the threshold voltages of the transistors M ₁₂ , M ₂₂ , M ₃₂ , M ₄₂ , M ₁₄ , and M ₃₄ are substantially the same. The gate lengths of the transistors M ₁₂ , M ₂₂ , M ₃₂ , M ₄₂ , M ₁₄ , and M ₃₄ are selected so that the same V _th is obtained.
As a result, the value of the voltage V _fix becomes
_{(V c2i,} the minimum value of _{V c2q) <V th <V} fix <(V c2i, the maximum value of _{V c2q) + V th}
It is easy to achieve the relationship represented by the following equation, and the voltage V _fix can be set to a fixed voltage.

_{V c2i,} V c2q is applied to the transistor _{M 12, M 22, M 32} , M 42 as a gate voltage. For example, when an NMOS transistor is set between 0 V and V _th , the value of the mutual conductance gm of the transistors M ₁₂ , M ₂₂ , M ₃₂ , and M ₄₂ decreases, and the signal input from the gate terminal is converted into a drain current. It becomes difficult to output.
On the other hand, in the range from _Vth to the maximum drain voltage (about 1.8 V in a 0.18 um CMOS process or the like), the value of the mutual conductance gm increases, and a signal input from the gate terminal can be taken out as a drain current.
In the vector sum phase shifter in this _{embodiment, V c2i, V c2q} is also applied as the drain and source voltages of the transistors _{M 14, M 34.} The drain in the transistor _{M 14, M 34} - for source potential is the same, the drain current of the direct current does not flow, the control voltage between the control voltage _{V fix} the gate voltage of the transistor _{M 14, M 34 V c2i} , V _c2q can be changed to change the drain-source resistance, thereby providing a variable resistance function.

If the gate voltages V _fix of M ₁₄ and M ₃₄ can be fixed, there is an advantage that an external control function is not required. That is, if the gate voltage V _fix of the canceling transistor can be a fixed voltage, it can be divided from the drain voltage and the like, so that there is an advantage that the control voltage and the external power supply terminal do not increase with respect to the conventional circuit. If the relationship of the above equation is satisfied, the gate voltages V _fix of the transistors M ₁₄ and M ₃₄ can be set to a fixed voltage. FIG. 9 shows examples of values of the control voltages V _c1i , V _c1q , / V _c1i , / V _c1q , and V _fix when a circuit is configured with NMOS transistors.

  According to at least one embodiment described above, a high-accuracy vector in which a setting error of a phase shift amount is reduced by reducing a leakage component of a vector signal to be suppressed in a vector synthesis type phase shifter in a radio frequency band. It is possible to provide a control method for the synthesis type phase shifter and the vector synthesis type phase shifter.

The above-described embodiments are all illustrative of the embodiments of the present invention and are not limited to the embodiments, and the present invention can be implemented in various other variations and modifications. .
For example, in the first to second embodiments, the drain power supply is connected via a load, but this may be constituted by a transistor in addition to a resistor and an inductor. Moreover, you may comprise with a constant current source instead of a voltage source.
In the first to third embodiments, the transistor M is an NMOS transistor, but is not limited thereto. For example, the transistor M may be a PMOS transistor.

M ₁₁ , M ₂₁ , M ₃₁ , M ₄₁ , M ₁₂ , M ₂₂ , M ₃₂ , M ₄₂ , M ₁₃ , M ₂₃ , M ₃₃ , M ₄₃ , M ₁₄ , M ₃₄ ... Transistor, V _c1i , / V _{c1i , V c1q, / V c1q,} V c2i, V c2q, V fix ... control voltage

Claims (4)

n is an integer from 1 to 4, and includes a transistor M _n1 , a transistor M _n2 , a transistor M _n3 , a transistor M ₁₄ , and a transistor M ₃₄ .
The transistors M _n1 and M _n2 are cascode-connected, the drain terminal of the transistor M _n3 is connected to the source terminal of the transistor M _n1 , the source terminals of the transistor M _n3 and the transistor M _n2 are grounded,
The drain terminals of the transistors M ₁₁ , M ₂₁ , M ₃₁ , M ₄₁ are connected to one and output terminals of a load, and the other of the load is connected to a drain voltage source ,
The drain and source terminals of the transistor M ₁₄ is connected between the gate terminals of the transistors M ₁₂ and M _22,
Wherein a drain and a source terminal of the transistor M ₃₄ is the vector sum phase shifter that will be connected between the gate terminals of the transistors M ₃₂ and M _42,
With respect to the gate terminals of the transistors M ₁₂ , M ₂₂ , M ₃₂ , and M _{42, positions} of 0 degrees, 180 degrees, 90 degrees, and 270 degrees are provided via series capacitors C ₁ , C ₂ , C ₃ , and C ₄ , respectively. The desired signal with phase difference is input,
The gate terminals of the transistors _{M 11} and _{M 23,} the gate terminal of the transistor _{M 21} and _{M 13,} the gate terminal of the transistor _{M 31} and _{M 43,} the respective gate terminals of the transistors _{M 41} and _{M 33,} synthesized A first control voltage for selecting a vector, a second control voltage inverted from the first control voltage, a third control voltage, and a fourth control voltage inverted from the third control voltage are input. ,
The gate terminals of the transistors M ₁₂ and M _22, the respective gate terminals of the transistors M ₃₂ and M _42, the fifth control voltage to adjust the amplitude of the output signal, the control voltage of the 6 are inputted,
The transistor M ₁₄ and the respective gate terminals of the M _34, the seventh vector sum phase shifter control voltage are entered in a fixed voltage. Gate length of the transistors _{M 12, M 22, M 32} , M 42, M 14, M 34 , the transistors _{M 12, M 22, M 32} , M 42, M 14, the threshold voltage of _{M 34} are the same The vector synthesis type phase shifter according to claim 1 , wherein n is an integer from 1 to 4, and includes a transistor M _n1 , a transistor M _n2 , a transistor M _n3 , a transistor M ₁₄ , and a transistor M ₃₄ .
The transistors M _n1 and M _n2 are cascode-connected, the drain terminal of the transistor M _n3 is connected to the source terminal of the transistor M _n1 , the source terminals of the transistor M _n3 and the transistor M _n2 are grounded,
The drain terminals of the transistors M ₁₁ , M ₂₁ , M ₃₁ , M ₄₁ are connected to one and output terminals of a load, and the other of the load is connected to a drain voltage source ,
The drain and source terminals of the transistor M ₁₄ is connected between the gate terminals of the transistors M ₁₂ and M _22,
The drain and source terminals of the transistor M ₃₄ is a said transistor M ₃₂ and a control method of the vector sum phase shifter that will be connected between the gate terminals of the M _42,
With respect to the gate terminals of the transistors M ₁₂ , M ₂₂ , M ₃₂ , and M _{42, positions} of 0 degrees, 180 degrees, 90 degrees, and 270 degrees are provided via series capacitors C ₁ , C ₂ , C ₃ , and C ₄ , respectively. Input desired signal with phase difference,
The gate terminals of the transistors _{M 11} and _{M 23,} the gate terminal of the transistor _{M 21} and _{M 13,} the gate terminal of the transistor _{M 31} and _{M 43,} the respective gate terminals of the transistors _{M 41} and _{M 33,} synthesized A first control voltage for selecting a vector, a second control voltage inverted from the first control voltage, a third control voltage, and a fourth control voltage inverted from the third control voltage are input. ,
The gate terminals of the transistors M ₁₂ and M _22, and input to each gate terminal of the transistor M ₃₂ and M _42, the fifth control voltage to adjust the amplitude of the output signal, a control voltage of the sixth,
The relative transistor M ₁₄ and M ₃₄ each gate terminal of the control method of the vector sum phase shifter for inputting a seventh control voltage of a fixed voltage. Gate length of the transistors _{M 12, M 22, M 32} , M 42, M 14, M 34 , the transistors _{M 12, M 22, M 32} , M 42, M 14, the threshold voltage of _{M 34} same The method of controlling a vector composition type phase shifter according to claim 3 , wherein

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