CN113918116A - Flow direction switch type vector adder circuit - Google Patents
Flow direction switch type vector adder circuit Download PDFInfo
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- CN113918116A CN113918116A CN202111276102.2A CN202111276102A CN113918116A CN 113918116 A CN113918116 A CN 113918116A CN 202111276102 A CN202111276102 A CN 202111276102A CN 113918116 A CN113918116 A CN 113918116A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
Abstract
The invention discloses a flow direction switch type vector adder circuit, and belongs to the field of radio frequency integrated circuits. The circuit comprises an input matching circuit, an input transistor, a flow direction change-over switch and an output matching circuit. The vector adder is embedded with a matching network formed by an inductor, an input transistor and a capacitor, so that the chip area is not wasted and a complex matching circuit is not needed, and the problem that power cannot be transmitted due to high-frequency reflection when the circuit is connected with a preceding stage is solved. On one hand, the gain of the circuit can be improved, and the positive and negative of the output gain can be changed through the switching of the switch in the other direction, so that a complex switch network is not designed at a current source end for switching the orthogonal axis direction when an active phase shifter is designed.
Description
Technical Field
The invention belongs to the technical field of radio frequency integrated circuits, and particularly relates to a flow direction switch type vector adder circuit.
Background
The CMOS technology has leaps and bounds under the impetus of cost, integration level, and power consumption. The cut-off frequency of the CMOS transistor can meet the integrated circuit design of a frequency band above several GHz. With the development of 5G phased array technology, the active phase shifter is widely concerned due to flexible design, high phase shifting precision, convenience in calibration and the like. The Vector summation circuit is usually implemented by adopting a common source architecture reported in the article "A24.25-26.65 GHz 6-bit Vector-Sum Phase Shifter in 65nm CMOS". The Vector adder (Vector adder) realized by the implementation mode has no input matching, and the Vector adder adopting the architecture can realize the positive and negative of the gain of the output signal only by controlling 8 switches S1, S2, S1N and S2N through a circuit shown in FIG. 1.
In summary, the vector adder in the prior art has the disadvantages of input matching, complex gain polarity control mode, and large phase-shift parasitic amplitude modulation in the phase shifter design.
Disclosure of Invention
Aiming at the difficulty and the defect of the design aspect of a GHz broadband vector adder circuit in the CMOS process in the prior art, the invention provides a flow direction switching type vector adder circuit which is provided with a flow direction switching switch and has high-performance input and output matching and vector summation in a low-frequency band.
In order to achieve the purpose, the invention adopts the technical scheme that:
a flow direction switch type vector adder circuit comprises 16 transistors and 14 passive devices, wherein the transistors M1I, M2I, M1Q and M2Q form a signal input stage; the transistors M3I, M4I, M5I, M6I, M3Q, M4Q, M5Q, M6Q constitute a flow direction changeover switch and also serve as a cascode gain stage; the transistors M7-M10 form two inverters; the inductors L1I and L2I and the capacitors C1I and C2I form an I-path input matching circuit, and the inductors L1Q and L2Q and the capacitors C1Q and C2Q form a Q-path input matching circuit; the inductors L3I, L3Q, L4I and L4Q and the resistors R1I and R1Q form an output load, and have the functions of output matching and bandwidth extension;
in the I-channel, a differential input signal Vin+,I、Vin-,IFlows from the input stage transistors M1I, M2I to the switches M3I, M4I, M5I, M6I, and finally flows out from Vout +, Vout-; in Q-channel, differential input signal Vin+,Q、Vin-,QFlows from the input stage transistors M1Q, M2Q to the switches M3Q, M4Q, M5Q, M6Q, and finally flows out from Vout +, Vout-.
Further, a radio frequency signal Vin-.IThe grid of the M1I and one end of a capacitor C1I are connected, the other end of the capacitor C1I is connected with the source of the M1I, the source of the M1I is connected with one end of an inductor L1I, the other end of the inductor L1I is connected with an A node, one end of a current source is connected with the A node, and the other end of the current source is connected with the ground; the drain of M1I is connected with the sources of M3I and M4I, the gate of M3I is connected with the gate of M6I, and the switch signal SWT1 is connected at the same time; gate connection switch output signals NSWT1 of M4I, M5I; radio frequency signal Vin+,IThe grid of the M2I and one end of a capacitor C2I are connected, the other end of the capacitor C2I is connected with the source of the M2I, the source of the M2I is connected with one end of an inductor L2I, and the other end of the inductor L2I is connected with an A node; the drain of M2I is connected with the sources of M5I and M6I; the drains of M3I and M5I are connected with a V1 node, and the drains of M4I and M6I are connected with a V2 node;
radio frequency signal Vin-,QThe grid of the M1Q and one end of a capacitor C1Q are connected, the other end of the capacitor C1Q is connected with the source of the M1Q, the source of the M1Q is connected with one end of an inductor L1Q, the other end of the inductor L1Q is connected with a node B, one end of a current source is connected with the node B, and the other end of the current source is connected with the ground; the drain of M1Q is connected with the sources of M3Q and M4Q, the gate of M3Q is connected with the gate of M6Q, and the switch signal SWT2 is connected at the same time; gate connection switch output signals NSWT2 of M4Q, M5Q; radio frequency signal Vin+,QThe grid of the M2Q and one end of a capacitor C2Q are connected, the other end of the capacitor C2Q is connected with the source of the M2Q, the source of the M2Q is connected with one end of an inductor L2Q, and the other end of the inductor L2Q is connected with a node B; the drain of M2Q is connected with the sources of M5Q and M6Q; the drains of M3Q and M5Q are connected with the V1 node,the drains of M4Q and M6Q are connected with the V2 node;
one end of the inductor L4I is connected with a power supply VDD, the other end of the inductor L4I is connected with R1I, the other end of R1I is connected with an inductor L3I, and the other end of the inductor L3I is connected with a V2 node; one end of the inductor L4Q is connected with a power supply VDD, the other end of the inductor L4Q is connected with R1Q, the other end of R1Q is connected with an inductor L3Q, and the other end of the inductor L3Q is connected with a V1 node;
the switch input signal SWT1 is connected with the gates of the transistors M7 and M8, the source of M7 is connected with the power supply VDD, the drain is connected with the drain of M8, and the source of M8 is grounded; the switch input signal SWT2 is connected with the gates of the transistors M9 and M10, the source of M9 is connected with the power supply VDD, the drain is connected with the drain of M10, and the source of M10 is grounded; the drain of M7 is connected to switch output signal NSWT1, and the drain of M9 is connected to switch output signal NSWT 2.
Compared with the prior art, the invention has the following beneficial effects:
1) the circuit realizes input matching, so that a bias electric matching network does not need to be designed for the circuit, the design complexity is reduced on one hand, and the chip area is reduced on the other hand.
2) The circuit of the invention is provided with a flow direction switch which can provide gain, and on the other hand, the gain of the circuit can be changed to be positive or negative, thereby avoiding changing the polarity of the gain by changing the current source access mode in the prior phase shifter design.
3) The invention fully considers the problems of output matching, circuit gain and bandwidth, and has good application effect.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a schematic diagram of a prior art vector adder.
Fig. 2 is a schematic diagram of a flow direction switch-mode vector adder in an embodiment of the present invention.
Fig. 3 shows simulation results of input matching and output matching of the half-equivalent circuit of the flow direction switch type vector adder according to the embodiment of the present invention.
Fig. 4 shows the simulation result of the gain flowing to the half-equivalent circuit of the switching type vector adder according to the embodiment of the present invention.
Detailed Description
The invention is further described with reference to the following figures and detailed description.
Referring to fig. 2, a flow direction switching type vector adder circuit includes an input matching circuit, an input transistor, a flow direction switching switch, and an output matching circuit. The circuit is designed by 16 transistors and 14 passive devices, and the transistors M1I, M2I, M1Q and M2Q form a signal input stage; the transistors M3I, M4I, M5I, M6I, M3Q, M4Q, M5Q, M6Q constitute a flow direction changeover switch and also serve as a cascode gain stage; inductors L1I and L2I and capacitors C1I and C2I form an I-path input matching circuit, a capacitor C1I, an inductor L1I and a transistor M1I form an input impedance matching network, and inductors L1Q and L2Q and capacitors C1Q and C2Q form a Q-path input matching circuit; the inductors L3I, L3Q, L4I, L4Q, resistors R1I and R1Q form an output load, and have the functions of output matching and bandwidth extension; the transistors M7 to M10 constitute two inverters. In the I-channel, a differential input signal Vin+,I、Vin-,IFlows from the input stage transistors M1I, M2I to the switches M3I, M4I, M5I, M6I, and finally flows out from Vout +, Vout-; in Q-channel, differential input signal Vin+,Q、Vin-,QFlows from the input stage transistors M1Q, M2Q to the switches M3Q, M4Q, M5Q, M6Q, and finally flows out from Vout +, Vout-.
The specific connection relationship of these devices is:
radio frequency signal Vin-,IThe grid of the M1I and one end of a capacitor C1I are connected, the other end of the capacitor C1I is connected with the source of the M1I, the source of the M1I is connected with one end of an inductor L1I, the other end of the inductor L1I is connected with a point A, one end of a current source is connected with the point A, and the other end of the current source is connected with the ground; the drain of M1I is connected with the sources of M3I and M4I, the gate of M3I is connected with the gate of M6I, and the switch signal SWT1 is connected at the same time; gate connection switch output signals NSWT1 of M4I, M5I; radio frequency signal Vin+,IThe grid of the M2I and one end of a capacitor C2I are connected, the other end of the capacitor C2I is connected with the source of the M2I, the source of the M2I is connected with one end of an inductor L2I, and the other end of the inductor L2I is connected with a point A; the drain of M2I is connected with the sources of M5I and M6I; the drains of M3I and M5I are connected with V1, and the drains of M4I and M6I are connected with V2.
Radio frequency signal Vin-,QThe grid of the M1Q and one end of a capacitor C1Q are connected, the other end of the capacitor C1Q is connected with the source of the M1Q, the source of the M1Q is connected with one end of an inductor L1Q, the other end of the inductor L1Q is connected with a point B, one end of a current source is connected with the point B, and the other end of the current source is connected with the ground; the drain of M1Q is connected with the sources of M3Q and M4Q, the gate of M3Q is connected with the gate of M6Q, and the switch signal SWT2 is connected at the same time; gate connection switch output signals NSWT2 of M4Q, M5Q; radio frequency signal Vin+,QThe grid of the M2Q is connected, one end of the capacitor C2Q is connected, the other end of the capacitor C2Q is connected with the source of the M2Q, the source of the M2Q is connected with one end of the inductor L2Q, and the other end of the inductor L2Q is connected with a point B; the drain of M2Q is connected with the sources of M5Q and M6Q; the drains of M3Q and M5Q are connected to point V1, and the drains of M4Q and M6Q are connected to point V2.
One end of the inductor L4I is connected with a power supply VDD, the other end of the inductor L4I is connected with R1I, the other end of R1I is connected with an inductor L3I, and the other end of the inductor L3I is connected with V2; inductor L4Q has one end connected to power VDD and the other end connected to R1Q, and the other end of R1Q connected to inductor L3Q and the other end of inductor L3Q connected to point V1.
The switch input signal SWT1 is connected to the gates of transistors M7 and M8, the source of M7 is connected to power VDD, the drain is connected to the drain of M8, and the source of M8 is grounded. The switch input signal SWT2 is connected to the gates of transistors M9 and M10, the source of M9 is connected to power VDD, the drain is connected to the drain of M10, and the source of M10 is grounded. The drain of M7 is connected to switch output signal NSWT1, and the drain of M9 is connected to switch output signal NSWT 2.
In the circuit, when the SWT1 is equal to 1 and the SWT2 is equal to 1, the I-channel gain is positive and the Q-channel gain is positive; when SWT1 is equal to 1 and SWT2 is equal to 0, the I channel gain is positive and the Q channel gain is negative; when SWT1 is 0 and SWT2 is 1, the I channel gain is negative and the Q channel gain is positive; when SWT1 and SWT2 are 0, the I-channel gain is negative and the Q-channel gain is negative.
In fig. 2, both the NMOS and PMOS transistors adopt rf transistors supported by CMOS process, and the gate length selection process can support the minimum size; the inductor adopts a common on-chip plane spiral structure, the resistor is a polysilicon resistor, and the capacitor is an MOM capacitor. Table 1 lists the parameter values for the devices used in the corresponding embodiment of fig. 2.
TABLE 1 flow direction switch type vector adder embodiment device parameters
The input impedance to the switched-mode vector adder can be derived from fig. 2:
where ω denotes the angular frequency, CgsRepresenting the gate capacitance of the input transistor M1I, L representing the value of the inductance L1I, ωTRepresenting the characteristic cut-off frequency of the process.
As can be seen from equation 1, when 1/(ω Cgs) ═ ω L,
input impedance
Zin(jω)＝ωTL (2)
The impedance is real, when ωTAnd when L is 50, the input impedance is matched.
The output end adopts a parallel inductance resonance technology, and the current flowing through the load resistor is prolonged due to the effect of the inductor L4I/L4Q, so that the charging rate of the load capacitor can be accelerated. The effect of the inductor L3I/L3Q further delays the time for current to flow into other networks, thereby increasing system bandwidth.
The value of L3I/L3Q/L4I/L4Q is L:
wherein R represents the value of the resistor R1I/R1Q, ClRepresenting the output load capacitance. k is a reference coefficient, and the maximum flatness delay of the system is influenced by the value of k, and generally k is about 0.5.
The gain of the flow direction switch type vector adder is
AV(jω)＝gm1gm3RO3(jωL3//(R+jωL4)) (4)
The transconductance of the input transistor M3I is gm1The transconductance of M3I is gm3Small signal impedance of RO3，L3Is the value of inductance L3I, L4Representing the value of inductance L4I. Another function introduced to the flow switch is to increase the gain of the circuit, as can be seen from equation (4).
FIG. 3 is a simulation diagram of the gain of the circuit, and it can be seen that the gain of the circuit from 5GHz to 10GHz is about-3 dB, and the gain flatness is 0.7 dB. Figure 4 is an input-output matching simulation curve for this circuit,
in the frequency range of 5 GHz-10 GHz, the input reflection coefficient S11 is smaller than-12 dB, and the output reflection coefficient S22 is smaller than-11.6 dB.
In conclusion, the invention embeds the matching network composed of the inductance, the input transistor and the capacitance in the design of the vector adder, the area of a chip is not wasted to make a complex matching circuit, and the problem that the power cannot be transmitted because of high-frequency reflection when the circuit is connected with a front stage is avoided. The invention introduces the flow direction switch, on one hand, the gain of the circuit can be improved, and on the other hand, the positive and negative of the output gain can be changed through the switching of the switch, and the mode avoids the design of a complex switch network at the current source end for switching the orthogonal axis direction during the design of an active phase device. In addition, the load of the present invention employs a bandwidth extension technique, so that the phase shifter maintains gain flatness over a wide frequency range.
The phase shifter can stably work in a frequency range of 5-10 GHz, keeps-3 dB gain and good input and output matching, and can be used for designing the phase shifter in a phased array system.
Claims (2)
1. A flow direction switch type vector adder circuit is characterized by comprising 16 transistors and 14 passive devices, wherein the transistors M1I, M2I, M1Q and M2Q form a signal input stage; the transistors M3I, M4I, M5I, M6I, M3Q, M4Q, M5Q, M6Q constitute a flow direction changeover switch and also serve as a cascode gain stage; the transistors M7-M10 form two inverters; the inductors L1I and L2I and the capacitors C1I and C2I form an I-path input matching circuit, and the inductors L1Q and L2Q and the capacitors C1Q and C2Q form a Q-path input matching circuit; the inductors L3I, L3Q, L4I and L4Q and the resistors R1I and R1Q form an output load, and have the functions of output matching and bandwidth extension;
in the I-channel, a differential input signal Vin+,I、Vin-,IFlows from the input stage transistors M1I, M2I to the switches M3I, M4I, M5I, M6I, and finally flows out from Vout +, Vout-; in Q-channel, differential input signal Vin+,Q、Vin-,QFlows from the input stage transistors M1Q, M2Q to the switches M3Q, M4Q, M5Q, M6Q, and finally flows out from Vout +, Vout-.
2. A flow direction switching vector adder circuit as claimed in claim 1,
radio frequency signal Vin-.IThe grid of the M1I and one end of a capacitor C1I are connected, the other end of the capacitor C1I is connected with the source of the M1I, the source of the M1I is connected with one end of an inductor L1I, the other end of the inductor L1I is connected with an A node, one end of a current source is connected with the A node, and the other end of the current source is connected with the ground; the drain of M1I is connected with the sources of M3I and M4I, the gate of M3I is connected with the gate of M6I, and the switch signal SWT1 is connected at the same time; gate connection switch output signals NSWT1 of M4I, M5I; radio frequency signal Vin+,IThe grid of the M2I and one end of a capacitor C2I are connected, the other end of the capacitor C2I is connected with the source of the M2I, the source of the M2I is connected with one end of an inductor L2I, and the other end of the inductor L2I is connected with an A node; the drain of M2I is connected with the sources of M5I and M6I; the drains of M3I and M5I are connected with a V1 node, and the drains of M4I and M6I are connected with a V2 node;
radio frequency signal Vin-,QThe grid of the M1Q and one end of a capacitor C1Q are connected, the other end of the capacitor C1Q is connected with the source of the M1Q, the source of the M1Q is connected with one end of an inductor L1Q, the other end of the inductor L1Q is connected with a node B, one end of a current source is connected with the node B, and the other end of the current source is connected with the ground; the drain of M1Q is connected with the sources of M3Q and M4Q, the gate of M3Q is connected with the gate of M6Q, and the switch signal SWT2 is connected at the same time; M4Q, M5Q gatesPole connection switch output signal NSWT 2; radio frequency signal Vin+,QThe grid of the M2Q and one end of a capacitor C2Q are connected, the other end of the capacitor C2Q is connected with the source of the M2Q, the source of the M2Q is connected with one end of an inductor L2Q, and the other end of the inductor L2Q is connected with a node B; the drain of M2Q is connected with the sources of M5Q and M6Q; the drains of M3Q and M5Q are connected with a V1 node, and the drains of M4Q and M6Q are connected with a V2 node;
one end of the inductor L4I is connected with a power supply VDD, the other end of the inductor L4I is connected with R1I, the other end of R1I is connected with an inductor L3I, and the other end of the inductor L3I is connected with a V2 node; one end of the inductor L4Q is connected with a power supply VDD, the other end of the inductor L4Q is connected with R1Q, the other end of R1Q is connected with an inductor L3Q, and the other end of the inductor L3Q is connected with a V1 node;
the switch input signal SWT1 is connected with the gates of the transistors M7 and M8, the source of M7 is connected with the power supply VDD, the drain is connected with the drain of M8, and the source of M8 is grounded; the switch input signal SWT2 is connected with the gates of the transistors M9 and M10, the source of M9 is connected with the power supply VDD, the drain is connected with the drain of M10, and the source of M10 is grounded; the drain of M7 is connected to switch output signal NSWT1, and the drain of M9 is connected to switch output signal NSWT 2.
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| CN202111276102.2A CN113918116A (en) | 2021-10-29 | 2021-10-29 | Flow direction switch type vector adder circuit |
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| CN202111276102.2A CN113918116A (en) | 2021-10-29 | 2021-10-29 | Flow direction switch type vector adder circuit |
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