CN114629470A - High-speed pulse generator and high-speed pulse generating method - Google Patents
High-speed pulse generator and high-speed pulse generating method Download PDFInfo
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- CN114629470A CN114629470A CN202210140888.3A CN202210140888A CN114629470A CN 114629470 A CN114629470 A CN 114629470A CN 202210140888 A CN202210140888 A CN 202210140888A CN 114629470 A CN114629470 A CN 114629470A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/013—Modifications of generator to prevent operation by noise or interference
Abstract
The invention discloses a high-speed pulse generator and a high-speed pulse generating method. The high-speed pulse generator is characterized by comprising an output node P, wherein transistors M1, M2 and M3 are PMOS transistors, and transistors M4, M5 and M6 are NMOS transistors; the source of M1 is connected with the power supply, the gate is connected with the clock signal CK0, and the drain is connected with the drain of M2 and the source of M3; the source of M2 is connected with the power supply, the gate is connected with the clock signal CK90, and the drain is connected with the drain of M1 and the source of M3; the gate of M3 is connected to the data input port, and the drain is connected to the output node P; the source of M4 is connected to ground, the gate is connected to clock signal CK90, and the drain is connected to output node P; m5 has its source connected to ground, gate connected to the data input port, and drain connected to the output node P; m6 has a source connected to ground, a gate connected to the clock signal CK0, and a drain connected to the output node P.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, relates to a high-speed serial communication circuit, and particularly relates to a high-speed pulse generator and a high-speed pulse generating method.
Background
The transmitter data path is constituted by a Pattern Generator (Pattern Generator), a 32:4Serializer (32:4Serializer), a Shift Register (Shift Register), a Retimer (timer), a Pulse Generator (Pulse Generator), and a Driver (Driver), as shown in fig. 1.
The code pattern generator generates 64 paths of parallel data, the parallel data are divided into two paths of 32-bit data, the two paths respectively enter two data paths of MSB (most Significant bit) and LSB (least Significant bit), the circuit structures of the MSB path and the LSB path are the same, and the sizes of the drivers at the last stage are different; in the MSB path, 32-path parallel data is firstly converted into 4-path parallel by a 32:4serializer, each data width is 4UI (UI represents the period of an output signal of a transmitter), then a shift register delays and saves the last two-bit data of each period, so that required data is prepared for a three-tap FFE, and six data with the width of 4UI are sent to a retimer; in a retimer, firstly, according to FFE coefficient setting, selecting four data from six data as tap data and sending the tap data to a later stage, repositioning four paths of data according to a four-phase clock, and spacing adjacent data by 1 UI; the pulse generator receives four paths of data, and selects the data by utilizing clock pulse signals with the width of 1UI generated by adjacent two-phase clocks to generate corresponding data pulse signals; the generated data pulse signal controls a grid electrode of a driving circuit, the driving circuit is also provided with four parallel paths, the four paths of data pulse signals take effect alternately, corresponding data are driven to an output node, the final 4:1 data serialization is completed at a driving stage, the driving stage adopts a current type structure, impedance matching is completed through a 50 ohm resistor, and bandwidth expansion is realized by utilizing an inductor.
4:1 data serialization is realized as shown in fig. 2, the widths of four paths of data transmitted by a preceding stage circuit are all 4UI, and the widths are 4:1, four inputs of a serializer are connected, each path of data is connected with a pulse generator and a driving circuit, and the outputs of the four driving circuits are connected in parallel to form an output node of the whole transmitter; four narrow pulses with the width of 1UI are generated by the four-phase clock through an overlapping relation, each pulse corresponds to one path of data, the corresponding path of data is gated within the effective pulse time with the width of 1UI, and the data is transmitted to an output node; the four paths work alternately to transmit data to the output node in sequence, so that high-speed serial output is formed.
To achieve high speed, low jitter, 4:1 serialization requires a high performance pulse generator. A prior art pulse generator design is shown in fig. 3. In the scheme of fig. 3(a), the CK90 and DI are subjected to combinational logic operation, and the operation result is then subjected to operation with CK0, so that the and logic of three inputs, namely CK0, CK90 and DI, is integrally realized, and an output pulse is generated; the scheme of fig. 3(b) connects three input signals in series on a path, which reduces jitter, but the three-stage series connection results in too low turning speed and is not suitable for ultra-high speed design; the scheme of fig. 3(c) performs and logic on the clock signal and the data signal by means of the transmission gate, thereby reducing jitter, but the transmission gate has poor driving capability and also has the problem of limited speed.
Disclosure of Invention
In view of the problems in the prior art, an object of the present invention is to provide a high-speed pulse generator and a high-speed pulse generating method. The high-speed pulse generator circuit of the invention uses intermediate levels other than 0 and 1 in the pulse generation logic, and uses the intermediate levels to drive the subsequent circuits; meanwhile, the high-speed pulse generator circuit provides a normally-on discharge path, and avoids the high-resistance node from interfering the digital signal in a non-working state.
The technical scheme of the invention is as follows:
a high-speed pulse generator includes an output node P, a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6; wherein M1, M2 and M3 are PMOS, and M4, M5 and M6 are NMOS;
the source of M1 is connected with the power supply, the gate is connected with the clock signal CK0, and the drain is connected with the drain of M2 and the source of M3;
the source of M2 is connected with the power supply, the gate is connected with the clock signal CK90, and the drain is connected with the drain of M1 and the source of M3; the clock signal CK90 is in phase quadrature with the clock signal CK 0;
m3 has a gate connected to the data input port for receiving input data DI and a drain connected to the output node P;
the source of M4 is connected to ground, the gate is connected to clock signal CK90, and the drain is connected to output node P;
m5 has a source connected to ground, a gate connected to the data input port for receiving input data DI, and a drain connected to the output node P;
m6 has a source connected to ground, a gate connected to the clock signal CK0, and a drain connected to the output node P.
Further, the periods of the clock signals CK0 and CK90 are both 4UI, and UI represents the period of the transmitter output signal.
Further, the input data DI is flipped and maintained at 4UI at the falling edge of CK 0.
A high-speed pulse generating method based on the high-speed pulse generator comprises the following steps of:
controlling the input data DI to be 0, CK0 and CK90 to be high level, and the output node P to be discharged to 0;
the CK0 is controlled to be reduced from a high level to a low level, the pre-charging stage is started, the charging path of the M1 and the charging path of the M3 in series are conducted, the discharging path of the M6 is turned off, but the discharging path of the M4 is still conducted, and the voltage of the output node P is raised from 0 to a set value Va;
the CK90 is controlled to be reduced from a high level to a low level, the full charging stage is entered, a series charging path of M2 and M3 is conducted, M4 is turned off, and an output node P is charged to a power supply voltage;
the CK0 is controlled to be raised from a low level to a high level, the M2 and the M3 charge the output node P, the M6 discharges the output node P, and the voltage of the output node P falls back to the set value Va;
the control CK90 rises from low to high again, and the output node P is discharged to 0.
Further, the set value Va is less than or equal to half of the power supply voltage.
The invention has the advantages that:
1) during the pulse forming phase, the output node voltage rises from the intermediate level, and compared with the prior art (rising from 0), the charge quantity needing to be charged is smaller, and the rising speed is faster.
2) Only one stage of logic circuit is arranged from the clock signal to the output node, and the introduced jitter is smaller.
Drawings
Fig. 1 is a transmitter datapath circuit.
FIG. 2 is a 4:1 data serialization implementation process;
(a) is a circuit structure diagram, and (b) is a sequential logic diagram.
FIG. 3 is three prior art pulse generators;
(a) a pulse generator based on a two-stage logic circuit, (b) a pulse generator based on a one-stage logic circuit, and (c) a pulse generator based on a transmission gate circuit.
Fig. 4 is a pulse generator circuit of the present invention.
FIG. 5 is a timing diagram of the operation of the pulse generator circuit of the present invention.
Detailed Description
The invention will be described in further detail with reference to the following drawings, which are given by way of example only for the purpose of illustrating the invention and are not intended to limit the scope of the invention.
The pulse generator circuit of the present invention is shown in fig. 4, and the corresponding operating principle is shown in fig. 5.
As shown in FIG. 4, the transistors M1, M2, M3 of the pulse generator of the present invention are PMOS, and M4, M5, M6 are NMOS; the source of M1 is connected with the power supply, the gate is connected with the clock signal CK0, and the drain is connected with the drain of M2 and the source of M3; the source of M2 is connected with the power supply, the gate is connected with the clock signal CK90, and the drain is connected with the drain of M1 and the source of M3; the source of M3 is connected to the drains of M1 and M2, the gate is connected to the input data DI, and the drain is connected to the output node P; the source of M4 is connected to ground, the gate is connected to clock signal CK90, and the drain is connected to output node P; m5 has its source connected to ground, its gate connected to input data DI, and its drain connected to output node P; the M6 has a source connected to ground, a gate connected to the clock signal CK0, and a drain connected to the output node P.
The pulse generator receives CK0 and CK90 two-phase orthogonal clocks and data DI as input signals, CK0 and CK90 both have a period of 4UI, DI is inverted at a falling edge of CK0 and keeps 4UI, when adjacent two-phase clocks CK0 and CK90 both are low level, the pulse generator intercepts data DI, if DI is 0, a pulse is formed at an output node P, and if DI is 1, the output node P keeps low level and does not form a pulse. The working process is as follows: when the input data DI is 1, M3 is always off, the output node P is discharged to 0 during the non-pulse forming time (CK0 or CK90 is high level, keeping 3UI), and when CK0 and CK90 are both low level (keeping 1UI), the output node P is not charged and keeps low level because M3 is off; when input data DI is equal to 0, M3 is turned on, when CK0 and CK90 are both high (hold 1UI), output node P is discharged to 0, when CK0 first drops to low and CK90 still keeps high, a new pulse generation cycle is entered, a pre-charge stage is entered first, the holding time is 1UI, M1, M3 series charging path is turned on, M6 discharging path is turned off but M4 discharging path is still on, the voltage of output node P is determined by the relative charge-discharge capacity of the two paths, the voltage of output node P is raised from 0 to Va, Va is a value less than half of the power supply voltage by appropriate dimensioning, when CK90 also drops to low, both CK0 and CK90 are low, a full charge stage is entered, the holding time is 1UI, the series charging path of M2, M3 is also turned on, M4 is turned off, and both charging paths are turned off, the output node is charged to the supply voltage, enters the discharge phase when CK0 goes high, has a hold time of 2UI, is charged by M2, M3 and discharged by M6, falls back to Va as well, and when CK90 goes high again, the output node is discharged to 0, waiting for the next falling edge of CK0 to enter the next cycle. When DI is equal to 1, the M6 tube provides a normally-on discharge path to prevent the output node from becoming a high impedance state.
The pulse generator keeps a low level and generates no pulse when the data DI is 1, and generates one positive pulse when both CK0 and CK90 are low when the data DI is 0. The generated pulse signal does not keep 0 level but rises to a value lower than half of the power supply voltage within the time of one UI before and after, the voltage value is lower than the turn-on voltage of the transistor, the transistor of the subsequent driving circuit is not turned on, and therefore the output signal of the transmitter is not disturbed, which is logically equivalent to 0, and a narrow pulse signal of 1UI valid and 3UI invalid is still generated.
According to the scheme, before the real pulse is generated, the voltage of the output node P is raised by a certain amplitude, so that the difference value of the voltage which is charged and raised when the real pulse reaches the power supply voltage is reduced, namely the rising time is shortened, and the pulse forming speed is improved. In addition, only one logic circuit is arranged between CK0/90 and the pulse output by the output node P, and the introduced jitter is the minimum in all schemes.
Although specific embodiments of the invention have been disclosed for purposes of illustration, and for purposes of aiding in the understanding of the contents of the invention and its implementation, those skilled in the art will appreciate that: various substitutions, changes and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims (6)
1. A high-speed pulse generator includes an output node P, a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6; wherein M1, M2 and M3 are PMOS, and M4, M5 and M6 are NMOS;
the source of M1 is connected with the power supply, the gate is connected with the clock signal CK0, and the drain is connected with the drain of M2 and the source of M3;
the source of M2 is connected with the power supply, the gate is connected with the clock signal CK90, and the drain is connected with the drain of M1 and the source of M3; the clock signal CK90 is in phase quadrature with the clock signal CK 0;
m3 has a gate connected to the data input port for receiving input data DI and a drain connected to the output node P;
the source of M4 is connected to ground, the gate is connected to clock signal CK90, and the drain is connected to output node P;
m5 has a source connected to ground, a gate connected to the data input port for receiving input data DI, and a drain connected to the output node P;
m6 has a source connected to ground, a gate connected to the clock signal CK0, and a drain connected to the output node P.
2. The high-speed pulse generator according to claim 1, wherein the periods of the clock signals CK0, CK90 are both 4UI, UI representing the period of the transmitter output signal.
3. The high-speed pulse generator according to claim 2, wherein the input data DI is flipped and held at 4UI at falling edge CK 0.
4. A high-speed pulse generating method based on the high-speed pulse generator according to claim 1, wherein each pulse is generated by the steps of:
controlling the input data DI to be 0, CK0 and CK90 to be high level, and the output node P to be discharged to 0;
the CK0 is controlled to be reduced from a high level to a low level, the pre-charging stage is started, the charging path of the M1 and the charging path of the M3 in series are conducted, the discharging path of the M6 is turned off, but the discharging path of the M4 is still conducted, and the voltage of the output node P is raised from 0 to a set value Va;
the CK90 is controlled to be lowered from a high level to a low level, the full-charge stage is entered, a series-connection charging path of M2 and M3 is conducted, M4 is turned off, and an output node P is charged to a power supply voltage;
the CK0 is controlled to be raised from a low level to a high level, the M2 and the M3 charge the output node P, the M6 discharges the output node P, and the voltage of the output node P falls back to the set value Va;
the control CK90 rises from low level to high level again, and the output node P is discharged to 0.
5. The method of claim 4, wherein the set value Va is less than or equal to half of a supply voltage.
6. The method of claim 4, wherein the clock signals CK0 and CK90 each have a period of 4UI, UI representing the period of the transmitter output signal.
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| CN202210140888.3A CN114629470A (en) | 2022-02-16 | 2022-02-16 | High-speed pulse generator and high-speed pulse generating method |
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| CN1332520A (en) * | 2000-04-04 | 2002-01-23 | 夏普株式会社 | Pulse generator for static clock |
| US20140152363A1 (en) * | 2012-11-30 | 2014-06-05 | National Chiao Tung University | Pulse-based flip flop |
| CN104218921A (en) * | 2013-05-30 | 2014-12-17 | 长春迪派斯科技有限公司 | Method and device for super-high-speed pulse signal generator |
| CN104935302A (en) * | 2014-03-17 | 2015-09-23 | 瑞昱半导体股份有限公司 | DC voltage generation circuit and pulse generation circuit thereof |
| EP3190703A1 (en) * | 2016-01-11 | 2017-07-12 | Semiconductor Manufacturing International Corporation (Shanghai) | D flip-flop and signal driving method |
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2022
- 2022-02-16 CN CN202210140888.3A patent/CN114629470A/en active Pending
Patent Citations (5)
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| CN1332520A (en) * | 2000-04-04 | 2002-01-23 | 夏普株式会社 | Pulse generator for static clock |
| US20140152363A1 (en) * | 2012-11-30 | 2014-06-05 | National Chiao Tung University | Pulse-based flip flop |
| CN104218921A (en) * | 2013-05-30 | 2014-12-17 | 长春迪派斯科技有限公司 | Method and device for super-high-speed pulse signal generator |
| CN104935302A (en) * | 2014-03-17 | 2015-09-23 | 瑞昱半导体股份有限公司 | DC voltage generation circuit and pulse generation circuit thereof |
| EP3190703A1 (en) * | 2016-01-11 | 2017-07-12 | Semiconductor Manufacturing International Corporation (Shanghai) | D flip-flop and signal driving method |
Non-Patent Citations (4)
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