JP2012234088A - Driving circuit and display device with the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a driving circuit capable of reducing peak current.SOLUTION: A driving circuit comprises: a level shift part 13 for shifting a voltage level of digital data with a plurality of bits and supplying the digital data to a plurality of gradation signal lines; a D/A conversion circuit 15 for outputting a gradation voltage according to the digital data supplied to the plurality of gradation signal lines as analog data; a plurality of switching circuits SWC1-SWCn provided respectively on the plurality of gradation signal lines between the level shift part 13 and the D/A conversion circuit 15; and a timing control circuit 21 for outputting a control signal for controlling a change from OFF to ON of at least one of the plurality of switching circuits SWC1-SWCn at a timing different from other switching circuits.

Description

  The present invention relates to a drive circuit and a display device including the same, and more particularly to a drive circuit suitable for reducing peak current and a display device including the drive circuit.

  In recent years, with the increase in resolution and color tone of display devices, driver ICs (display device drive circuits) have increased in output and gradation. As driver ICs increase in output and gradation, the number of level shifters supplied to the D / A conversion circuit by shifting the amplitude voltage level of the gradation signal, which is a digital signal, from a low voltage to a high voltage increases. To do.

  Here, when the voltage level of the output signal of the level shifter changes from the low level to the high level or from the high level to the low level, the charge / discharge current and the through current are passed from the level shifter to the D / A conversion circuit with the peak immediately after the change. Flowing. When the number of level shifters increases and the voltage levels of the output signals of the plurality of level shifters simultaneously change from the low level to the high level or from the high level to the low level, a peak immediately after the change is taken as a peak, and the D / A The charge / discharge current and the through-current flow through the conversion circuit all at once, and the peak current of the power supply wiring including the GND that supplies power to a plurality of level shifters in common increases (hereinafter, simply “the peak current of the level shifter (group) increases) "Sometimes it says" Specifically, when the output signal of the level shifter changes from the low level to the high level, a charge / discharge current (part of the operating current) flows through the power supply line having a potential higher than GND, and when the output signal changes from the high level to the low level, the GND power supply line Charge / discharge current (part of operating current) flows. The through current is generated in both cases of the output change, and the same current flows in both the GND line and the high-potential power line. As a result, there have been problems such as the occurrence of circuit malfunction due to electromagnetic interference (EMI) and power supply noise.

  Techniques for reducing power consumption are disclosed in Patent Literature 1 and Patent Literature 2.

  FIG. 16 is a diagram illustrating a driving circuit of the display device disclosed in Patent Document 1. In FIG. 16 includes a level shifter group 101 including a plurality of level shifters, a gradation voltage output circuit (not shown) 102, a gradation signal line 103, a gradation voltage line 104, and a digital-analog. A conversion circuit 105, a level shifter signal switch 106, a gradation voltage input switch 107, and a charge recovery switch 108 are provided.

  The level shifter group 101 outputs digital gradation signals as a plurality of complementary signals. The gradation voltage output circuit 102 outputs an analog gradation voltage. The gradation signal line 103 receives an output from the level shifter group 101. The gradation voltage line 104 receives an output from the gradation voltage output circuit 102. The digital-analog conversion circuit 105 selects and outputs an analog gradation voltage given by the gradation voltage line 104 in accordance with the digital gradation signal given by the gradation signal line 103. The level shifter signal switch 106 disconnects the level shifter group 101 from the gradation signal line 103 or connects the gradation signal line 103. The gradation voltage input switch 107 disconnects the gradation voltage output circuit 102 from the gradation voltage line 104 or connects it to the gradation voltage line 104. The charge recovery switch 108 connects the pair of gradation signal lines that transmit the pair of complementary signals, or separates the pair of gradation signal lines.

  The level shifter signal switch 106 controls whether or not the digital gradation signal output from the level shifter group 101 is transmitted to the digital-analog conversion circuit 105. For example, when the level shifter signal switch 106 is on, the level shifter group 101 and the digital-analog conversion circuit 105 are electrically connected. Accordingly, the digital-analog conversion circuit 105 selects and outputs an analog gradation voltage based on the digital gradation signal output from the level shifter group 101. On the other hand, when the level shifter signal switch 106 is OFF, the electrical connection between the level shifter group 101 and the digital-analog conversion circuit 105 is cut off. At this time, the charge recovery switch 108 is turned on to short-circuit the pair of gradation signal lines that transmit the pair of complementary signals, thereby collecting the charges of the gradation signal line 103. Thereby, power consumption is reduced. At this time, the gate voltages of the transistors constituting the digital-analog conversion circuit 105 are all intermediate between the GND and the high-potential power supply voltage due to the charge recovery, so that all the transistors constituting the digital-analog conversion circuit 105 are turned on. Resulting in. Accordingly, the grayscale voltage input switch 107 is turned off in order to prevent the outputs of the grayscale voltage output circuit 102 from being short-circuited.

  FIG. 17 is a diagram illustrating the potential conversion circuit 200 disclosed in Patent Document 2. In FIG. A potential conversion circuit 200 illustrated in FIG. 17 includes a latch circuit 202 that latches input data IN output from the register circuit 201, a level shifter circuit 203 that converts the output signal of the latch circuit 202, and an output of the level shifter circuit 203. And an inverter circuit 204 for shaping and outputting to the LCD control circuit 205. Note that a plurality of the potential conversion circuits 200 described above are provided between the register circuit 201 and the LCD control circuit 205.

  Inverter circuit 204 includes a P-channel MOS transistor 206, an N-channel MOS transistor 207, and a DC path cut transistor 208. The transistors 206 to 208 are connected in series between the VCC power supply and the VSS power supply. Outputs from the level shifter circuit 203 are supplied to the gates of the transistors 206 and 207, respectively. The potential at the connection point N1 between the drain of the transistor 206 and the drain of the transistor 207 is output to the LCD control circuit 205 as output data OUT. The cut signal CUT output from the timing generation circuit (not shown) 209 is input to the gate of the transistor 208.

  The potential conversion circuit 200 shown in FIG. 17 turns off the transistor 208 based on the cut signal CUT from the timing generation circuit 209 when the potential of the input data IN changes, thereby causing an inverter caused by the output level of the level shifter circuit 203 The DC path of the circuit 204 is cut. Thereby, power consumption is reduced.

JP 2009-015217 A JP-A-9-197369

  Japanese Patent Application Laid-Open No. 2004-228561 does not mention any timing for switching from a plurality of switches constituting the level shifter signal switch 106 to OFF. Therefore, it is considered that the plurality of switches are switched from OFF to ON at the same time. For this reason, in the drive circuit shown in Patent Document 1, charge / discharge current flows from the plurality of level shifters constituting the level shifter group 101 to the gates of the transistors constituting the gradation signal line 103 and the digital-analog conversion circuit 105 all at once. There is a problem that the peak current of the power supply lines of the group 101 increases.

  The potential conversion circuit 200 shown in Patent Document 2 cuts the DC path of the inverter circuit 204 when the potential of the input data changes by the cut signal CUT from the timing generation circuit 209. Therefore, it is considered that the outputs of the plurality of potential conversion circuits 200 change all at once when the cut signal CUT from the timing generation circuit 209 is turned on (the DC path cut transistor 208 is turned on). Therefore, in the drive circuit including a plurality of potential conversion circuits 200 shown in Patent Document 2, charge / discharge currents flow from the plurality of level shifter circuits 203 to the LCD control circuit 205 all at once, and the peak of the power supply line common to the plurality of level shifter circuits 203 There was a problem that the current increased.

  Thus, the conventional drive circuit has a problem that the peak current increases.

  The drive circuit according to the present invention includes a level shift unit that shifts a signal voltage level of digital data of a plurality of bits and supplies the digital data to a plurality of gradation signal lines, and the digital data supplied to the plurality of gradation signal lines. A D / A conversion circuit for outputting a corresponding gradation voltage as analog data, and a plurality of first switches provided on the plurality of gradation signal lines between the level shift unit and the D / A conversion circuit, respectively. A circuit, and a timing control circuit that outputs a control signal for controlling switching of at least one of the plurality of first switch circuits from OFF to ON at a timing different from that of the other switch circuits.

  With the circuit configuration as described above, an increase in peak current can be suppressed.

  According to the present invention, it is possible to provide a driving circuit capable of suppressing an increase in peak current and a display device including the driving circuit.

1 is a block diagram showing a drive circuit according to a first exemplary embodiment of the present invention. 1 is a block diagram showing a drive circuit according to a first exemplary embodiment of the present invention. It is a figure which shows the structural example of the D / A converter circuit concerning Embodiment 1 of this invention. 3 is a timing chart showing the operation of the drive circuit according to the first exemplary embodiment of the present invention. It is a timing chart which shows operation | movement of the drive circuit of a prior art. It is a timing chart which shows change of current which flows into level shifter LS1. It is a timing chart which shows change of current which flows into level shifters LS1-LSn of a prior art. 6 is a timing chart showing a change in current flowing in a power supply line common to level shifters LS1 to LSn according to the first embodiment of the present invention; 1 is a diagram illustrating a configuration example of a timing control circuit according to a first embodiment of the present invention; 3 is a timing chart showing the operation of the timing control circuit according to the first exemplary embodiment of the present invention; It is a figure which shows the other structural example of the timing control circuit concerning Embodiment 1 of this invention. 3 is a timing chart showing the operation of the timing control circuit according to the first exemplary embodiment of the present invention; It is a block diagram which shows the drive circuit concerning Embodiment 2 of this invention. 6 is a timing chart showing the operation of the drive circuit according to the second exemplary embodiment of the present invention. It is a block diagram which shows the drive circuit concerning Embodiment 3 of this invention. It is a block diagram which shows the drive circuit of a prior art. It is a block diagram which shows the electric potential converter circuit of a prior art.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Since the drawings are simplified, the technical scope of the present invention should not be interpreted narrowly based on the description of the drawings. Moreover, the same code | symbol is attached | subjected to the same element and the overlapping description is abbreviate | omitted.

Embodiment 1
FIG. 1 is a block diagram showing a drive circuit according to the first exemplary embodiment of the present invention. The drive circuit 1 according to the present embodiment includes a plurality of levels between a D / A conversion circuit and a level shift unit that shifts the voltage level of multi-bit parallel data (digital data) and outputs the voltage level to the D / A conversion circuit. Switch circuits (first switch circuits) SWC1 to SWCn. The drive circuit 1 according to the present embodiment controls switching from at least one switch circuit of the plurality of switch circuits SWC1 to SWCn from OFF to ON at a timing different from that of the other switch circuits. Thereby, the peaks of the charge / discharge current flowing from the level shifters LS1 to LSn to the D / A conversion circuit 15 are dispersed, and the increase in the peak current is suppressed as a whole. This will be specifically described below.

  First, the circuit configuration of the drive circuit 1 will be described. As shown in FIG. 1, the drive circuit 1 includes a serial-parallel conversion circuit 11, a latch unit 12, a level shift unit 13, a gradation voltage output circuit 14, a D / A conversion circuit 15, and an output circuit 16. The switch unit 20 and the timing control circuit 21 are provided. In FIG. 1, a clock signal / bit data unit 17 outputs bit data. The serial-parallel conversion circuit 11 inputs bit data and outputs n-bit parallel data (digital data). The serial-parallel conversion circuit 11 and the latch unit 12 operate in synchronization with the strobe signal STB output from the logic setting input signal unit 18. Thereby, the parallel data output from the serial-parallel conversion circuit 11 is written in the latch unit 12. The latch unit 12 outputs the written parallel data to the level shift unit 13.

  The level shift unit 13 shifts the voltage level of the parallel data of a plurality of bits and outputs it to the D / A conversion circuit 15 through a plurality of gradation signal lines. Note that a switch unit 20 is provided on a plurality of gradation signal lines between the level shift unit 13 and the D / A conversion circuit 15.

  The timing control circuit 21 generates a plurality of switch control signals based on the strobe signal STB and outputs them to the switch unit 20. On / off of the switch unit 20 is controlled by the plurality of switch control signals.

The gradation voltage output circuit 14 generates a plurality of gradation voltages having different voltage levels based on the power supply of the γ correction power supply 19 and outputs the gradation voltages to the DA conversion circuit 15 through a plurality of gradation voltage lines. For example, the gradation voltage output circuit 14 generates and outputs 2 ⁿ (n is an integer of 2 or more) gradation voltages. The DA conversion circuit 15 selects one of the 2 ⁿ gradation voltages based on the parallel data after the voltage level shift, and outputs it as analog data. The output circuit 16 outputs analog data as an output of the drive circuit 1.

  Next, details of the drive circuit 1 will be described with reference to FIG. Hereinafter, a case where the bit width of parallel data per analog output of the drive circuit 1 is n bits will be described as an example unless otherwise specified. The latch unit 12 has n latch circuits L1 to Ln per analog output. The latch unit 12 outputs n sets of complementary signals corresponding to the n-bit parallel data in synchronization with the rising edge of the strobe signal STB. More specifically, the latch circuit L1 outputs a first set of complementary signals from the output terminals Q and QB. The latch circuit L2 outputs a second set of complementary signals from the output terminals Q and QB. Similarly, the latch circuits L3 to Ln output the third to n sets of complementary signals from the output terminals Q and QB, respectively.

  The level shift unit 13 has n level shifters LS1 to LSn per analog output. The level shift unit 13 shifts the voltage levels of the n sets of complementary signals output from the latch unit 12 from the low voltage system to the high voltage system, and supplies them to the n sets of gradation signal lines. More specifically, the level shifter LS1 shifts the voltage level of the first set of complementary signals (signal A1 and its inverted signal A1B) output from the latch circuit L1 from the low voltage system to the first voltage set. The complementary signal (signal S1 and its inverted signal S1B) is output. Similarly, the level shifters LS2 to LSn increase the voltage levels of the 2 to n sets of complementary signals (signals A2 to An and their inverted signals A2B to AnB) output from the latch circuits L2 to Ln from the low voltage system, respectively. The voltage system is shifted to output 2 to n sets of complementary signals (signals S2 to Sn and their inverted signals S2B to SnB).

  For example, when the signal A1 is at a low level, the inverted signal A1B indicates a high level, the signal S1 indicates a low level, and the inverted signal S1B indicates a high level. When the signal A1 is at a high level, the inverted signal A1B indicates a low level, the signal S1 indicates a high level, and the inverted signal S1B indicates a low level. Similarly, when the signals A2 to An are low level, the inverted signals A2B to AnB are high level, the signals S2 to Sn are low level, and the inverted signals S2B to SnB are high level.

The D / A conversion circuit 15 generates 2 ⁿ levels based on n complementary signals (parallel data after voltage level shift) S1, S1B to Sn, SnB per analog output outputted from the level shift unit 13. One of the gradation voltages is selected and output as analog data. The 2 ⁿ gradation voltages are supplied from the gradation voltage output circuit 14 to the D / A conversion circuit 15 via the corresponding 2 ⁿ gradation voltage lines. In addition, n sets of complementary signals S1, S1B to Sn, SnB are supplied from the level shift unit 13 to the D / A conversion circuit 15 via n sets of grayscale signal lines that form a set of two lines.

The D / A conversion circuit 15 includes a plurality of transistors. More specifically, D / A conversion circuit 15 is provided with respective complementary signals S1, S1B～Sn, the ² n to 2 ¹ of transistors against SnB. For example, when n = 4, the D / A conversion circuit 15 includes 2 ⁴ +2 ³ +2 ² +2 ¹ = 30 transistors. Hereinafter, the operation of the D / A conversion circuit 15 when n = 4 will be described with reference to FIG. In the following description, the plurality of transistors are all N-channel MOS transistors, and the high level is a voltage higher than the maximum voltage of the gradation voltage output circuit and the low level is a voltage lower than the minimum voltage of the gradation voltage output circuit. Of course, when all of the plurality of transistors are P-channel MOS transistors, the high level is considered to be a voltage lower than the lowest voltage of the gradation voltage output circuit, and the low level is assumed to be a voltage higher than the maximum voltage of the gradation voltage output circuit.

Of ² 4 (= 16) pieces of transistors T1~T16 provided for complementary signals S1, S1B, transistor T1~T8 is eight of each ² 4 (= 16) the gradation voltage lines It is provided between the gradation voltage line and nodes N11 to N18. The transistors T9 to T16 are provided between the remaining eight gradation voltage lines and the nodes N11 to N18, respectively.

  The signal S1 output from the level shifter LS1 is applied to the gates of the transistors T1 to T8, and the signal S1B is applied to the gates of the transistors T9 to T16. For example, when the signal S1 is high level and the signal S1B is low level, the transistors T1 to T8 are turned on and the transistors T9 to T16 are turned off. On the other hand, when the signal S1 is at a low level and the signal S1B is at a high level, the transistors T1 to T8 are turned off and the transistors T9 to T16 are turned on.

Of the 2 ³ (= 8) transistors T21 to T28 provided for the complementary signals S2 and S2B, the transistors T21 to T24 are respectively connected between the nodes N12, N14, N16, and N18 and the nodes N21 to N24. Provided. Transistors T25 to T28 are provided between nodes N11, N13, N15, and N17 and nodes N21 to N24, respectively.

  The signal S2 output from the level shifter LS2 is applied to the gates of the transistors T21 to T24, and the signal S2B is applied to the gates of the transistors T25 to T28. For example, when the signal S2 is at a high level and the signal S2B is at a low level, the transistors T21 to T24 are turned on and the transistors T25 to T28 are turned off. On the other hand, when the signal S2 is low level and the signal S2B is high level, the transistors T21 to T24 are turned off and the transistors T25 to T28 are turned on.

Of the 2 ² (= 4) transistors T31 to T34 provided for the complementary signals S3 and S3B, the transistors T31 and T32 are provided between the nodes N22 and N24 and the nodes N31 and N32, respectively. Transistors T33 and T34 are provided between nodes N21 and N23 and nodes N31 and 32, respectively.

  The signal S3 output from the level shifter LS3 is applied to the gates of the transistors T31 and T32, and the signal S3B is applied to the gates of the transistors T33 and T34. For example, when the signal S3 is at a high level and the signal S3B is at a low level, the transistors T31 and T32 are turned on and the transistors T33 and T34 are turned off. On the other hand, when the signal S3 is low level and the signal S3B is high level, the transistors T31 and T32 are turned off and the transistors T33 and T34 are turned on.

Of the 2 ¹ (= 2) transistors T41 and T42 provided for the complementary signals S4 and S4B, the transistor T41 is provided between the node N32 and the output terminal of the D / A conversion circuit 15. The transistor T42 is provided between the node N31 and the output terminal of the D / A conversion circuit 15.

  The signal S4 output from the level shifter LS4 is applied to the gate of the transistor T41, and the signal S4B is applied to the gate of the transistor T42. For example, when the signal S4 is high level and the signal S4B is low level, the transistor T41 is turned on and the transistor T42 is turned off. On the other hand, when the signal S4 is at a low level and the signal S4B is at a high level, the transistor T41 is turned off and the transistor T42 is turned on.

The D / A conversion circuit 15 has any one of 2 ⁿ gradation voltage lines based on the n sets of complementary signals S1, S1B to Sn, SnB output from the level shift unit 13 with the circuit configuration described above. One gradation voltage line and the output terminal of the D / A conversion circuit 15 are made conductive. In this way, the D / A conversion circuit 15 selects any one of the 2 ⁿ gradation voltages and outputs it as analog data.

  As illustrated in FIG. 2, the switch unit 20 includes switch circuits SWC1 to SWCn. The switch circuits SWC1 to SWCn are provided on n sets of gradation signal lines between the level shift unit 13 and the D / A conversion circuit 15, respectively. Each switch circuit SWC1 to SWCn has two switches SW1, SW1B to SWn, SWnB.

The switch unit 20 determines whether or not to transmit the n sets of complementary signals (parallel data after voltage level shift) S1, S1B to Sn, SnB output from the level shift unit 13 to the D / A conversion circuit 15. Control. For example, when the switch circuits SWC1 to SWCn constituting the switch unit 20 are on, the level shift unit 13 and the D / A conversion circuit 15 are electrically connected. Accordingly, n sets of complementary signals S1, S1B to Sn, SnB output from the level shift unit 13 are transmitted to the D / A conversion circuit 15. The D / A conversion circuit 15 selects and outputs one gradation voltage from ²ⁿ gradation voltages based on n sets of complementary signals S1, S1B to Sn, SnB. On the other hand, when the switch circuits SWC1 to SWCn are off, the electrical connection between the level shift unit 13 and the D / A conversion circuit 15 is cut off.

  The timing control circuit 21 generates switch control signals C1 to Cn based on the strobe signal STB and outputs them to the switch circuits SWC1 to SWCn, respectively. FIG. 4 is a timing chart showing the operation of the drive circuit according to the present embodiment. As shown in FIG. 4, the timing control circuit 21 simultaneously lowers the switch control signals C1 to Cn in synchronization with the rise of the strobe signal STB. Accordingly, the switch circuits SWC1 to SWCn are turned off all at once, and the electrical connection between the level shift unit 13 and the D / A conversion circuit 15 is cut off. Note that the input of the gradation signal line on the D / A conversion circuit 15 side is in a HiZ (high impedance) state, but is stored in the parasitic capacitance of the gradation signal line and the gate capacitance of the transistor connected to the gradation signal line. Due to the electric charge, the potential of the gradation signal line is held for a short time of about several tens of ns. As will be described later, since the period during which the strobe signal STB is at a high level is about 100 ns, even if the switch circuits SWC1 to SWCn are turned off for about several tens of ns, the operation of the transistors in the D / A conversion circuit 15 is not affected. Absent. Therefore, the malfunction of the D / A conversion circuit 15 due to a short circuit between the gradation voltage lines does not occur.

  Thereafter, the timing control circuit 21 sequentially raises the switch control signals C1 to Cn at different timings. Thereby, the switch circuits SWC1 to SWCn are sequentially turned on at different timings, and accordingly, the level shifters LS1 to LSn provided in the level shift unit 13 and the corresponding transistors provided in the D / A conversion circuit 15, Are electrically connected in order at different timings. That is, n sets of complementary signals S1, S1B to Sn, SnB output from the level shifters LS1 to LSn are sequentially transmitted to the D / A conversion circuit 15 at different timings. Thereby, the peaks of the charge / discharge currents of the level shifters LS1 to LSn are dispersed, and the increase of the peak current is suppressed as the entire drive circuit. Note that parallel data is written to the D / A conversion circuit 15 during the period when the strobe signal STB is at a high level. That is, while the strobe signal STB is at a high level, the ON / OFF states of the plurality of transistors provided in the D / A conversion circuit 15 are determined in order, and the values at that time are output from the D / A conversion circuit 15. Since the output of the output circuit 16 that receives the output of the D / A conversion circuit 15 is set to HiZ, the output of the drive circuit 1 does not change. Thereafter, during the period when the strobe signal STB falls and shows a low level, the gradation voltage selected based on the parallel data and output from the D / A conversion circuit 15 is output from the output circuit 16, and the output voltage of the drive circuit 1 is output. Will be determined.

  Of course, if the timing control circuit 21 is configured to raise at least one switch control signal among the switch control signals C1 to Cn at a timing different from that of the other switch control signals, then raise the other switch control signals. Good. Thereby, the peaks of the charge / discharge currents of the level shifters LS1 to LSn are distributed more than when the switch control signals C1 to Cn are raised all at once, and the increase of the peak current is suppressed as a whole of the drive circuit. Here, the signal change timings of the switch control signals C1 to Cn are preferably determined in consideration of the peak value of the charge / discharge current of each level shifter. For example, in the case of a level shifter with a small number of transistors controlling on / off, the peak of charge / discharge current is relatively small. Even if a plurality of switch circuits connected to a level shifter having a small peak of charge / discharge current are controlled from OFF to ON at the same timing, the peak of charge / discharge current hardly increases. In other words, signals that control switches with a small number of gates of transistors to be connected, such as switch control signals Cn, Cn-1, and Cn-2, can be operated as a group at the same timing without any problem. .

  The two switches SW1, SW1B to SWn, SWnB constituting each switch circuit SWC1 to SWCn are switched on / off simultaneously. This is to prevent gradation voltage fluctuations, wasteful power consumption, and shortening of element life due to a short circuit between the gradation voltage lines.

  As described above, the drive circuit 1 according to the present embodiment shifts the voltage level of the multi-bit parallel data (digital data) and supplies it to the D / A conversion circuit, and the D / A conversion circuit. Are provided with a plurality of switch circuits SWC1 to SWCn. The drive circuit 1 according to the present embodiment controls switching from at least one switch circuit of the plurality of switch circuits SWC1 to SWCn from OFF to ON at a timing different from that of the other switch circuits. Thereby, the peaks of the charge / discharge current flowing from the level shifters LS1 to LSn to the D / A conversion circuit 15 are dispersed, and the increase in the peak current is suppressed as a whole.

(Comparison with conventional technology)
FIG. 5 is a timing chart showing the operation of a conventional driving circuit that does not include the switch circuits SWC1 to SWCn and the timing control circuit 21. As shown in FIG. 5, in the conventional driving circuit, n sets of complementary signals S1, S1B to Sn, SnB (voltage Parallel data after level shift) is transmitted all at once. For example, parallel data is written to the D / A conversion circuit 15 at a time during the period when the strobe signal STB is at a high level. That is, during the period when the strobe signal STB is at a high level, the ON / OFF state of the plurality of transistors provided in the D / A conversion circuit 15 is determined, and one gradation voltage is selected. However, since the output circuit 16 is HiZ at that time, the output of the drive circuit 1 does not change. Thereafter, during the period when the strobe signal STB falls and indicates a low level, the gradation voltage selected based on the parallel data is output from the output circuit 16 and the output voltage of the drive circuit 1 is determined. In the case of a conventional driving circuit having a configuration in which the switch circuits SWC1 to SWCn are simultaneously switched from OFF to ON, the level shifters LS1 to LSn are simultaneously switched by simultaneously switching the switch circuits SWC1 to SWCn from OFF to ON. Operate.

  FIG. 6 is a timing chart showing changes in the current flowing through the level shifter LS1. As shown in FIG. 6, when the switch circuit SWC1 is switched from OFF to ON, a charge / discharge current flows from the level shifter LS1 to the D / A conversion circuit 15 with the peak immediately after the switching.

  In the case of the prior art having a configuration in which the switch circuits SWC1 to SWCn are switched from OFF to ON all at once, the charge / discharge current flows from the level shifters LS1 to LSn to the D / A conversion circuit 15 all at once, with the peak immediately after the switching. Therefore, as shown in FIG. 7, the charge / discharge currents of the level shifters LS1 to LSn are superimposed, and the peak current increases as the entire drive circuit.

  On the other hand, when the switch circuits SWC1 to SWCn are sequentially switched from off to on at different timings as in the present invention, the peaks of the charge / discharge current flowing from the level shifters LS1 to LSn to the D / A conversion circuit 15 are dispersed. As shown, the increase in peak current is suppressed as a whole. In addition, if at least one switch circuit of the switch circuits SWC1 to SWCn is switched from on to off at a timing different from that of the other switch circuits, an increase in peak current is suppressed as a whole as compared with the related art.

(Configuration example of timing control circuit 21)
FIG. 9 is a diagram illustrating a specific configuration example of the timing control circuit 21. The timing control circuit 21 illustrated in FIG. 9 includes a flip-flop (hereinafter simply referred to as FF) 211, a delay generation unit 212, inverters 213-1 to 213-n, NAND circuits 214-1 to 214-n, OR circuits 215-1 to 215-n and level shifters 216-1 to 216-n are provided.

  In the FF 211, a high level fixed signal is input to the data input terminal (D), the strobe signal STB is input to the clock input terminal (C), the reset signal RST is input to the reset input terminal (RST), and the data output terminal A signal is output from (Q) to the delay generation unit 212.

  The delay generation unit 212 includes a plurality of cascade-connected buffers that are provided after the FF 211. Output signals of any n of the plurality of cascade-connected buffers are output as delay signals DLY1 to DLYn, respectively. That is, the delay generation unit 212 outputs delay signals DLY1 to DLYn obtained by adding different delay amounts to the output signal of the FF 211.

  Inverters 213-1 to 213-n output delay signals DLY1B to DLYnB, which are inverted signals of delay signals DLY1 to DLYn, respectively.

  NAND circuits 214-1 to 214-n output a negative logical product of the delay signals DLY1B to DLYnB and the strobe signal STB, respectively. The OR circuits 215-1 to 215-n output logical sums of the signals output from the NAND circuits 214-1 to 214-n and the delay signals DLY1 to DLYn, respectively. Level shifters 216-1 to 216-n shift the voltage levels of the signals output from the OR circuits 215-1 to 215-n, respectively, and output switch control signals C1 to Cn.

  FIG. 10 is a timing chart showing the operation of the timing control circuit 21 shown in FIG. In the initial state, the reset signal RST and the strobe signal STB indicate a low level, and the output signal of the FF 211, the delay signals DLY1 to DLYn, and the switch control signals C1 to Cn indicate indefinite.

  First, the FF 211 sets the output signal to a low level in synchronization with the rising edge of the reset signal RST (time t0). As a result, the delay signals DLY1 to DLYn become low level. Here, since the delay signals DLY1B to DLYnB, which are inverted signals, are at a high level and the strobe signal STB is at a low level, the switch control signals C1 to Cn are at a high level.

  Next, the FF 211 sets the output signal to the high level in synchronization with the rising edge of the strobe signal STB after releasing the reset (time t1). At time t1, the delay signals DLY1 to DLYn are all at a low level. Here, since the delay signals DLY1B to DLYnB, which are inverted signals, are all at a high level and the strobe signal STB is at a high level, the switch control signals C1 to Cn are at a low level (time t1).

  Thereafter, the delay signals DLY1 to DLYn sequentially change from the low level to the high level at different timings (time t2, t3, t4). Here, the delay signals DLY1B to DLYnB, which are inversion signals, sequentially change from high level to low level at different timings, and the strobe signal STB is high level. Therefore, the switch control signals C1 to Cn are sequentially changed from low level at different timings. It changes to high level (time t2, t3, t4). The same operation is performed after time t5.

  As described above, the timing control circuit 21 shown in FIG. 9 can sequentially output the switch control signals C1 to Cn at different timings. As a result, the timing control circuit 21 shown in FIG. 9 can switch the switch circuits SWC1 to SWCn from OFF to ON sequentially at different timings. Note that when it is desired to switch some of the switch circuits SWC1 to SWCn from off to on at the same timing, the timing control circuit 21 generates one delay signal generated by the delay generation unit in the timing control circuit 21. Is supplied to a plurality of corresponding inverters in the subsequent stage, thereby changing the switch control signals for the several switch circuits at the same timing. Alternatively, the timing control circuit 21 supplies one switch control signal to the several switch circuits. As described above, the timing control circuit 21 can divide the switch circuits SWC1 to SWCn into a plurality of groups, and can control switching of the plurality of groups from OFF to ON at different timings.

(Another configuration example of the timing control circuit 21)
FIG. 11 is a diagram illustrating another configuration example of the timing control circuit 21. FIG. 12 is a timing chart showing the operation of the timing control circuit 21 shown in FIG. The timing control circuit 21 illustrated in FIG. 11 includes a delay generation unit 212a instead of the delay generation unit 212, as compared with the timing control circuit 21 illustrated in FIG. Other circuit configurations and operations of the timing control circuit 21 shown in FIG. 11 are the same as those of the timing control circuit 21 shown in FIG.

  The delay generation unit 212a is provided in the subsequent stage of the FF 211 and includes n FFs connected in cascade. In these n FFs, the output signal of the preceding FF (including FF211) is input to the data input terminal (D), the reset signal RST is input to the reset input terminal (RST), and the system is connected to the clock input terminal (C). The clock CLK is input, and a signal is output from the data output terminal (Q) toward the corresponding inverters 213-1 to 213-n.

  As illustrated in FIG. 12, the delay generation unit 212a adds a delay amount corresponding to the cycle of the system clock CLK to the output signal of the FF 211, and sequentially outputs the delay signals DLY1 to DLYn at different timings.

  As described above, the timing control circuit 21 illustrated in FIG. 12 can sequentially output the switch control signals C1 to Cn at different timings. Thereby, the timing control circuit 21 shown in FIG. 12 can switch the switch circuits SWC1 to SWCn from OFF to ON sequentially at different timings. Note that when it is desired to switch some of the switch circuits SWC1 to SWCn from off to on at the same timing, the timing control circuit 21 generates one delay signal generated by the delay generation unit in the timing control circuit 21. Is supplied to a plurality of corresponding inverters in the subsequent stage, thereby changing the switch control signals for the several switch circuits at the same timing. Alternatively, the timing control circuit 21 supplies one switch control signal to the several switch circuits. As described above, the timing control circuit 21 can divide the switch circuits SWC1 to SWCn into a plurality of groups, and can control switching of the plurality of groups from OFF to ON at different timings.

Embodiment 2
FIG. 13 is a block diagram showing a drive circuit 1a according to the second embodiment of the present invention. The drive circuit 1a shown in FIG. 13 differs from the drive circuit 1 shown in FIG. 2 in the configuration of the D / A conversion circuit 15, and includes a charge recovery switch unit 22, a gradation voltage input switch unit 23, a logic And an inversion identification circuit 24.

The D / A conversion circuit 15 generates 2 ⁿ levels based on n complementary signals (parallel data after voltage level shift) S1, S1B to Sn, SnB per analog output outputted from the level shift unit 13. One of the gradation voltages is selected and output as analog data. The 2 ⁿ gradation voltages are supplied from the gradation voltage output circuit (not shown in FIG. 13) 14 to the D / A conversion circuit 15 via the corresponding 2 ⁿ gradation voltage lines. In addition, n sets of complementary signals S1, S1B to Sn, SnB are supplied from the level shift unit 13 to the D / A conversion circuit 15 via n sets of grayscale signal lines that form a set of two lines.

The D / A conversion circuit 15 includes a plurality of transistors. More specifically, D / A conversion circuit 15 includes a transistor of each ^{2 n} pieces for each level shifter LS1 to LSn. In other words, the D / A conversion circuit 15 includes a total of n · ²ⁿ transistors.

When the output signal S1 of the level shifter LS1 is at a high level, the transistor 151 is turned on and the gradation voltage of the gradation voltage line 152 is selected. At this time, since the inverted output signal S1B of the level shifter LS1 becomes low level, the transistor 153 is turned off, and the gradation voltage of the gradation voltage line 154 is not selected. On the other hand, when the output signal S1 of the level shifter LS1 is at a low level, the transistor 151 is turned off and the gradation voltage of the gradation voltage line 152 is not selected. At this time, since the inverted output signal S1B of the level shifter LS1 becomes high level, the transistor 153 is turned on, and the gradation voltage of the gradation voltage line 154 is selected. In this way, the complementary signals S1, S1B through the pair of gray-scale signal line connected to the level shifter LS1, 2 ^n-1 pieces of gradation voltage lines of the 2 ⁿ the gradation voltage line is selected The Further, ^2n-2 lines out of ^2n-1 gradation voltage lines selected by the complementary signals S1 and S1B by the complementary signals S2 and S2B flowing through the set of gradation signal lines connected to the level shifter LS2. Grayscale voltage lines are selected. Similarly, 2 ⁿ⁻³ gradation voltage lines are selected from the 2 ⁿ⁻² gradation voltage lines selected by the complementary signals S1 and S1B and the complementary signals S2 and S2B by the complementary signals S3 and S3B. The Eventually, one gradation voltage line is selected by the complementary signals S1, S1B to Sn, SnB flowing through n sets of gradation signal lines connected to n level shifters. The gradation voltage of the gradation voltage line is output to the output circuit 16 as analog data.

  The switch unit 20 controls whether n sets of complementary signals S1, S1B to Sn, SnB output from the level shift unit 13 are transmitted to the D / A conversion circuit 15. For example, when the switch circuits SWC1 to SWCn constituting the switch unit 20 are on, the level shift unit 13 and the D / A conversion circuit 15 are electrically connected. Thus, n sets of complementary signals S1, S1B to Sn, SnB output from the level shift unit 13 are transmitted to the D / A conversion circuit 15. On the other hand, when the switch circuits SWC1 to SWCn are off, the electrical connection between the level shift unit 13 and the D / A conversion circuit 15 is cut off.

  The charge recovery switch unit 22 is provided in the subsequent stage of the switch unit 20. The charge recovery switch unit 22 includes n transistors (third switch circuits). The n transistors are provided between n sets of gradation signal lines, each of which is a set of two lines, and ON / OFF is controlled by the logic inversion identification circuit 24. The transistor 155 is provided between a set of gradation signal lines connected to the level shifter LS1 and, when controlled to be on, shorts the gradation signal line receiving the signal S1 and the gradation signal line receiving the signal S1B. Thus, the potential of the gradation signal line that receives the signal S1 and the potential of the gradation signal line that receives the signal S1B are set to the same level. Thus, each transistor provided in the charge recovery switch unit 22 is provided between a pair of gradation signal lines connected to a corresponding level shifter. It operates so that the potential becomes the same level by short-circuiting.

The gradation voltage input switch unit 23 is provided on ²ⁿ gradation voltage lines between the gradation voltage output circuit (not shown in FIG. 13) 14 and the D / A conversion circuit 15. The gradation voltage input switch unit 23 is composed of 2 ⁿ switches (second switch circuits), and 2 ⁿ switches are provided on 2 ⁿ gradation voltage lines, respectively. When the gradation voltage input switch unit 23 is on, the gradation voltage output circuit 14 and the D / A conversion circuit 15 are electrically connected via ²ⁿ gradation voltage lines. As a result, ²ⁿ gradation voltages output from the gradation voltage output circuit 14 are transmitted to the D / A conversion circuit 15. On the other hand, when the gradation voltage input switch unit 23 is off, the electrical connection between the gradation voltage output circuit 14 and the D / A conversion circuit 15 is cut off.

  The logic inversion identification circuit 24 detects the change state of the parallel data (digital data) continuously supplied to the D / A conversion circuit 15 and controls the charge recovery switch unit 22 based on the detection result. For example, when the logic inversion identification circuit 24 detects that the logic of (n / 2) +1 or more gradation signal lines among the n sets of gradation signal lines is inverted, it controls the charge recovery switch unit 22 to be turned on. To do. Thereby, charge recovery is performed. On the other hand, when the logic inversion identification circuit 24 detects that the gradation signal lines equal to or less than (n / 2) pairs are inverted, it controls the charge recovery switch unit 22 to be turned off. Thereby, charge recovery is not performed.

In a period during which the D / A conversion circuit 15 performs an operation of converting parallel data into analog data (hereinafter referred to as a drive period), the switch unit 20 is turned on, the gradation voltage input switch unit 23 is turned on, and the charge recovery switch The unit 22 is controlled to be off. Thereby, the D / A conversion circuit 15 selects the gradation voltage corresponding to the parallel data output from the level shift unit 13 from the ²ⁿ gradation voltages output from the gradation voltage output circuit 14. However, it can be output as analog data.

  When D / A conversion for certain parallel data is completed in the driving period, the charge recovery period starts. In the charge collection period, the charge collection switch unit 22 is controlled by the logic inversion identification circuit 24. Hereafter, each operation | movement with and without performing charge collection in a charge collection period is demonstrated.

  When charge recovery is performed during the charge recovery period, that is, when the logic inversion identification circuit 24 detects that the logic of (n / 2) +1 or more pairs of gradation signal lines is inverted, the charge recovery switch unit 22 is switched from OFF to ON. Can be switched. As a result, the grayscale signal lines of each set are short-circuited, so that the potentials between the grayscale signal lines are substantially the same and substantially the same value. In this charge recovery period, the switch unit 20 is controlled to be off and the gradation voltage input switch unit 23 is controlled to be off. When the switch unit 20 is controlled to be turned off, the electrical connection between the level shift unit 13 and the D / A conversion circuit 15 is interrupted. As a result, charge recovery can be achieved by shorting the grayscale signal lines of each set. Further, the gradation voltage input switch unit 23 is controlled to be turned off, so that the electrical connection between the gradation voltage output circuit 14 and the D / A conversion circuit 15 is cut off. This suppresses the occurrence of abnormal current between different gradation voltage lines.

  When the charge recovery is completed in the charge recovery period, the process proceeds to the next drive period, and D / A conversion is performed on the next parallel data. At this time, the switch unit 20 is turned on, the gradation voltage input switch unit 23 is turned on, and the charge recovery switch unit 22 is turned off. Since the charge recovery is performed during the charge recovery period, each gradation signal line is at an intermediate level. Therefore, in this driving period, each gradation signal line changes from the intermediate level to the low level or the high level, and the power consumption is reduced as compared with the case where the gradation level changes from the high level to the low level or from the low level to the high level.

  On the other hand, when charge collection is not performed during the charge collection period, that is, when the logic inversion identification circuit 24 detects that the gradation signal lines equal to or less than (n / 2) pairs are inverted, the charge collection switch unit 22 is held off. The In this charge recovery period, the switch unit 20 and the gradation voltage input switch unit 23 may be off or on. If the switch unit 20 and the gradation voltage input switch unit 23 are always turned off during the charge recovery period, the circuit configuration is simplified. On the other hand, when charge collection is not performed during the charge collection period, the switch unit 20 and the gradation voltage input switch unit 23 are kept on. The increase is further suppressed.

  Then, after the charge recovery period, the process proceeds to the next drive period, and D / A conversion is performed on the next parallel data. At this time, the switch unit 20 is turned on, the gradation voltage input switch unit 23 is turned on, and the charge recovery switch unit 22 is turned off. Since charge collection was not performed during the charge collection period, each gradation signal line holds a voltage level corresponding to the previous parallel data. Here, since the next parallel data is supplied to the D / A conversion circuit 15, only the (n / 2) pairs or less of the gradation signal lines are inverted, so that the increase in power consumption is relatively small.

  As described above, the drive circuit 1a shown in FIG. 13 suppresses an increase in power consumption by collecting charges of each set of gradation signal lines.

  Here, a specific operation when the switch unit 20 is switched from OFF to ON will be described with reference to FIG. FIG. 14 is a timing chart showing the operation of the drive circuit 1a shown in FIG. In the following, a case where the driving period is shifted to after the charge recovery is performed in the charge recovery period will be described as an example.

  First, when the D / A conversion for certain parallel data is completed in the driving period, the charge recovery period starts. Specifically, the gradation voltage input switch unit 23 is controlled to be off, and the charge recovery switch unit 22 is controlled to be on. In addition, the timing control circuit 21 simultaneously lowers the switch control signals C1 to Cn in synchronization with the rise of the strobe signal STB (time t1). As a result, the switch circuits SWC1 to SWCn are turned off all at once, and the movement of charges is blocked between the level shift unit 13 and the D / A conversion circuit 15. Then, charge recovery is performed during the charge recovery period (time t1 to t2).

  When charge collection is completed in the charge collection period, the next drive period is started, and D / A conversion is performed on the next parallel data. At this time, the gradation voltage input switch unit 23 is controlled to be on, and the charge recovery switch unit 22 is controlled to be off. Further, the timing control circuit 21 sequentially raises the switch control signals C1 to Cn at different timings after the grayscale voltage input switch unit 23 and the charge recovery switch unit 22 are both turned off (time t3, t4, t5). Thereby, the switch circuits SWC1 to SWCn provided in the switch unit 20 are sequentially turned on at different timings, and accordingly, the level shifters LS1 to LSn provided in the level shift unit 13 and the D / A conversion circuit 15 are provided. The corresponding transistors are sequentially electrically connected at different timings. That is, n sets of complementary signals S1, S1B to Sn, SnB output from the level shifters LS1 to LSn are sequentially transmitted to the D / A conversion circuit 15 at different timings. As a result, the peaks of the charge / discharge currents of the level shifters LS1 to LSn are dispersed, and an increase in the peak current is suppressed as the entire drive circuit. During the period when the strobe signal STB is at a high level, parallel data is written to the D / A conversion circuit 15 (time t3 to t6). Thereafter, during the period of low level after the strobe signal STB falls, the gradation voltage selected based on the parallel data is output from the D / A conversion circuit 15 (time t6 to t7).

  Note that the timing control circuit 21 has a configuration in which at least one switch control signal among the switch control signals C1 to Cn is raised at a timing different from that of the other switch control signals, and then the other switch control signal is raised. Good. Thereby, the peaks of the charge / discharge currents of the level shifters LS1 to LSn are distributed more than when the switch control signals C1 to Cn are raised all at once, and the increase of the peak current is suppressed as a whole of the drive circuit. Here, the signal change timings of the switch control signals C1 to Cn are preferably determined in consideration of the peak value of the charge / discharge current of each level shifter. For example, in the case of a level shifter with a small number of transistors controlling on / off, the peak of charge / discharge current is relatively small. Even if a plurality of switch circuits connected to a level shifter having a small peak of charge / discharge current are controlled from OFF to ON at the same timing, the peak of charge / discharge current hardly increases.

  The two switches SW1, SW1B to SWn, SWnB constituting each switch circuit SWC1 to SWCn are switched on / off simultaneously. This is to prevent the D / A conversion circuit 15 from malfunctioning due to a short circuit between the gradation voltage lines.

  As described above, the drive circuit 1a according to the present embodiment shifts the voltage level of parallel data (digital data) of a plurality of bits and supplies it to the D / A conversion circuit, the D / A conversion circuit, and the like. Are provided with a plurality of switch circuits SWC1 to SWCn. Then, the drive circuit 1a according to the present embodiment controls at least one switch circuit among the plurality of switch circuits SWC1 to SWCn to be switched from OFF to ON at a timing different from that of the other switch circuits. Thereby, the peaks of the charge / discharge current flowing from the level shifters LS1 to LSn to the D / A conversion circuit 15 are dispersed, and the increase in the peak current is suppressed as a whole.

  Furthermore, since the drive circuit 1a according to the present embodiment further includes the charge recovery switch unit 22 and the gradation voltage input switch unit 23, the charge recovery of each set of gradation signal lines can be performed. An increase in power is suppressed.

Embodiment 3
FIG. 15 is a block diagram showing a drive circuit 1b according to the third embodiment of the present invention. In the drive circuit 1 according to the first exemplary embodiment illustrated in FIG. 2, the switch control signals C1 to Cn output from the timing control circuit 21 are input to the switch circuits SWC1 to SWCn, respectively. On the other hand, in the drive circuit 1b according to the present embodiment, the switch control signals C1 to Cn output from the timing control circuit 21 are input to the switch circuits SWCn to SWC1, respectively. The other circuit configuration and operation of the drive circuit 1b shown in FIG. 15 are the same as those of the drive circuit 1 shown in FIG.

  In the drive circuit 1b shown in FIG. 15, switching of the switch circuits SWC1 to SWCn from off to on is performed at different timings from the switch circuit SWCn to the switch circuit SWC1 in order. The switch circuit SWCn controls transmission of the most significant bit digital data, and the switch circuit SWC1 controls transmission of the least significant bit digital data.

  As described above, the switch circuits SWC1 to SWCn are switched from OFF to ON at different timings sequentially from the switch circuit SWCn to the switch circuit SWC1, thereby sequentially starting from the transistor group closer to the output terminal side of the D / A conversion circuit 15. The on / off status is confirmed. That is, the on / off state is determined in order from the transistor group through which the most significant bit digital data is propagated. As a result, the voltage level of the analog data output from the D / A conversion circuit 15 changes so as to converge gradually without greatly changing. As a result, the output circuit 16 at the subsequent stage can drive and output stable analog data with little fluctuation.

  More specifically, in the drive circuit 1b according to the present embodiment, the delay of the output circuit 16 can be minimized by quickly bringing the input voltage of the output circuit 16 to the final value. First, when the switch circuit SWCn is turned on, the amount of change in the output voltage of the D / A conversion circuit 15 changes the most, about half of the maximum voltage and the minimum voltage of the gradation voltage output circuit 14. Next, when the switch circuit SWC (n−1) is turned on, the amount of change in the output voltage of the D / A conversion circuit 15 is about 1 of the maximum voltage of the gradation voltage output circuit 14 when the switch circuit SWCn is turned on. / 2. Similarly, as the switch circuits SWC (n−2) to SWC1 are sequentially turned on, the change in the input voltage of the output circuit 16 becomes ½. As a result, the change in the input voltage of the output circuit 16 until the time when the strobe signal STB becomes low level and the output circuit 16 outputs is sequentially reduced, so that the input voltage of the output circuit 16 quickly converges to the final value. Therefore, the delay of the output circuit 16 can be minimized, which is more preferable.

  In the drive circuit 1 shown in FIG. 2, the same effect can be obtained by adjusting the output timing of the switch control signals C1 to Cn output from the timing control circuit 21.

  As described above, the drive circuit according to the first to third embodiments shifts the voltage level of the multi-bit parallel data (digital data) and outputs it to the D / A conversion circuit, and the D / A A plurality of switch circuits SWC1 to SWCn are provided between the conversion circuit. Then, the drive circuits according to the first to third embodiments control switching from at least one switch circuit of the plurality of switch circuits SWC1 to SWCn from off to on at timings different from those of the other switch circuits. Thereby, the peaks of the charge / discharge current flowing from the level shifters LS1 to LSn to the D / A conversion circuit 15 are dispersed, and the increase in the peak current is suppressed as a whole.

  Such a drive circuit is mounted on a display device as driving a data line of the display panel together with a display panel and a plurality of gate drivers that drive the gate lines of the display panel.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, the configuration of the D / A conversion circuit 15 according to the first embodiment and the third embodiment and the configuration of the D / A conversion circuit 15 according to the second embodiment are different from each other. The drive circuit according to the third embodiment can employ the configuration of the D / A conversion circuit 15 according to the second embodiment, and the drive circuit according to the second embodiment can employ the configuration of the first and third embodiments. The configuration of the D / A conversion circuit 15 according to the above can be employed.

  Further, the drive circuit according to the above embodiment can adopt a configuration of a cyclic D / A conversion circuit.

DESCRIPTION OF SYMBOLS 1 Drive circuit 11 Serial-parallel conversion circuit 12 Latch part 13 Level shift part 13-1 to 13-n Level shifter 14 Gradation voltage output circuit 15 D / A conversion circuit 16 Output circuit 17 Clock signal / bit data part 18 Logic setting input Signal unit 19 γ correction power supply 20 Switch unit 21 Timing control circuit 22 Charge recovery switch unit 23 Gradation voltage input switch unit 24 Logic inversion identification circuit 211 Flip-flop 212, 212a Delay generation unit 213 Inverter 214-1 to 214-n NAND circuit 215-1 to 215-n OR circuit 216-1 to 216-n level shifter LS1 to LSn level shifter L1 to Ln latch circuit SWC1 to SWCn switch circuit

Claims (7)

A level shift unit that shifts the voltage level of digital data of a plurality of bits and supplies it to a plurality of gradation signal lines;
A D / A conversion circuit for outputting, as analog data, a gradation voltage corresponding to the digital data supplied to the plurality of gradation signal lines;
A plurality of first switch circuits respectively provided on the plurality of gradation signal lines between the level shift unit and the D / A conversion circuit;
A drive circuit comprising: a timing control circuit that outputs a control signal for controlling switching of at least one of the plurality of first switch circuits from OFF to ON at a timing different from other switch circuits. The timing control circuit includes:
2. The drive circuit according to claim 1, wherein the control signal that controls switching of the plurality of first switch circuits from OFF to ON at different timings is output. The timing control circuit includes:
2. The drive circuit according to claim 1, wherein the plurality of first switch circuits are divided into a plurality of groups, and the control signal that controls switching of the plurality of groups from OFF to ON at different timings is output. . The timing control circuit includes:
The control signal is output so as to be switched from off to on in order from the switch circuit on the gradation signal line through which the most significant bit digital data is propagated among the plurality of first switch circuits. Item 4. The drive circuit according to any one of Items 1 to 3. A plurality of second switch circuits respectively provided on a plurality of gradation voltage lines between the gradation voltage output circuit for outputting the gradation voltage and the D / A conversion circuit;
The timing control circuit according to claim 1, further comprising a plurality of third switch circuits provided between the pair of gradation signal lines.   6. The plurality of first switch circuits and the plurality of second switch circuits are all controlled to be turned off when the plurality of third switch circuits are controlled to be turned on. Timing control circuit. A display panel;
A plurality of gate drivers for driving gate lines of the display panel;
A display device comprising: the drive circuit according to claim 1 that drives a data line of the display panel.

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