KR20090115008A - Multiplexer - Google Patents

Abstract

PURPOSE: A multiplexer is provided to perform a high serialization operation by reducing a value of a virtual capacitor when outputting parallel input data as the serial output data. CONSTITUTION: A first discharge controller(300) controls the discharge of an output node in response to the first input data and a first clock. A second discharge controller(320) controls the discharge of the output node in response to the second input data and a second clock. A charge controller(340) controls the charge of the output node in response to an operation control signal. A driver(360) generates the output data by reversely driving the output node. The phase of the first clock is opposite to the phase of the second clock.

Description

Multiplexer {MULTIPLEXER}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly, to a multiplexer of a semiconductor device, and more particularly, to be used in a Serializer / DESerializer (SERDES) circuit to perform a high speed serialization operation. The present invention relates to a multiplexer of a semiconductor device capable of doing so.

In general, a SERIALIZER / DESerializer (SERDES) circuit receives an output of parallelized data and converts the data into serialized data, or receives a serialized data and converts the data into serialized data.

That is, the SERDES circuit is a circuit for performing a serialization operation in which a plurality of pieces of data in parallel are inputted and outputted in series by a predetermined number, and a plurality of pieces of data in series by a predetermined number. When the input is made, the data may be divided into a circuit for performing a deserialization operation in which a plurality of input data are collected and output in parallel.

Therefore, a circuit for performing serialization operation is usually included with a multiplexer for selectively outputting a plurality of data, and a circuit for performing deserialization operation has a single data. A demultiplexer is included which outputs by dividing by.

1 is a circuit diagram illustrating in detail a multiplexer according to the prior art used in a SERDES circuit.

Referring to FIG. 1, a multiplexer according to the related art used in a SERDES circuit receives first input data P_DATA_A and second input data P_DATA_B in parallel, respectively, and have a phase opposite to each other. In response to the first clock CLOCK_1 and the second clock CLOCK_2, it is outputted as output data S_DATA formed in series.

Specifically, the first driver 100 for driving the first input data P_DATA_A, the second driver 105 for driving the second input data P_DATA_B, and the first clock applied to the positive clock stage. To control the transfer of the first input data P_DATA_A applied to the first input terminal IN_A to the first parallel output terminal PA_ND in response to CLOCK_1 and the second clock CLOCK_2 applied to the sub-clock terminal. Second input data applied to the second input terminal IN_B in response to the first transfer gate TG_1, the first clock CLOCK_1 applied to the sub clock terminal, and the second clock CLOCK_2 applied to the positive clock terminal. The second transfer gate TG_2 for controlling the transfer of the P_DATA_B to the second parallel output terminal PB_ND, and the data carried in the first parallel output terminal PA_ND and the second parallel output terminal PB_ND are driven. Third row for applying to the serial output terminal S_OUT_NODE as output data S_DATA made in series The driver 120 is provided.

FIG. 2 is a timing diagram showing an operation waveform of a multiplexer according to the prior art used in the SERDES circuit shown in FIG.

Referring to FIG. 2, in the multiplexer according to the related art, the first input data P_DATA_A 'A0, A1, A2, A3, A4' is continuously input without intervals, but while passing through the first transfer gate TG_1. It can be seen that the first input data P_DATA_A 'A0, A1, A2, A3, A4' is mounted on the first parallel output terminal PA_ND only at an activation section of the first clock CLOCK_1 and has a predetermined interval.

Similarly, although the second input data P_DATA_B 'B0, B1, B2, B3, and B4' are continuously inputted without intervals, the second input data P_DATA_B 'B0, B1, through the second transfer gate TG_2'. It can be seen that B2, B3, and B4 'are mounted on the second parallel output terminal PB_ND only at an activation section of the second clock CLOCK_2 and have a constant interval.

In this case, as described above, since the first clock CLOCK_1 and the second clock CLOCK_2 have phases opposite to each other, the activation period of the first clock CLOCK_1 and the activation period of the second clock CLOCK_2 are shown in the drawing. As you can see, they don't overlap each other.

Therefore, in the activation section of the first input data P_DATA_A 'A0, A1, A2, A3, A4' and the second clock CLOCK_2 in the first parallel output terminal PA_ND in the activation section of the first clock CLOCK_1. The sections of the second input data P_DATA_B 'B0, B1, B2, B3, and B4' loaded on the second parallel output terminal PB_ND do not overlap each other.

In addition, the first parallel output terminal PA_ND and the second parallel output terminal PB_ND are connected to each other when they are applied to the third driver 120, but have already received the first input data P_DATA_A 'A0, A1, A2, A3, A4. 'And the second input data P_DATA_B' B0, B1, B2, B3, B4 'do not overlap each other, so the serial output data S_DATA mounted on the serial output terminal S_OUT_NODE is the first input data P_DATA_A' A0. , A1, A2, A3, A4 'and the second input data P_DATA_B' B0, B1, B2, B3, B4 'are alternately repeated.

As described above, the multiplexer according to the related art used in the Serdes circuit is serially inputted when two pieces of data, first input data P_DATA_A and second input data P_DATA_2, are formed in parallel. It can be seen that the serialization operation is performed correctly by outputting one data-serialized output data (S_DATA).

However, as shown in FIG. 1, the following problem may occur when the same structure as the multiplexer according to the related art used in the SERDES circuit is provided.

First, after the first input data P_DATA_A passes through the first driver 100 and then passes through the third driver 120 again, the first transfer gate TG_1 including one NMOS transistor and one PMOS transistor is used. After passing through the drain (source) -source (drain), it must pass through the gate of the third driver 120 including one NMOS transistor and one PMOS transistor. That is, a virtual capacitor is generated between the drain (source) and the source (drain) of the first transfer gate TG_1 and passes through a junction capacitor that affects a signal passing through the first driver gate TG_1. It must pass through a gate capacitor that occurs between the gate and the drain (source) -source (drain) and affects the driving force.

Similarly, after the second input data P_DATA_b passes through the second driver 110 and then passes through the third driver 120 again, the second transfer gate TG_2 including one NMOS transistor and one PMOS transistor is used. After passing through the drain (source) -source (drain), it must pass through the gate of the third driver 120 including one NMOS transistor and one PMOS transistor. That is, the gate of the third driver 120 passes through a junction capacitor that affects a signal generated virtually between the drain (source) and the source (drain) of the second transfer gate TG_2. It must pass through a gate capacitor, which occurs between and the drain (source) -source (drain) and affects the driving force.

As such, in order to output the first input data P_DATA_A and the second input data P_DATA_b as output data S_DATA formed in series, a junction capacitor and a gate capacitor must be charged and discharged, respectively. .

In this case, when the first input data P_DATA_A and the second input data P_DATA_b are input at relatively small frequencies, the junction capacitors are respectively formed from the first input data P_DATA_A and the second input data P_DATA_b. ) And enough time to fully swing between the power supply voltage (VDD) level and the ground voltage (VSS) level even after the time for charging / discharging the gate capacitor.

Accordingly, the serial output data S_DATA generated corresponding to the first input data P_DATA_A and the second input data P_DATA_b always swings between the power supply voltage VDD level and the ground voltage VSS level. It is less likely to cause data transmission errors because of the swing. That is, there is little probability of jitter in the form of inter symbol interference (ISI).

However, when the first input data P_DATA_A and the second input data P_DATA_b are input at a relatively high frequency, the junction capacitors are respectively formed from the first input data P_DATA_A and the second input data P_DATA_b. ) And the gate capacitor has insufficient time to fully swing between the power supply voltage (VDD) level and the ground voltage (VSS) level.

Therefore, the serial output data S_DATA generated corresponding to the first input data P_DATA_A and the second input data P_DATA_b swings between the power supply voltage VDD level and the ground voltage VSS level. ), There is a high probability of data passing errors. That is, the probability of jitter in the form of inter symbol interference (ISI) is very high.

In addition, the first input data P_DATA_A and the second input data P_DATA_b have only a function of transmitting the applied data to the first transfer gate TG_1 and the second transfer gate TG_2, respectively, which are to be amplified. Since there is no function to make the first input data P_DATA_A and the second input data P_DATA_b are transmitted, there is a problem of delaying output for a predetermined time.

That is, the output timing of the output data S_DATA in series is delayed by a predetermined time than the input timings of the first input data P_DATA_A and the second input data P_DATA_b so that the information contained in the serial output data S_DATA is delayed. Problems may affect the judgment.

The present invention has been proposed to solve the above-described problems of the prior art, by reducing the value of the virtual capacitor to pass in the process of outputting a plurality of input data in parallel to the output data in series (SERializer / DEserializer) It is an object of the present invention to provide a multiplexer of a semiconductor device that can be used in a SERDES circuit to perform a high speed serialization operation.

According to an aspect of the present invention for achieving the above object, the first discharge control means for controlling the discharge of the output node in response to the first input data and the first clock; Second discharge control means for controlling discharge of the output node in response to second input data and a second clock; Charging control means for controlling charging of the output node in response to an operation control signal; And a driving means for inverting the output node to generate output data.

According to another aspect of the present invention for achieving the above object, the discharge control means for controlling the discharge of the output node in response to a plurality of input data sequentially selected in accordance with the phase signal; Charging control means for controlling charging of the output node in response to an operation control signal; And driving means for inverting the output node to generate output data.

The present invention changes the structure of a multiplexer, thereby minimizing the value of a virtual capacitor that must be passed in the process of outputting a plurality of input data in parallel as output data in series.

As a result, it is used in a SERializer / DESerializer (SERDES) circuit, and thus, the serialization operation can be performed at high speed.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be configured in various different forms, only this embodiment is intended to complete the disclosure of the present invention and to those skilled in the art the scope of the present invention It is provided to inform you completely.

3 is a circuit diagram illustrating in detail a multiplexer according to an embodiment of the present invention used in a SERDES circuit.

Referring to FIG. 3, the multiplexer according to the embodiment of the present invention used in the Serdes circuit receives the first input data P_DATA_A and the second input data P_DATA_B in parallel, respectively. It can be seen that the output data S_DATA made in series is output in response to the first clock CLOCK_1 and the second clock CLOCK_2 having opposite phases.

Specifically, the first discharge control unit 300 for controlling the discharge of the output node S_OUT_NODE in response to the first input data P_DATA_A and the first clock CLOCK_1, and the second input data P_DATA_B and the first input data P_DATA_A and the first clock CLOCK_1. A second discharge control unit 320 for controlling the discharge of the output node (S_OUT_NODE) in response to the two clock (CLOCK_2), and for controlling the charging of the output node (S_OUT_NODE) in response to the operation control signal (MV_CON). The charging control unit 340 and a driving unit 360 for inverting the output node S_OUT_NODE to generate the output data S_DATA are provided.

Here, the first discharge controller 300 outputs the first NAND gate NAND1 and the output signal of the first NAND gate NAND1 for negative logic multiplication of the first clock CLOCK_1 and the first input data P_DATA_A. Is connected to the output node S_OUT_NODE connected to the drain-source and the ground voltage VSS in response to the output signal of the first inverter INV1 and the first inverter INV1 applied to the gate. A first NMOS transistor N1 for controlling is provided.

The second discharge controller 320 outputs the second NAND gate NAND2 and the output signal of the second NAND gate NAND2 for negative logic multiplication of the second clock CLOCK_2 and the second input data P_DATA_B. Is connected to the output terminal S_OUT_NODE and the ground voltage VSS terminal connected to the drain-source in response to the output signal of the second inverter INV2 and the second inverter INV2 applied to the gate. And a second NMOS transistor N2 for controlling this.

In addition, the charge controller 340 controls the connection of the source-drain power supply voltage VDD terminal and the output node S_OUT_NODE in response to the operation control signal MV_CON applied to the gate. It is provided.

In this case, the driving force of the PMOS transistor P1 included in the charge control unit 340 is the driving force of the first NMOS transistor N1 included in the first discharge control unit 300 and the second NMOS provided in the second discharge control unit 320. It is relatively smaller than the driving force of the transistor N2.

The driving force of the first NMOS transistor N1 included in the first discharge control unit 300 and the driving force of the second NMOS transistor N2 provided in the second discharge control unit 320 are the same.

In addition, the driver 360 may include a PMOS transistor P2 for driving the output node S_OUT_NODE up to the potential level of the power supply voltage VDD in response to the potential level of the output node S_OUT_NODE applied to the gate, The NMOS transistor P3 is configured to pull down the output node S_OUT_NODE to the potential level of the ground voltage VSS in response to the potential level of the output node S_OUT_NODE applied to the gate.

That is, the driver 360 includes an inverter for inverting the signal loaded on the output node S_OUT_NODE based on the predetermined logic decision level. Therefore, the driver 360 outputs the output data S_DATA in the inactive state pulled down to logic 'Low' when the potential level of the signal loaded on the output node S_OUT_NODE is higher than the predetermined logic decision level, and outputs the output. When the potential level of the node S_OUT_NODE is lower than the predetermined logic decision level, the output data S_DATA of the active state pull-up driven to the logic 'High' is output.

FIG. 4 is a timing diagram illustrating an operating waveform of a multiplexer according to an embodiment of the present invention used in the SERDES circuit shown in FIG. 3.

Referring to FIG. 4, the multiplexer according to the embodiment of the present invention, similarly to the multiplexer according to the related art shown in FIG. 2, has a first input data P_DATA_A 'A0, A1, A2, A3, A4'. Is input continuously without intervals, but the first input data P_DATA_A 'A0, A1, A2, A3, A4' is the first only in the activation section of the first clock CLOCK_1 by the operation of the first discharge control unit 300. It can be seen that the parallel output terminal PA_ND has a predetermined interval.

In addition, although the second input data P_DATA_B 'B0, B1, B2, B3, and B4' are continuously input without intervals, the second input data P_DATA_B 'B0, B1' is operated by the operation of the second discharge control unit 320. , B2, B3, and B4 'are placed on the second parallel output terminal PB_ND only at the activation section of the second clock CLOCK_2 and have a constant interval.

In this case, as described above, since the first clock CLOCK_1 and the second clock CLOCK_2 have phases opposite to each other, the activation period of the first clock CLOCK_1 and the activation period of the second clock CLOCK_2 are shown in the drawing. As you can see it does not overlap each other.

Specifically, referring to a process in which the first input data P_DATA_A 'A0, A1, A2, A3, A4' is loaded on the first parallel output terminal PA_ND, the first NAND gay provided in the first discharge control unit 300 will be described. The first input data P_DATA_A 'A0, A1, A2, A3, A4' is continuously applied to the first input terminal of the NAND1, and the first clock CLOCK_1 is applied to the second input terminal. 1 The logic level of the input data P_DATA_A 'A0, A1, A2, A3, A4' may be logic 'high' or logic 'low', that is, any logic level In a state in which the first clock CLOCK_1 is activated as logic 'high', the first input data P_DATA_A 'A0, A1,' may be unknown due to the operation characteristic of the first NAND_1 gate. Data of logic level 'high' among A2, A3 and A4 'is inverted and output as logic' low ', and data of logic' low 'is logic' high ' As inverted and output.

However, when the first clock CLOCK_1 is deactivated as logic 'low', the first input data P_DATA_A is 'A0, A1, A2, A3, A4' due to the operation characteristic of the first NAND_1 gate. Regardless of the logic level of ',' it is always output as logic 'High'.

That is, when the first clock CLOCK_1 is activated with logic 'High', the logic level of the first input data P_DATA_A 'A0, A1, A2, A3, A4' is inverted and output. In a state in which the signal is 'low', a signal having a logic level fixed at a logic 'high' is output.

In this state, the first inverter INV1 included in the first discharge control unit 300 inverts the output signal of the first NAND gate NAND1 and transfers the output signal to the first parallel output terminal PA_ND. When CLOCK_1 is activated with logic 'High', a signal having the same logic level as the first input data P_DATA_A 'A0, A1, A2, A3, A4' is loaded on the first parallel output terminal PA_ND. In a state where the first clock CLOCK_1 is deactivated as logic 'low', a signal having a logic level fixed as logic 'low' is loaded on the first parallel output terminal PA_ND.

In this way, the signal loaded on the first parallel output terminal PA_ND is applied to the gate of the first NMOS transistor N1 included in the first discharge control unit 300 so that the potential level of the output node S_OUT_NODE becomes the potential of the ground voltage VSS. The discharge to the level is controlled.

That is, when the first clock CLOCK_1 is activated with logic 'High', a signal having the same logic level as the first input data P_DATA_A 'A0, A1, A2, A3, A4' is the first parallel. Since it is loaded on the output terminal PA_ND, the first NMOS transistor N1 is turned on in a section where the logic level of the first input data P_DATA_A 'A0, A1, A2, A3, A4' is logic 'high'. turn on to discharge the potential level of the output node S_OUT_NODE to the potential level of the ground voltage VSS, and the logic level of the first input data P_DATA_A 'A0, A1, A2, A3, A4' is logic The output node S_OUT_NODE is not discharge controlled by turning off the first NMOS transistor N1 in a period of 'high'.

In addition, when the first clock CLOCK_1 is deactivated to logic 'low', a signal having a logic level fixed to logic 'low' is loaded on the first parallel output terminal PA_ND. The 1NMOS transistor N1 is turned off so that the output node S_OUT_NODE is not always discharge controlled.

In addition, referring to a process in which the second input data P_DATA_B 'B0, B1, B2, B3, and B4' are loaded on the second parallel output terminal PB_ND, the second NAND gate provided in the second discharge control unit 320 may be described. The second input data P_DATA_B 'B0, B1, B2, B3, B4' is continuously applied to the first input terminal of NAND2), and the second clock CLOCK_2 is applied to the second input terminal. The logic level of the data P_DATA_B 'B0, B1, B2, B3, B4' may be logic 'high' or logic 'low', that is, it knows what logic level. In the state where the second clock CLOCK_2 is activated with logic 'High', the second input data P_DATA_B may be changed to 'B0', 'B1', 'B2' due to an operation characteristic of the second NAND gate NAND_2. Data of logic level 'high' among B3 and B4 'is inverted and output as logic' low ', and data of logic' low 'is inverted as logic' high ' And print it out.

However, in a state in which the second clock CLOCK_2 is deactivated as logic 'low', the second input data P_DATA_B 'B0, B1, B2, B3, B4 due to the operation characteristic of the second NAND gate NAND_2. Regardless of the logic level of ',' it is always output as logic 'High'.

That is, when the second clock CLOCK_2 is activated with logic 'High', the logic levels of the second input data P_DATA_B 'B0, B1, B2, B3, and B4' are inverted and output. In a state in which the signal is 'low', a signal having a logic level fixed at a logic 'high' is output.

In this state, the second inverter INV2 provided in the second discharge control unit 320 inverts the output signal of the second NAND gate NAND2 and transfers the output signal to the second parallel output terminal PB_ND. When CLOCK_2 is activated with logic 'High', a signal having the same logic level as the second input data P_DATA_B 'B0, B1, B2, B3, and B4' is loaded on the second parallel output terminal PB_ND. When the second clock CLOCK_2 is deactivated to logic 'low', a signal having a logic level fixed to logic 'low' is loaded on the second parallel output terminal PB_ND.

In this way, the signal loaded on the second parallel output terminal PB_ND is applied to the gate of the second NMOS transistor N2 included in the second discharge control unit 320 so that the potential level of the output node S_OUT_NODE is the potential of the ground voltage VSS. The discharge to the level is controlled.

That is, when the second clock CLOCK_2 is activated with logic 'High', a signal having the same logic level as the second input data P_DATA_B 'B0, B1, B2, B3, and B4' has a second parallelism. Since it is loaded on the output terminal PB_ND, the second NMOS transistor N2 is turned on in a section in which the logic level of the second input data P_DATA_B 'B0, B1, B2, B3, B4' is logic 'high'. turn on to discharge control the potential level of the output node S_OUT_NODE to the potential level of the ground voltage VSS, and the logic level of the second input data P_DATA_B 'B0, B1, B2, B3, B4' is logic In the 'high' period, the second NMOS transistor N2 is turned off to not discharge control the output node S_OUT_NODE.

In addition, when the second clock CLOCK_2 is deactivated as logic 'low', a signal having a logic level fixed as logic 'low' is loaded on the second parallel output terminal PB_ND. 2NMOS transistor N2 is turned off so that output node S_OUT_NODE is not always discharge controlled.

In this case, as described above, since the first clock CLOCK_1 and the second clock CLOCK_2 have phases opposite to each other, the first clock CLOCK_1 is activated in the first discharge control unit 300 so that the first input data is activated. (P_DATA_A) In the period where the discharge node S_OUT_NODE is discharge-controlled according to the logic levels of 'A0, A1, A2, A3, A4', the second clock CLOCK_2 is deactivated in the second discharge controller 320 so that the output node ( S_OUT_NODE) is not discharge controlled.

Similarly, the second clock CLOCK_2 is activated in the second discharge controller 320 to discharge control the output node S_OUT_NODE according to the logic level of the second input data P_DATA_B 'B0, B1, B2, B3, and B4'. In the section, the first clock CLOCK_1 is deactivated in the first discharge control unit 300 so as not to discharge control the output node S_OUT_NODE.

That is, the first discharge control unit 300 and the second discharge control unit 320 alternately rotate the output node S_OUT_NODE in response to the first clock CLOCK_1 and the second clock CLOCK_2 that are activated alternately with each other. Discharge control.

In addition, the charging control unit 340 always supplies the output node S_OUT_NODE to the power supply voltage VDD in response to the operation control signal MV_CON which is always kept active at a logic 'low' in a section in which the multiplexer operates. Charge control at potential level

In this way, although the charging control unit 340 always controls charging in a section in which the multiplexer operates, the potential of the output node S_OUT_NODE when discharge control is performed in the first discharge control unit 300 or the second discharge control unit 320. The reason for the level fluctuation is that the size of the PMOS transistor P1 included in the charge control unit 340 is equal to the size of the first NMOS transistor N1 provided in the first discharge control unit 300 or the second discharge control unit 320. This is because it is smaller than the size of the provided second NMOS transistor N2.

That is, the second NMOS provided in the first NMOS transistor N1 or the second discharge control unit 320 included in the first discharge control unit 300 even while the PMOS transistor P1 included in the charge control unit 340 is charging. When the transistor N2 performs the discharge drive, the potential level of the output node S_OUT_NODE is discharged to the potential level of the ground voltage VSS.

However, the second NMOS provided in the first NMOS transistor N1 and the second discharge control unit 320 included in the first discharge control unit 300 even while the PMOS transistor P1 included in the charge control unit 340 is charging. When the transistor N2 does not discharge drive, the potential level of the output node S_OUT_NODE is charged and driven to the potential level of the power supply voltage VDD.

In addition, the driver 360 determines the potential level of the output node S_OUT_NODE based on the predetermined logic determination level, so that the logic 'high' whose output data S_DATA has the same potential level as that of the power supply voltage VDD. Output is made so as to have a logic 'Low' having the same potential level as the potential level of the high and ground voltages VSS.

That is, while the output node S_OUT_NODE is charged / discharged by the first discharge control unit 300, the second discharge control unit 320, and the charge control unit 340, the potential level is the target level of the power supply voltage VDD. Power supply during the activation period of the first clock (CLOCK_1) or the second clock (CLOCK_2) because the rising speed or falling speed of the potential level is not fast enough. Even if the potential level of the voltage VDD or the potential level of the ground voltage VSS is not reached, the output data S_DATA is equal to the potential level of the power supply voltage VDD if it rises or falls beyond the predetermined logic decision level. A logic 'high' having a level and a logic 'low' having a potential level equal to the potential level of the ground voltage VSS are outputted.

As described above, when the multiplexer according to the embodiment of the present invention used in the Serdes circuit is inputted with two pieces of data, which are formed in parallel, the first input data P_DATA_A and the second input data P_DATA_2. In response, the output node S_OUT_NODE is properly charged / discharged to correctly perform the serialization operation of outputting one serial data-the serial output data S_DATA.

In addition, in the multiplexer according to an embodiment of the present invention, the first input data (P_DATA_A) in the multiplexer according to the prior art shown in FIG. After passing through the first inverter (INV1) provided in 300, passes through the driving unit 360, which is a component compared to the third driver 100 in the multiplexer according to the prior art shown in FIG. In this case, it can be seen that only the gate of the first NMOS transistor N1 of the first discharge control unit 300 and the gates of the NMOS transistor N3 and the PMOS transistor P2 of the driving unit 360 need to pass through.

That is, a gate capacitor and a NMOS transistor provided in the driving unit 360 that are generated between the gate and the drain-source of the first NMOS transistor N1 included in the first discharge control unit 300 to affect driving force ( It can be seen that only a gate capacitor which is generated between N3) and the gate and the drain (source) -source (drain) of the PMOS transistor P2 and affects the driving force is passed.

Similarly, in the multiplexer according to the embodiment of the present invention, the second input data P_DATA_B is the second discharge control unit, which is a component compared to the second driver 110 in the multiplexer according to the related art shown in FIG. After passing through the second inverter (INV2) provided in 320, passes through the driving unit 360, which is a component compared to the third driver 100 in the multiplexer according to the prior art shown in FIG. In this case, it can be seen that only the gate of the second NMOS transistor N2 included in the second discharge control unit 320 and the gates of the NMOS transistor N3 and the PMOS transistor P2 provided in the driver 360 need to pass through.

That is, the gate capacitor and the gate capacitor of the second NMOS transistor N2 included in the second discharge control unit 320 affect the driving force and the NMOS transistor provided in the driver 360 ( It can be seen that only a gate capacitor which is generated between N3) and the gate and the drain (source) -source (drain) of the PMOS transistor P2 and affects the driving force is passed.

Therefore, in the multiplexer according to the embodiment of the present invention, the first input data P_DATA_A and the second input data P_DATA_b are stored without charging / discharging the junction capacitor, compared to the conventional multiplexer. It can output as serial output data S_DATA.

At this time, when the size of the junction capacitor and the size of the gate capacitor (gate capacitor), the size of the junction capacitor (junction capacitor) is much larger than the size of the gate capacitor (gate capacitor), the implementation of the present invention In the multiplexer according to the example, the first input data P_DATA_A and the second input data P_DATA_b are outputted in series as output data S_DATA. The capacitor passed through the input data P_DATA_A and the second input data P_DATA_b as serial output data S_DATA has a much larger value.

Therefore, in the multiplexer according to the embodiment of the present invention, the probability of a data transfer error occurring when outputting the first input data P_DATA_A and the second input data P_DATA_b as serial output data S_DATA is known. Much less than the multiplexer. That is, there is little probability of jitter in the form of inter symbol interference (ISI).

As described above, when the embodiment of the present invention is applied, a plurality of input data in parallel-first input data P_DATA_A and second input data P_DATA_b-are output data in series-output data S_DATA By eliminating the use of the transfer gate in the process of outputting with-, the value of the virtual capacitors-junction capacitor and gate capacitor-through which a plurality of input data are output as output data can be minimized. have.

Therefore, since it is used in a serializer / deserializer (SERDES) circuit and performs a high speed serialization operation, there is little possibility that jitter in the form of inter symbol interference (ISI) is generated. serialization) operation can be performed.

The present invention described above is not limited to the above-described embodiments and drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be obvious to those with knowledge.

For example, in the above-described embodiment of the present invention, although a plurality of input data is two and a multiplexer for serializing the same has been presented, even if the number of input data is more than two and a multiplexer for serializing the scope of the present invention. Included in

In addition, in the above-described embodiment of the present invention, the multiplexing operation is controlled by using two clocks having phases opposite to each other, but a larger number of clocks, for example, 0 degrees, 90 degrees, 180 degrees, and 270 degrees, are used. The use of four clocks with phases to control the multiplexing operation is also within the scope of the present invention.

In addition, the logic gate and the transistor illustrated in the above-described embodiment should be implemented in different positions and types depending on the polarity of the input signal.

1 is a circuit diagram illustrating in detail a multiplexer according to the prior art used in a SERDES circuit.

2 is a timing diagram showing an operating waveform of a multiplexer according to the prior art used in the SERDES circuit shown in FIG.

3 is a circuit diagram illustrating in detail a multiplexer according to an embodiment of the present invention used in a SERDES circuit.

4 is a timing diagram showing an operating waveform of a multiplexer according to an embodiment of the present invention used in the SERDES circuit shown in FIG.

* Explanation of symbols for main parts of the drawings

100: first driver 110: second driver

120: third driver 300: first discharge control unit

320: second discharge control unit 340: charge control unit

360: drive unit

Claims (20)

First discharge control means for controlling discharge of the output node in response to the first input data and the first clock; Second discharge control means for controlling discharge of the output node in response to second input data and a second clock; Charging control means for controlling charging of the output node in response to an operation control signal; And Driving means for inverting the output node to generate output data Multiplexer having a. The method of claim 1, And the first clock and the second clock have opposite phases to each other. The method of claim 1, The first discharge control means, And the output node is discharged when the first input data is in an activation period of the first clock. The method of claim 1, The first discharge control means, And the output node is not discharged when the first input data is in an inactive state in an activation section of the first clock. The method of claim 1, The first discharge control means, And the output node is not discharged irrespective of the first input data in the inactivation section of the first clock. The method of claim 1, The second discharge control means, And discharging the output node when the second input data is in an active state in the activation period of the second clock. The method of claim 1, The second discharge control means, And the output node is not discharged when the second input data is in an inactive state in an activation section of the second clock. The method of claim 1, The second discharge control means, And the output node is not discharged irrespective of the second input data in the inactivation section of the second clock. The method of claim 1, The charging control means, And a PMOS transistor for controlling the connection of the source node and the source voltage to the output node in response to the operation control signal applied to the gate. The method of claim 9, The first discharge control means, A first NAND gate for negative logic multiplication of the first clock and the first input data; A first inverter for inverting the output signal of the first NAND gate; And And a first NMOS transistor for controlling the connection of the drain-source connected output node and the ground voltage terminal in response to the output signal of the first inverter applied to the gate. The method of claim 10, The second discharge control means, A second NAND gate for negative logic multiplication of the second clock and the second input data; A second inverter for inverting the output signal of the second NAND gate; And And a second NMOS transistor for controlling the connection of the drain-source connected output node and the ground voltage terminal in response to the output signal of the second inverter applied to the gate. The method of claim 11, And the first NMOS transistor and the second NMOS transistor have the same discharge port power. The method of claim 12, And the PMOS transistor has a relatively lower driving force than the first and second NMOS transistors. The method of claim 1, The drive means, And generating the output data in an inactive state when the potential level of the output node is higher than a predetermined logic decision level. The method of claim 1, The drive means, And generate the output data in an activated state when the potential level of the output node is lower than a predetermined logic decision level. Discharge control means for controlling discharge of the output node in response to a plurality of input data sequentially selected according to the phase signal; Charging control means for controlling charging of the output node in response to an operation control signal; And Driving means for inverting the output node to generate output data Multiplexer having a. The method of claim 16, The phase signal is, A multiplexer comprising a plurality of clocks each having a predetermined activation interval in different predetermined phases. The method of claim 17, The discharge control means, And a plurality of discharge drivers for discharging the output node in response to any one of a plurality of clocks and an input signal of a plurality of input signals. The method of claim 16, The drive means, And generating the output data in an inactive state when the potential level of the output node is higher than a predetermined logic decision level. The method of claim 16, The drive means, And generate the output data in an activated state when the potential level of the output node is lower than a predetermined logic decision level.

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