CN114628571A

CN114628571A - Superconducting Josephson junction and preparation method thereof

Info

Publication number: CN114628571A
Application number: CN202210243219.9A
Authority: CN
Inventors: 胡志伟; 邱祥冈
Original assignee: Institute of Physics of CAS
Current assignee: Institute of Physics of CAS
Priority date: 2022-03-11
Filing date: 2022-03-11
Publication date: 2022-06-14
Anticipated expiration: 2042-03-11
Also published as: CN114628571B

Abstract

The embodiment of the invention relates to a superconducting Josephson junction and a preparation method thereof, wherein the preparation method comprises the following steps: sequentially preparing on an intrinsic silicon substrate by a magnetron sputtering deviceFirst Nb layer, Al-Al₂O₃The layer and the second Nb layer gave a sample with a three-layer structure; forming junction regions on the three-layered structure by electron beam exposure; removing the second Nb layer in the area to be etched through reactive ion etching; chemical vapor deposition S i₃N₄An insulating layer; removing the positive electron beam resist ZEP520 and S i deposited on said positive electron beam resist ZEP520 by a lift-off process₃N₄An insulating layer; subjecting the sample to chemical vapor deposition S i₃N₄An insulating layer formed by removing S i above the junction region by photolithography and reactive ion etching₃N₄An insulating layer forming a contact hole; cleaning the surface of the sample, then preparing a third Nb layer by magnetron sputtering, and removing the third Nb layer in an area outside a projection area where the contact hole is located by photoetching and reactive ion etching; and cleaning the obtained sample to obtain the superconducting Josephson junction.

Description

Superconducting Josephson junction and preparation method thereof

Technical Field

The invention relates to the technical field of micromachining of thin film materials, in particular to a superconducting Josephson junction and a preparation method thereof.

Background

The josephson junction is composed of two superconductors and a barrier layer through which an electron pair can form a josephson superconducting current, as shown in fig. 1, the S-I-S type junction is most widely used, i.e. the barrier layer (insulating layer) I has the same superconductor S at both ends. The computing power of a computer depends on the integration level of a circuit to a great extent, the size of a device reaches the level of several nm due to the continuous progress of modern micromachining technology, the size is reduced continuously, the insulation and heat dissipation among the devices are problematic, and the small scale also has quantum effect, so that the integration level is difficult to improve after reaching a certain degree. The superconductivity greatly reduces the dissipation and noise of the circuit, has the advantages of high sensitivity close to quantum limit, wide working frequency band and the like, and the performance is far higher than that of other conventional circuits. Thus, superconducting quantum circuits with josephson junctions as core elements are promising candidates for implementing next generation computers. After decades of development, based on Nb/Al-AlO in the eighties of the last century_xThe process for preparing the Josephson junction (Nb junction for short) device with/Nb structure is continuously advanced and matured, the practical application of the Josephson device is gradually realized, and the quality improvement of the Josephson junction of the basic element is a key of modern quantum computers. Nb has many advantages, Nb has high Tc (9.2K), can work well at the temperature of liquid helium, has good thermal cyclicity and stable chemical property, has good physical property and is not easy to damage. The junction area and the critical current density can be well controlled manually; however, the Nb junction also has some disadvantages, such as complex process and long preparation period; for junctions with a size of less than 0.1 μm, process repeatability is of concernAnd the like. The innovation and perfection of the Josephson junction preparation technology can bring profound influence on the development of technology and economy.

The method for manufacturing the Josephson junction in the prior art mainly comprises the following steps:

method one, as described in h.kroger, l.n.smith, and d.w.jillie, appl.phys.lett.39,280(1981), m.gurvitch, m.a.washington, and h.a.huggins, appl.phys.lett.42,472(1983), et al:

the earliest mature Nb junction preparation Process was a Selective Niobium Anodization Process (SNAP), which uses an oxidizing solution to perform Anodization to prepare an insulating layer; in addition, a Selective Niobium Etching Process (SNEP) for Nb junctions has been developed, in which aluminum oxide is used as a junction barrier layer, and Reactive Ion Etching (RIE) is used to form the junctions. The two processes are largely the same and slightly different, and the main difference lies in the different preparation methods of the insulating layer. The SNEP is specifically implemented by covering a junction area with photoresist on the basis of a three-layer film, etching an uncovered upper Nb film by RIE (reactive ion etching), performing anodic oxidation treatment to form an insulating layer, removing the photoresist, cleaning the surface of the junction, and plating a Nb film as an electrode to prepare a complete superconducting Josephson junction, as shown in figure 2.

The quality, reliability and repeatability of the junction made by the SNEP and SNAP technology are greatly improved compared with those of the prior method, but two of the problems are prominent:

1. the insulating layer in the process is obtained by an anodic oxidation method, the thickness of the insulating layer is not easy to control, the insulating property is not good, and therefore the junction is easy to leak (the upper electrode and the lower electrode are short-circuited). The economy and subsequent treatment of the oxidation liquor are also a major problem.

2. The process is difficult to make the junction area small. To contact the junction region with the last deposited Nb lead, a contact hole must be left above the junction, which requires that the area of the junction must be larger than the contact hole, otherwise leakage occurs. This is because from fig. 2 d of the process, it is known that the process requires an electrode made above Nb2 in the shaded insulating layer, which is smaller than the upper Nb2 area, and therefore the junction area is larger than the contact hole for process reasons. For a junction with a size of 2 μm, the contact hole size is required to be 1 μm, which is difficult to achieve and is more difficult to realize a submicron device.

Method two, as described in S.Morohashi, S.Hasao, and T.Yamaoka, appl.Phys.Lett.48,254(1986), T.Imamura and S.Hasao, J.Appl.Phys.64,1586(1988), etc.:

in order to solve the problem of insulation, a Self Aligned Contact (SAC) process is developed on the basis of SNEP, and Nb is subjected to anodic oxidation₂O₅On which Al is deposited as a barrier layer for RIE. Then sputtering a layer of SiO on the surface₂As an insulating layer, junction short-circuiting is greatly reduced. In order to obtain submicron junction area, a Self-aligned Niobium (SCAN) oxidation process is also proposed. As shown in FIG. 3, after the good junction region is determined by anodic oxidation, SiO is used₂Covering the junction region with CHF by reactive ion etching₃The etching rate of the gas to different materials is different, a contact hole larger than the junction area is etched, and the junction with the size of 0.7 mu m is prepared by the process. In fig. 3, a is a structure after an insulating layer is formed after etching, b is a structure after an Al layer is deposited in a and photoresist is removed, and c is a structure after a contact hole is made.

The method is different from SNEP in size, the quality of a sample is improved and the junction area is reduced by adding insulating layers in different modes on the basis of SNAP, but the process flow is more complicated, the yield of devices is not high, and the commercial production is difficult to realize.

Method three, as proposed by z.bao, m.bhushan, s.han, and j.e.lukens, IEEE trans.appl.supercond 5,2731 (1995):

in the field of integration, 1991, the industry, in combination with Chemical Mechanical Polishing (CMP) Technology in the semiconductor industry, developed a set of tunnel junction processing Technology-planar All-Refractory Technology for low-critical-temperature superconductors (PARTS), by which to fabricate on 125mm Si substrateLarge batch of submicron junctions are prepared, and the processing technology of the submicron junctions advances a large step. Later, the development of the process was carried out, and in combination with Electron Beam Lithography (EBL), a PARTS-EBL process was developed to reduce the junction size to the deep submicron level and minimize the junction area to 0.006 μm². Although the PARTS process can be scaled up and can produce high quality submicron junctions, the process is too complex, only SiO₂Four layers are sputtered, the photolithography and etching technology (including wet etching) is frequently used, the process requirement of each step is very high, the equipment requirement is high, the preparation period is too long, and the cost is high. Figure 4 shows a more typical process flow for which complexity can be seen.

Disclosure of Invention

The invention aims to provide a superconducting Josephson junction and a preparation method thereof, the preparation method has high success rate, good repeatability and simpler process, and can realize submicron Nb/Al-AlO_xMicromachining of josephson junctions of/Nb construction.

To this end, in a first aspect, embodiments of the present invention provide a method of preparing a superconducting josephson junction, the method comprising:

preparing a clean intrinsic silicon substrate;

sequentially preparing a first Nb layer and Al-Al on the intrinsic silicon substrate by magnetron sputtering equipment₂O₃The layer and the second Nb layer gave a sample with a three-layer structure; wherein two Nb layers and Al-Al₂O₃The Al layer is formed by magnetron sputtering in a sputtering chamber of the magnetron sputtering device, the Al-Al layer₂O₃Al in the layer₂O₃The layer is formed by oxidation in a pure oxygen environment of a sample chamber of the magnetron sputtering equipment; in the process of forming the three-layer structure, the intrinsic silicon substrate is not in contact with the atmosphere;

forming junction regions on the three-layered structure by electron beam exposure; wherein the junction area is covered by positive electron beam resist ZEP520 on the surface, and the two sides of the junction area are provided with areas to be etched which are not covered by the positive electron beam resist ZEP 520;

removing the second Nb layer in the area to be etched through reactive ion etching;

chemical vapor deposition of Si₃N₄An insulating layer;

removing the positive electron beam resist ZEP520 and Si deposited on said positive electron beam resist ZEP520 by a lift-off process₃N₄Insulating layer, and cleaning the surface of the sample;

carrying out chemical vapor deposition (Si) on the sample with the cleaned surface₃N₄An insulating layer for removing Si above the junction region by photolithography and reactive ion etching₃N₄An insulating layer forming a contact hole; the area of the contact hole is larger than that of the junction region, so that Al-Al of the junction region₂O₃A layer exposed in the contact hole;

cleaning the surface of the sample, then preparing a third Nb layer by magnetron sputtering, and removing the third Nb layer in an area outside a projection area where the contact hole is located by photoetching and reactive ion etching; the bottom of the retained third Nb layer is in contact with the second Nb layer of the junction region, the top forming a test electrode of the superconducting josephson junction;

and cleaning the obtained sample to obtain the superconducting Josephson junction.

Preferably, the room temperature resistivity of the intrinsic silicon substrate is greater than 10000 Ω · cm.

Preferably, the first Nb layer and the Al-Al layer are sequentially prepared on the intrinsic silicon substrate through a magnetron sputtering device₂O₃The layer and the second Nb layer the sample obtained with the three-layer structure specifically included:

in the sputtering cavity of the magnetron sputtering equipment, the vacuum degree is 1 multiplied by 10^-6The working gas is high-purity Ar gas with the purity of 5N, the flow rate is set to be 20sccm, the current is set to be 1500mA, the voltage is set to be 340V, the coating time is set to be 120s, and a first Nb layer with the thickness of 120nm +/-5% is prepared;

cooling for a set time;

degree of vacuum of 2X 10^-6Pa below, the working gas is high-purity Ar gas with the purity of 5N, the flow rate is set to be 20sccm, the current is set to be 250mA, the voltage is set to be 370V, and plating is carried outThe film forming time is 20s, and an Al layer with the film thickness of 10nm +/-10% is prepared;

after cooling time, the sample was transferred to a vacuum of 1X 10^-5A sample introduction chamber below Pa;

filling high-purity oxygen with the purity of 5N into the sample chamber, setting the pressure to be 1000Pa and the ventilation time to be 60min, carrying out surface oxidation on the Al layer, and forming Al on the surface of the Al layer₂O₃；

Then the mixture is sent into a sputtering cavity of the magnetron sputtering equipment with the vacuum degree of 1 multiplied by 10^-6Pa below, the working gas is high-purity Ar gas with the purity of 5N, the flow rate is set to be 20sccm, the current is set to be 1500mA, the voltage is set to be 340V, the coating time is set to be 50s, and the second Nb layer with the thickness of 50nm +/-10% is prepared.

Preferably, the forming of the junction region on the triple-layered structure by electron beam exposure specifically includes:

sequentially putting the sample with the three-layer structure into acetone, absolute ethyl alcohol and deionized water for ultrasonic cleaning, and drying after cleaning;

and coating a positive electron beam resist ZEP520 on the sample with the three-layer structure after being washed and dried, and forming the junction area through pre-baking, electron beam exposure, development and fixation.

Preferably, the removing of the second Nb layer in the region to be etched by reactive ion etching specifically includes:

in the reactive ion etching apparatus, the working gas was Ar gas, the gas flow rate was 5.9sccm, and the working gas pressure was 2.0X 10^-2Pa, ion energy 300eV, acceleration voltage-200V, and ion beam current density 50mA/cm²The anode voltage is 45V, and the second Nb layer in the area to be etched, which is not covered by the positive electron beam resist ZEP520, is etched; wherein, every etching time is 1min, cooling is carried out for 5min, so as to avoid coking of the positive electron beam resist ZEP520 in the etching process.

Preferably, the chemical vapor deposition of Si₃N₄The insulating layer specifically is:

using inductively coupled chemical vapor deposition (ICP-PECVD) system, working gas and corresponding flow are divided at a working temperature of 130 DEG CAr gas 126sccm, SiH₄ 6.9sccm，NH₃Si is carried out under the conditions of 13sccm, working gas pressure of 1.0Pa and ICP power of 350W₃N₄Chemical vapor deposition of the insulating layer;

wherein, every 45s of deposition, the cooling is carried out for 5 min.

Preferably, the positive electron beam resist ZEP520 and the Si deposited on the positive electron beam resist ZEP520 are removed by a stripping process₃N₄The insulating layer specifically is:

the sample was put into a dimethylacetamide solution and soaked for 24 hours to remove the positive electron beam resist ZEP520 and Si deposited on the positive electron beam resist ZEP520₃N₄Insulating layer to expose Nb junctions on the sample surface.

Preferably, the sample after surface cleaning is subjected to chemical vapor deposition Si₃N₄An insulating layer for removing Si above the junction region by photolithography and reactive ion etching₃N₄The insulating layer, the contact hole that forms includes specifically:

sequentially putting a sample into acetone, absolute ethyl alcohol and deionized water for ultrasonic cleaning, and drying after cleaning;

after cleaning and drying, the sample is subjected to glue spreading, pre-baking, electron beam exposure, development and fixation to form a contact hole area to be etched;

performing sample surface pretreatment, setting the working gas as Ar gas, the flow rate of 30sccm, the power of 100W, the gas pressure of 30mTorr and the etching time of 30 s;

etching the contact hole with CHF as working gas and corresponding flow rate₃ 50sccm，O₂5sccm, power 200W, and gas pressure 55 mTorr.

Preferably, the step of preparing the third Nb layer by magnetron sputtering, and the step of removing the third Nb layer in the region other than the projection region where the contact hole is located by photolithography and reactive ion etching specifically includes:

in the sputtering cavity of the magnetron sputtering equipment, the vacuum degree is 1 multiplied by 10^-6Pa below, the working gas is high-purity Ar gas with the purity of 5N, the flow rate is set to be 20sccm, the current is set to be 1500mA, the voltage is set to be 340V, and the coating time is set300s, preparing a third Nb layer with the film thickness of 300nm +/-5%;

after cleaning and drying, the sample is subjected to glue coating, prebaking, electron beam exposure, development and fixation to expose a region to be etched;

etching the area to be etched to remove the third Nb layer in the area outside the projection area of the contact hole, wherein the working gas and the corresponding flow rate are respectively Ar gas 10sccm and SF gas₆30sccm, power 130W, and gas pressure 30 mTorr.

In a second aspect, the embodiments of the present invention provide a superconducting josephson junction prepared by the preparation method described in the first aspect.

The preparation method of the superconducting Josephson junction provided by the embodiment of the invention has the advantages of high success rate, good repeatability and simpler process, and can realize the submicron Nb/Al-AlO_xMicromachining of josephson junctions of/Nb construction.

Drawings

FIG. 1 is a schematic view of a Josephson junction;

FIG. 2 is a schematic process flow diagram of SNEP;

FIG. 3 is a schematic cross-sectional view of a Nb junction prepared by the SAC process;

FIG. 4 is a flow diagram of a typical PARTS-EBL process;

FIG. 5 shows Nb/Al-Al in accordance with an embodiment of the present invention₂O₃A flow chart of a preparation method of a Josephson junction with a/Nb structure;

FIG. 6 is a schematic diagram of a process for preparing a Josephson junction of Nb/Al-Al2O3/Nb structure according to an embodiment of the present invention;

FIG. 7 is an Atomic Force Microscope (AFM) view of a Nb film of an example of the present invention;

FIG. 8 is a Scanning Electron Microscope (SEM) image of an Nb junction made according to an embodiment of the present invention;

FIG. 9 is an enlarged view of the edge of the junction region shown in FIG. 8;

fig. 10 is a graph of current-voltage IV and differential conductance dI/dV for samples of josephson junctions prepared in accordance with an embodiment of the present invention.

Detailed Description

The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments. It should be noted that the specific process parameters adopted in the following embodiments of the present invention are not limited to the conditions that the present invention can be implemented, and those skilled in the art can adjust the specific process parameters according to the actual equipment and the actual device structure according to the process flow provided by the present invention.

An embodiment of the present invention provides a method for preparing a superconducting josephson junction, which mainly includes the steps shown in fig. 5, fig. 6 is a schematic view of a process for preparing a Nb/Al-Al2O3/Nb structure josephson junction provided by an embodiment of the present invention, and the preparation method of the present invention is introduced with reference to fig. 5 and 6.

The method mainly comprises the following steps:

step 110, preparing a clean intrinsic silicon substrate;

the normal temperature resistivity of the intrinsic silicon substrate is more than 10000 omega cm.

In one embodiment, the substrate is 1 × 1 × 0.5cm in size³The surface of the intrinsic silicon substrate is provided with SiO with the thickness of about 300nm₂And oxidizing the layer. To ensure that the intrinsic silicon has no effect on the thin film, 300nm thick SiO is added on the intrinsic silicon substrate₂The oxide layer and thus the substrate can be guaranteed to be insulating and not to affect the measurement process.

When in use, the substrate can be cleaned firstly, and then ultrasonically cleaned for 5min by acetone, absolute ethyl alcohol and deionized water in sequence, and then dried by a dry nitrogen gun or a drying machine. The sample at this point is shown as a in figure 6.

Step 120, preparing a first Nb layer and Al-Al layer in sequence on the intrinsic silicon substrate by magnetron sputtering equipment₂O₃The layer and the second Nb layer gave a sample with a three-layer structure;

wherein two Nb layers and Al-Al₂O₃The Al layer of the layers is formed by magnetron sputtering in a sputtering chamber of a magnetron sputtering device, Al-Al₂O₃Al in the layer₂O₃The layer is formed by oxidation in a pure oxygen environment of a sample chamber of a magnetron sputtering device. In the process of forming the three-layer structure, the intrinsic silicon substrate is not contactedAnd (4) the atmosphere.

The three layers of films are not contacted with the atmosphere during the preparation process, so that the quality of an interface is ensured. The coating parameters mainly comprise the degree of vacuum of the back bottom, the flow of working gas, the current and voltage of a power supply and the coating time of a sputtering chamber before coating. In the sputtering process, a constant current mode of a direct current power supply is used, in the constant current mode, the current is set to be constant, the voltage is determined by the air pressure of the sputtering cavity, and a gate valve which is used for connecting the sputtering cavity and a vacuum pump in the adjusting equipment can change the air pressure and further react on the voltage, so that only the voltage needs to be concerned in the film coating process, and the air pressure does not need to be measured. The coating parameters are as follows:

cooling for a set time;

degree of vacuum of 2X 10^-6The working gas is high-purity Ar gas with the purity of 5N, the flow rate is set to be 20sccm, the current is set to be 250mA, the voltage is set to be 370V, the coating time is set to be 20s, and an Al layer with the thickness of 10nm +/-10% is prepared;

introducing high-purity oxygen with purity of 5N into the sample chamber, setting pressure 1000Pa and ventilation time 60min, performing surface oxidation of Al layer, and forming Al on the surface of Al layer₂O₃；

Then the mixture is sent into a sputtering cavity of magnetron sputtering equipment, and the vacuum degree is 1 multiplied by 10^-6Pa below, the working gas is high-purity Ar gas with the purity of 5N, the flow rate is set to be 20sccm, the current is set to be 1500mA, the voltage is set to be 340V, the film coating time is set to be 50s, and the second Nb layer with the film thickness of 50nm +/-10% is prepared.

All the processes are finished at room temperature, the substrate is cooled by cooling water, and in order to prevent interface quality degradation and stress among different film layers caused by temperature change in the coating process, the substrate needs to be cooled for at least 1 hour after each coating of one film.

The sample at this point is shown as b in figure 6.

Step 130, forming junction regions on the three-layer structure by electron beam exposure;

wherein the surface of the junction area is covered by the positive electron beam resist ZEP520, and both sides of the junction area have an area to be etched which is not covered by the positive electron beam resist ZEP 520.

The preparation method comprises the specific steps of sequentially placing a sample with a three-layer structure into acetone, absolute ethyl alcohol and deionized water, ultrasonically cleaning for 5min, and then drying by using a dry nitrogen gun or a drying machine. The sample with the three-layer structure after being washed and dried is coated with a positive electron beam resist ZEP520, and subjected to prebaking, electron beam exposure, development and fixation to form a junction region.

The junction area pattern is formed by electron beam Exposure (EBL), the electron beam exposure glue uses ZEP520, which is an EBL positive resist with the resolution of 10nm and high sensitivity, and the most important characteristic is strong etching resistance, and in a subsequent Ar ion etching system, the etching rate of the glue is low and is only 1-2nm/min, so that the glue has very high selective etching ratio; meanwhile, the adhesive can withstand relatively high temperature without scorching, and is not prone to problems during sputtering and stripping of the insulating layer.

The main process parameters we used in the implementation are as follows:

gluing: dripping ZEP520 photoresist on the surface of the cleaned sample; and (4) homogenizing the glue on a spin coater at the speed of 3000r/min for 1min, wherein the glue thickness is about 350 nm.

Pre-baking: the sample was baked on a hot plate at 130 ℃ for 1 min.

Electron beam exposure: the exposure equipment adopts Raith 150, the exposure voltage is 20kV, the aperture is 20 mu m, and the dosage is 30 mu C/cm²。

And (3) developing: the exposed sample was developed with developer solution xylene for 90 plus 20 seconds, where the last 20 seconds is the over-development time. The increase of the over-development is beneficial to the stripping of the subsequent insulating layer.

Fixing: after the development, the sample was placed in methyl isobutyl ketone (MIBK), isopropyl alcohol (IPA) 1:3 and IPA for 1min each, and finally the surface of the sample was dried with a nitrogen gun.

The sample at this point is shown as c in figure 6.

Step 140, removing the second Nb layer in the area to be etched through reactive ion etching;

in the reactive ion etching apparatus, the working gas was Ar gas, the gas flow rate was 5.9sccm, and the working gas pressure was 2.0X 10^-2Pa, ion energy 300eV, acceleration voltage-200V, ion beam current density 50mA/cm²The anode voltage is 45V, and the second Nb layer in the area to be etched, which is not covered by the positive electron beam resist ZEP520, is etched; and measuring the etching rate, wherein the ZEP520 is 1-2nm/min, the Nb is 10nm/min, and the etching time can be calculated according to the thickness of the second Nb layer, and the over-etching time is 3% -5%.

In order to prevent the temperature from increasing to cause gel coking in the etching process, cooling is carried out for 5min every time the positive electron beam resist ZEP520 is etched, so that coking of the positive electron beam resist ZEP520 in the etching process is avoided, and conditions are created for stripping a subsequent insulating layer.

The sample at this point is shown as d in FIG. 6.

Step 150, chemical vapor deposition of Si₃N₄An insulating layer;

the periphery of the junction region after etching needs to be protected by an insulating layer, and Si is deposited by using an inductively coupled chemical vapor deposition system (ICP-PECVD)₃N₄An insulating layer. SiO is not used in the present invention₂The reason for the insulating layer is because of the deposition of SiO₂Oxygen active ions exist in the process, the damage to the sample is unknown, and Si is used₃N₄This problem can be avoided.

The insulating layer has two functions, namely, the gap left by etching the film is filled and leveled, so that the surface of the sample is a relatively flat surface, and the subsequent preparation of the measuring electrode is facilitated; secondly, the insulating layer deposited by the method has good coating property, and can effectively prevent the electrode from being communicated with the side wall of the bottom layer.

In one embodiment, an inductively coupled chemical vapor deposition (ICP-PECVD) system is used, wherein the working gas and the corresponding flow rates are respectively 126sccm of Ar gas and 126sccm of SiH at a working temperature of 130 DEG C₄6.9sccm，NH₃Si is carried out under the conditions of 13sccm, working gas pressure of 1.0Pa and ICP power of 350W₃N₄InsulationChemical vapor deposition of the layer; wherein, every 45s of deposition, cooling for 5min for 6 times, and preparing Si with thickness of about 100nm₃N₄An insulating layer.

The sample at this point is shown as e in figure 6.

160, the positive E-beam resist ZEP520 and the Si deposited on the positive E-beam resist ZEP520 are removed by a lift-off process₃N₄Insulating layer, and cleaning the surface of the sample;

specifically, the sample obtained in the above step was immersed in a dimethylacetamide solution for 24 hours to remove the positive electron beam resist ZEP520 and Si deposited on the positive electron beam resist ZEP520₃N₄Insulating layer to expose Nb junctions on the sample surface. During the soaking process, ultrasonic treatment can be simultaneously carried out.

Sample surface cleaning is sample surface cleaning using Reactive Ion Etching (RIE). The working gas is Ar gas, the flow rate is 30sccm, the power is 100W, the gas pressure is 30mTorr (30mTorr starting), and the etching time is 30 s.

The sample at this point is shown as f in figure 6.

Step 170, performing chemical vapor deposition Si on the sample with the cleaned surface₃N₄An insulating layer for removing Si over the junction region by photolithography and reactive ion etching₃N₄An insulating layer forming a contact hole;

the contact hole is used for manufacturing a measuring electrode and ensures that each designed part circuit can be accurately connected to the surface of the upper Nb film with the junction exposed. In order to manufacture the measuring electrode in actual operation, an insulating layer is required to be protected around a junction region, and the method adopted by the invention is to deposit an insulating layer and etch a contact hole of the measuring electrode.

Depositing an insulating layer by ICP-PECVD, and depositing Si by ICP-PECVD in the same step 150 according to specific process parameters₃N₄And (5) processing parameters of the insulating layer.

The lithography uses EBL exposure with a write field area of 100 microns and junction regions in the middle of the area surrounded by an insulating layer such that there is an insulating layer around the junction regions in the range of about 50 microns. And after photoetching is finished, etching the contact hole by using reactive ions.

The specific process parameters are as follows:

and (3) putting the sample into acetone, absolute ethyl alcohol and deionized water, ultrasonically cleaning for 5min respectively, and blow-drying the sample by using a nitrogen gun after cleaning.

Gluing: and dripping AZ6130 ultraviolet photoresist on the surface of the cleaned sample by a dropper, and homogenizing the photoresist on a homogenizer at the speed of 4000r/min for 1min to be about 1 mu m thick.

Pre-baking: the sample was baked on a hotplate at 115 ℃ for 1 min.

Exposure: the samples were exposed on a laser direct write DWL66+, working wavelength 405nm, exposure parameters: 60mW of power, 60 percent of intensity and 25 percent of filter.

And (3) developing: the sample was placed in AZ300MIF developer for 1 min.

Fixing: the sample was placed in deionized water for fixation for 10 s. The water on the surface was blown dry using a nitrogen gun.

Etching the insulating layer:

working gas and flow rate thereof: CHF₃50sccm，O₂5sccm, a power of 200W, a gas pressure of 55mTorr, a room temperature etching temperature, and an etching rate of about 85 nm/min.

The area of the contact hole formed finally is larger than the area of the junction region, so that the Al-Al of the junction region₂O₃The layer is exposed in the contact hole.

The sample at this point is shown as g in FIG. 6.

Step 180, cleaning the surface of the sample, preparing a third Nb layer by magnetron sputtering, and removing the third Nb layer in an area outside a projection area where the contact hole is located by photoetching and reactive ion etching;

after the contact hole is made, the excess photoresist is washed away with acetone, and then the sample surface is cleaned with RIE, the method is the same as the method described in step 160.

Then, a 300nm thick Nb film was deposited by magnetron sputtering in a sputtering chamber of a magnetron sputtering apparatus under a vacuum degree of 1X 10^-6Pa below, the working gas is high-purity Ar gas with the purity of 5N, the flow rate is set to be 20sccm, the current is set to be 1500mA, the voltage is set to be 340V, and the plating is carried outAnd preparing a third Nb layer with the thickness of 300nm +/-5% within 300 s.

After cleaning and drying, the sample is subjected to glue coating, prebaking, electron beam exposure, development and fixation to expose a region to be etched; the specific lithography parameters refer to the lithography of the Nb layer in the foregoing step, and may also use the process of the ultraviolet photoresist, refer to step 170, and the ultraviolet photoresist used in the implementation of the present invention is not described herein again.

Then, etching the area to be etched to remove the third Nb layer in the area outside the projection area where the contact hole is located, wherein the working gas and the corresponding flow rate of the working gas are respectively 10sccm and SF of Ar gas₆30sccm, power 130W, and gas pressure 30 mTorr. Similarly, considering that the photoresist can be removed easily, cooling is carried out for 2min every 45s of etching time in the etching process, and the total etching time is calculated according to the etching rate and the film thickness and is overetched for 3% -5%. And soaking and cleaning the photoresist by using acetone after etching, and blowing the sample by using a nitrogen gun until the sample preparation is finished.

The bottom of the retained third Nb layer is in contact with the second Nb layer of the junction region, the top forming a test electrode of the superconducting josephson junction.

The sample at this point is shown as h in FIG. 6.

And 190, cleaning the obtained sample to obtain the superconducting Josephson junction.

Fig. 6 is an Atomic Force Microscope (AFM) image of the Nb thin film prepared in the example of the present invention, and it can be seen that the surface of the film is flat and the columnar crystal structure of Nb can be clearly seen.

FIG. 7 is a Scanning Electron Microscope (SEM) image of a prepared Nb junction, FIG. 8 is a magnified result of the edge of the junction, from which the boundary between the junction and the surrounding insulating layer can be clearly seen, the insulating layer coating around the junction is good, no leakage region exists, the columnar structure of Nb film on the junction surface can be seen, and the result is consistent with that of FIG. 6, which shows that the insulating layer on the junction surface is peeled off cleanly.

Fig. 9 is a graph of the current-voltage IV and differential conductance dI/dV of a sample normalized using the values of the high bias voltage, showing the nonlinear current-voltage curve of the sample, and a tunneling differential conductance plot for a typical superconducting josephson junction, from which it can be seen that the superconducting bandgap of Nb is 2.6meV, and the superconducting transition temperature is 8.9K.

The invention realizes simplicity, reliability, short preparation period, no complexity in process, and good stability and repeatability on the premise of ensuring the quality of the superconductive Josephson junction.

In the preparation process of the invention, the quality of each layer of film, particularly the surface flatness, is the key of a high-quality junction, the back vacuum is high, high-purity sputtering gas and a faster sputtering rate are key factors, and the Nb film obtained by optimizing parameters is shown in figure 6, the surface flatness (RMS) is 0.321nm, and the surface fluctuation peak-to-valley value is 1.567nm, which is superior to the result of RMS about 1nm mentioned in the general literature.

Compared with the SNAP and SAC technologies in the early days, the oxidation liquid is used for anodic oxidation to achieve the purpose of insulation, and the use and subsequent treatment of the oxidation liquid are not friendly in economy and environment. The process uses the alumina as the insulating layer between the three layers of films, avoids the problem of oxidizing liquid, has good economic and environmental benefits, can accurately control the thickness of the insulating layer, can prepare a structure with a complex structure, and is particularly important for the processing and the preparation of precise devices.

The process is completely finished in an ultra-clean room, so that the quality of a sample is ensured; compared with the complex technology in commercialization, the process has the advantages of simple operation, low requirement on instruments, high operation flexibility and sufficient variable space. The method is also suitable for other thin film materials and monocrystalline block materials, and can be popularized in a large range.

The use of the ZEP520 e-beam resist and subsequent silicon nitride plays an important role in the preparation of high quality junctions. The ZEP520 electron beam resist has high sensitivity and strong etching resistance which is far higher than that of the common PMMA electron beam resist (the etching rate is about 60nm/min), the selected etching ratio is high, the applicable material range is wide, the preparation of a submicron-sized device can be realized by controlling the exposure condition, the success rate of a sample is high, and the success rate of the micron-sized sample can be close to 100 percent. The silicon nitride is used as the insulating layer, so that the damage to the surface of an oxygen ion sample in the process of depositing silicon dioxide in the traditional process can be avoided, and experiments show that the silicon nitride is easier to strip than the silicon dioxide under the same conditions, and the success rate is higher.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A method of preparing a superconducting josephson junction, the method comprising:

preparing a clean intrinsic silicon substrate;

chemical vapor deposition of Si₃N₄An insulating layer;

removal of positive electron beam resist ZEP520 and Si deposited on said positive electron beam resist ZEP520 by a lift-off process₃N₄Insulating layer, and cleaning the surface of the sample;

2. The production method according to claim 1, wherein the room-temperature resistivity of the intrinsic silicon substrate is greater than 10000 Ω -cm.

3. The method of claim 1, wherein the first Nb layer, the Al-Al layer, and the first Nb layer are sequentially formed on the intrinsic silicon substrate by a magnetron sputtering apparatus₂O₃The layer and the second Nb layer the sample obtained with the three-layer structure specifically included:

cooling for a set time;

in the sample introduction chamberCharging high-purity oxygen with the purity of 5N, setting the pressure to be 1000Pa and the ventilation time to be 60min, carrying out surface oxidation on the Al layer, and forming Al on the surface of the Al layer₂O₃；

Then the mixture is sent into a sputtering cavity of the magnetron sputtering equipment, and the vacuum degree is 1 multiplied by 10^-6Pa below, the working gas is high-purity Ar gas with the purity of 5N, the flow rate is set to be 20sccm, the current is set to be 1500mA, the voltage is set to be 340V, the film coating time is set to be 50s, and the second Nb layer with the film thickness of 50nm +/-10% is prepared.

4. The method of claim 1, wherein the forming junction regions on the three-layered structure by electron beam exposure comprises:

5. The preparation method according to claim 1, wherein the removing of the second Nb layer in the region to be etched by reactive ion etching specifically comprises:

in the reactive ion etching apparatus, the working gas was Ar gas, the gas flow rate was 5.9sccm, and the working gas pressure was 2.0X 10^- ²Pa, ion energy 300eV, acceleration voltage-200V, ion beam current density 50mA/cm²The anode voltage is 45V, and the second Nb layer in the area to be etched, which is not covered by the positive electron beam resist ZEP520, is etched; wherein, every etching time is 1min, cooling is carried out for 5min, so as to avoid coking of the positive electron beam resist ZEP520 in the etching process.

6. The method of claim 1, wherein the chemical vapor deposition of Si₃N₄The insulating layer specifically is:

using an inductively coupled chemical vapor deposition system(ICP-PECVD) with a working gas of 126sccm Ar gas and SiH corresponding to the working gas at a working temperature of 130 DEG C₄ 6.9sccm，NH₃Si is carried out under the conditions of 13sccm, working gas pressure of 1.0Pa and ICP power of 350W₃N₄Chemical vapor deposition of the insulating layer;

wherein, every 45s of deposition, the cooling is carried out for 5 min.

7. The method for preparing a positive electron beam resist ZEP520 according to claim 1, wherein said removing of the positive electron beam resist ZEP520 and Si deposited on the positive electron beam resist ZEP520 by a lift-off process₃N₄The insulating layer specifically is:

8. The method according to claim 1, wherein the surface-cleaned sample is subjected to chemical vapor deposition Si₃N₄An insulating layer for removing Si over the junction region by photolithography and reactive ion etching₃N₄The insulating layer, the contact hole that forms includes specifically:

after cleaning and drying, the sample is subjected to glue coating, prebaking, electron beam exposure, development and fixation to form a contact hole area to be etched;

9. The preparation method according to claim 1, wherein the magnetron sputtering is used for preparing a third Nb layer, and the step of removing the third Nb layer in the region outside the projection region where the contact hole is located by photoetching and reactive ion etching specifically comprises the following steps:

in the sputtering cavity of the magnetron sputtering equipment, the vacuum degree is 1 multiplied by 10^-6The working gas is high-purity Ar gas with the purity of 5N, the flow rate is set to be 20sccm, the current is set to be 1500mA, the voltage is set to be 340V, the coating time is set to be 300s, and a third Nb layer with the thickness of 300nm +/-5% is prepared;

10. A superconducting josephson junction prepared by the method of any one of claims 1 to 9.