CN114628536A - Segmented battery manufacturing method, segmented battery and photovoltaic module - Google Patents
Segmented battery manufacturing method, segmented battery and photovoltaic module Download PDFInfo
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Abstract
According to the manufacturing method of the segmented cell, the edge positions of the intrinsic layer and the doped layer on at least one side of the obtained segmented cell are covered by the transparent conductive film layer after the splitting and cannot be directly exposed to the external environment, so that the edge recombination of the segmented cell can be effectively inhibited, and the FF, VOC, JSC and efficiency of the segmented cell are improved.
Description
Technical Field
The invention relates to the field of photovoltaic manufacturing, in particular to a manufacturing method of a segmented battery, the segmented battery and a photovoltaic assembly.
Background
The demand for efficient solar cells is increasing in the current photovoltaic world. The heterojunction solar cell adopting the amorphous silicon passivation technology combines the characteristics of the crystalline silicon cell and the silicon-based thin film cell, has the advantages of short manufacturing process, low process temperature, high conversion efficiency, more generated energy and the like, and is particularly concerned.
In addition, with the development of the photovoltaic industry, the whole cell is divided into a plurality of segmented cells, and then the solar photovoltaic module is prepared from the segmented cells, so that the resistance loss of the module can be reduced, the density of the module packaging cells (such as a laminated tile module) can be improved, and the efficiency of the solar photovoltaic module can be effectively improved. At present, the preparation method of the split battery generally comprises the steps of preparing a finished battery piece (namely a whole piece) according to a conventional process, and then dividing the whole piece of the battery piece into the split pieces.
However, after the finished whole cell is prepared into a segmented cell by the above method, crystal lattices at the edges of the segmented cell (i.e. the fracture section of the whole segment) are directly exposed, and surface defects formed by exposed surface dangling bonds are effective carrier recombination centers, so that the edge recombination of the segmented cell is generated, and the performance of the cell is reduced. For a heterojunction solar cell, the basic structure of the heterojunction solar cell comprises a silicon substrate and amorphous silicon layers (specifically, an intrinsic amorphous silicon layer and a doped amorphous silicon layer) attached to the two side surfaces of the silicon substrate, when exposed to the outside, dangling bonds with much higher density exist at the edge position of the amorphous silicon layer than at other positions, and the dangling bonds promote carrier recombination and greatly reduce the performance of the segmented heterojunction cell.
In view of the above, there is a need to provide an improved solution to the above problems.
Disclosure of Invention
The invention aims to at least solve one technical problem in the prior art, and in order to achieve the purpose of the invention, the invention provides a method for manufacturing a segmented battery, which is specifically designed as follows.
A method for manufacturing a segmented battery comprises the following steps:
providing a silicon substrate;
forming an intrinsic layer and a doped layer, wherein the intrinsic layer comprises a first intrinsic layer and a second intrinsic layer which are respectively positioned on two different surfaces of the silicon substrate, the doped layer comprises a first doped layer positioned on the outer surface of the first intrinsic layer and a second doped layer positioned on the outer surface of the second intrinsic layer, and the doping type of the second doped layer is opposite to that of the first doped layer;
forming a separation channel on at least one surface side of the silicon substrate, wherein the separation channel extends from the outer surface of the doped layer towards the direction of the silicon substrate in a concave manner and is connected to the silicon substrate;
forming a transparent conductive film layer, wherein the transparent conductive film layer comprises a first transparent conductive film layer positioned on the outer surface of the first doping layer and a second transparent conductive film layer positioned on the outer surface of the second doping layer, and the wall surface of the separation channel is covered by the transparent conductive film layer;
forming a first collector electrode and a second collector electrode respectively positioned on two different surface sides of the silicon substrate, wherein the first collector electrode and the second collector electrode respectively comprise auxiliary gates with extension directions consistent with the extension directions of the separation channels;
and splitting the silicon substrate along the separation channel to form the split cell.
Further, the silicon substrate is an n-type monocrystalline silicon substrate, the first doping layer is an n-type doping layer, the second doping layer is a p-type doping layer, and the separation channel is formed at least on one side where the second doping layer is located.
Furthermore, the separation channels are arranged on the two surface sides of the silicon substrate, the separation channels on the two different surface sides of the silicon substrate are in one-to-one correspondence, and the projection positions of the two corresponding separation channels on one surface of the silicon substrate are the same.
Further, the first collector electrode and the second collector electrode also have main gates vertically connected to the corresponding sub-gates, and the first collector electrode and the second collector electrode respectively have 6 to 18 main gates.
Further, the separation channel is located between two adjacent secondary grids, and the distance between the center line of the separation channel and the two adjacent secondary grids is equal.
Further, the depth of the separation channel is 8-12 μm, and the width is 10-300 μm.
And further, when the silicon substrate is split along the separation channel, cutting the silicon substrate along the separation channel by adopting laser.
Further, the depth of the laser for cutting the silicon substrate along the separation channel is 30% -60% of the thickness of the silicon substrate.
Further, the surface of the silicon substrate where the first intrinsic layer is located is a light receiving surface, and the first doping layer sequentially comprises a first doped amorphous silicon film, a doped amorphous silicon oxide film and a second doped amorphous silicon film with doping concentration higher than that of the first doped amorphous silicon film in a direction from the silicon substrate to the first collector; in a direction from the silicon substrate to the second collector, the second doping layer sequentially includes a third doped amorphous silicon film and a fourth doped amorphous silicon film having a doping concentration higher than that of the third doped amorphous silicon film.
Furthermore, the first intrinsic layer and the second intrinsic layer respectively comprise at least two stacked intrinsic amorphous silicon films, and in two adjacent intrinsic amorphous silicon films, the hydrogen content of the intrinsic amorphous silicon film close to the silicon substrate is greater than that of the intrinsic amorphous silicon film far away from the silicon substrate.
The invention also provides a segmented battery which is manufactured by the manufacturing method of the segmented battery.
The invention also provides a photovoltaic module which comprises the segmented battery manufactured by the segmented battery manufacturing method.
The invention has the beneficial effects that: according to the manufacturing method of the segmented battery, the edge positions of the intrinsic layer and the doped layer on at least one side of the obtained segmented battery are covered by the transparent conductive film layer after the segmented battery is split and cannot be directly exposed to the external environment, so that edge recombination of the segmented battery can be effectively inhibited, and FF, VOC, JSC and efficiency of the segmented battery are improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic front view of a solar cell in which a whole solar cell is split into individual cells;
FIG. 2 is a schematic view of the back side of a whole solar cell being split into individual cells;
FIG. 3 is a schematic view of a silicon substrate with an intrinsic layer and a doped layer formed on the surface thereof;
FIG. 4 is a schematic view showing a silicon substrate having separation channels formed on both surface sides thereof;
FIG. 5 is a schematic view of the structure shown in FIG. 4 with transparent conductive film layers formed on both sides;
FIG. 6 is a schematic diagram of the structure shown in FIG. 5 with a first collector and a second collector formed on both sides of the structure;
FIG. 7 is a schematic structural diagram of a segmented battery;
FIG. 8 is a schematic view of a silicon substrate having separation channels formed on only one surface side;
FIG. 9 is a schematic view of the structure shown in FIG. 8 with transparent conductive film layers formed on both sides;
fig. 10 is a schematic view of the structure shown in fig. 9, in which a first collector electrode and a second collector electrode are formed on both surface sides, respectively.
In the figure, 100 is a segmented cell, 10 is a silicon substrate, 21 is a first intrinsic layer, 31 is a first doped layer, 310 is a first separation channel, 41 is a first transparent conductive film layer, 51 is a first collector, 511 is a front side main gate, 512 is a front side sub-gate, 22 is a second intrinsic layer, 32 is a second doped layer, 320 is a second separation channel, 42 is a second transparent conductive film layer, 52 is a second collector, 521 is a back side main gate, and 522 is a back side sub-gate.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Reference is made to fig. 3-10, which show schematic diagrams of several different states in the implementation of the method for manufacturing a segmented battery according to the present invention.
Specifically, the manufacturing method of the segmented battery comprises the following steps:
a silicon substrate 10 is provided.
An intrinsic layer including a first intrinsic layer 21 and a second intrinsic layer 22 respectively located on two different surfaces of the silicon substrate 10 and doped layers including a first doped layer 31 located on an outer surface of the first intrinsic layer 21 and a second doped layer 32 located on an outer surface of the second intrinsic layer 22 are formed, as shown in fig. 3. The doping type of the second doping layer 32 is opposite to that of the first doping layer 31, and one is n-type doping, namely phosphorus doping is adopted; the other is p-type doping, i.e. boron doping is used.
A separation channel is formed on at least one surface side of the silicon substrate 10, and the separation channel is concavely extended from the outer surface of the doped layer toward the silicon substrate and connected to the silicon substrate 10. Referring to fig. 4, in this embodiment, the isolation channel includes a first isolation channel 310 and a second isolation channel 320, which are formed to extend in the same direction, wherein the first isolation channel 310 extends from the outer surface of the first doped layer 31 to the silicon substrate 10 in a recessed manner and penetrates through the first doped layer 31 and the first intrinsic layer 21, and the second isolation channel 320 extends from the outer surface of the second doped layer 32 to the silicon substrate 10 in a recessed manner and penetrates through the second doped layer 32 and the second intrinsic layer 22; referring to fig. 8, in this embodiment, the isolation channel is formed only on one surface side of the silicon substrate 10, and specifically, the isolation channel includes only the second isolation channel 320 which extends from the outer surface of the second doped layer 32 toward the silicon substrate 10 and penetrates through the second doped layer 32 and the second intrinsic layer 22.
Forming a transparent conductive film layer, where the transparent conductive film layer includes a first transparent conductive film layer 41 located on the outer surface of the first doping layer 31 and a second transparent conductive film layer 42 located on the outer surface of the second doping layer 32, and the wall surface of the separation channel is covered by the transparent conductive film layer, which can be specifically referred to fig. 5 and 9.
Forming a first collector electrode 51 and a second collector electrode 52 respectively located on two different surface sides of the silicon substrate 10, wherein the first collector electrode 51 and the second collector electrode 52 both comprise sub-gates with extension directions consistent with the extension direction of the separation channel; specifically, as shown in fig. 1, 2, 6, and 10, the first collector electrode 51 has a front side sub-gate 512 extending in the same direction as the separation channel, and the second collector electrode 52 has a back side sub-gate 522 extending in the same direction as the separation channel.
The silicon substrate 10 is split along the separation channel to form the divided cell 100 shown in fig. 1 and 2. It is easy to understand that the segmented battery 100 involved in the present invention is a heterojunction battery.
The invention also provides a segmented battery which is manufactured by the manufacturing method of the segmented battery.
Further, the invention also provides a photovoltaic module which comprises the segmented battery manufactured by the segmented battery manufacturing method.
Based on the manufacturing method of the segmented battery provided by the invention, in the obtained segmented battery, the edge positions of the intrinsic layer and the doped layer on at least one side are covered by the transparent conductive film layer after the splitting and can not be directly exposed in the external environment, so that the edge recombination of the segmented battery 10 can be effectively inhibited, and the FF, VOC, JSC and efficiency of the segmented battery are improved.
When the separation channel is formed on both surfaces of the silicon substrate 10, due to the arrangement of the first separation channel 310 and the second separation channel 320, when the first transparent conductive film layer 41 and the second transparent conductive film layer 42 are formed, the first transparent conductive film layer 41 enters the first separation channel 310 and covers the wall surface of the first separation channel 310, and the second transparent conductive film layer 42 enters the second separation channel 320 and covers the wall surface of the second separation channel 320. Thus, the split battery formed after the splitting has the structure shown in fig. 7, that is, the first transparent conductive film layer 41 is formed with the first covering part 410 covering the edges of the first intrinsic layer 21 and the first doped layer 31 at the splitting position, the second transparent conductive film layer 42 is formed with the second covering part 420 covering the edges of the second intrinsic layer 22 and the second doped layer 32 at the splitting position, and the first covering part 410 and the second covering part 420 can prevent the first intrinsic layer 21 and the first doped layer 31, and the second intrinsic layer 22 and the second doped layer 32 from being exposed at the splitting position, and can further optimize the passivation at the splitting position, thereby improving FF, VOC, JSC and efficiency of the split battery 100. It can be understood that the wall of the first isolation channel 310 refers to a wall of the trench surrounding the first isolation channel 310 and corresponding to the first intrinsic layer 21 and the first doped layer 31; accordingly, the wall of the second isolation channel 310 refers to a wall surrounding the second isolation channel 320 and corresponding to the second intrinsic layer 22 and the second doped layer 32.
It can be understood that, when the silicon substrate 10 has only one surface side formed with the separation channel, referring to fig. 10, the separation channel is also covered by the transparent conductive film on the corresponding side, and the corresponding transparent conductive film will also cover the corresponding intrinsic layer and the doped layer after the splitting, so that the edges of the intrinsic layer and the doped layer corresponding to the split cell have a better passivation effect.
In a preferred embodiment of the present invention, the silicon substrate 10 is an n-type single crystal silicon substrate, the first doped layer 31 is an n-type doped layer, the second doped layer 32 is a p-type doped layer, and the separation channel is formed at least on the side of the second doped layer 32. Since the silicon substrate 10 is an n-type monocrystalline silicon substrate and the second doping layer 32 is a p-type doping layer, the pn junction of the whole solar cell is equivalently positioned on the back side of the silicon substrate 10, the edge passivation effect of the pn junction of the solar cell has the greatest influence on the performance of the solar cell, and the separation channel is formed on the side where the second doping layer 32 is positioned, so that the split cell can be ensured to have a better passivation effect at the pn junction position.
In the present invention, when the silicon substrate 10 is cracked along the separation channel, the silicon substrate 10 is cut along the separation channel by using laser. Referring to fig. 6 and 10, the L-dashed line shows the splitting position, which also corresponds to the laser cutting position.
Preferably, in the implementation structure that the silicon substrate 10 is an n-type single crystal silicon substrate, the first doping layer 31 is an n-type doping layer, and the second doping layer 32 is a p-type doping layer, when the separation channels are formed on both side surfaces of the silicon substrate 10 in the present invention, the laser-cut surface in this embodiment is the surface side where the first separation channel 310 is located, that is, the laser cuts the silicon substrate along the first separation channel 310, so that the influence of heat generated during laser cutting of the split piece on the pn junction can be reduced to the greatest extent, and the obtained split battery has the optimal performance.
It is easy to understand that, in the implementation of the present invention, when the separation channels are disposed on both surfaces of the silicon substrate 10, the separation channels located on two different surfaces of the silicon substrate 10 are in one-to-one correspondence, and the projection positions of the two corresponding separation channels on one surface of the silicon substrate 10 are the same. Referring to fig. 4, the first isolation channel 310 corresponds to the second isolation channel 320 one by one, and the projection positions of the corresponding isolation channel 310 and the second isolation channel 320 on one surface of the silicon substrate 10 are the same. According to the invention, the separation channels are arranged on both sides of the silicon substrate 10, so that the edge passivation of the segmented cell can be optimized to the greatest extent, and the whole solar cell can have a better splitting effect.
In the practice of the present invention, the first and second collectors 51 and 52 also have main gates vertically connected to the respective sub-gates. Referring to fig. 1 and 2, the first collector 51 has a front main gate 511 vertically connected to the front sub-gate 512, and the second collector 52 has a back main gate 521 vertically connected to the back sub-gate 522. In a preferred embodiment, the first collector electrode 51 and the second collector electrode 52 have 6 to 18 main grids, respectively, that is, the first collector electrode 51 has 6 to 18 front main grids 511, and the second collector electrode 52 has 6 to 18 back main grids 521; generally, the number of the front main gates 511 is the same as that of the rear main gates 521.
It is understood that in other embodiments of the present invention, the first and second collector electrodes 51 and 52 may not include a main gate structure, i.e. the partitioned battery is a no main gate battery.
Each whole solar cell in the invention can be split into 4-6 strip-shaped split cells 100. The whole solar cell is in a square shape with the side length of 156mm-210mm (a chamfer is allowed at the corner position).
Preferably, in the present invention, the separation channel is located in the middle of two adjacent sub-grids, and the center line of the separation channel is equidistant from the two adjacent sub-grids. Based on the arrangement, when the split piece forms the split battery, the split piece position is located at the right middle position of the two adjacent auxiliary grids, so that the auxiliary grids can be prevented from being damaged during the split piece, the distance between the outermost auxiliary grid and the edge of each split battery is the same, the edge auxiliary grids of each split battery have the same current collecting capacity, and the electrical performance of each split battery can be closer. In this way, a high efficiency photovoltaic module is more easily obtained.
Further preferably, the separation channel in the present invention has a depth of 8-12 μm and a width of 10-300 μm, and the first separation channel 310 and the second separation channel 320 are typically formed by laser grooving. In practical implementation, the thicknesses of the first intrinsic layer 21, the first doped layer 31, the second intrinsic layer 22 and the second doped layer 32 in the present invention are usually in the nanometer level, and the depths of the first isolation channel 310 and the second isolation channel 320 are 8-12 μm, so that a part of the first cover portion 410 and the second cover portion 420 extends onto the silicon substrate 100 and covers the edge of the silicon substrate 100 at the splitting position, thereby further optimizing the edge passivation effect after the splitting of the cell piece 100.
It is understood that the structure shown in fig. 5 is only a schematic diagram, and there is a certain difference from the actual structure. Specifically, in practice, since the depth and width of the first isolation channel 310 and the second isolation channel 320 are much larger than the thickness of the first intrinsic layer 21, the first doped layer 31, the second intrinsic layer 22 and the second doped layer 32, the first transparent conductive film 41 forms a corresponding groove shape at the position of the first isolation channel 310 (i.e. the first transparent conductive film 41 is not in a flat state as shown in the figure); the second transparent conductive film 42 also forms a corresponding groove pattern (i.e., the second transparent conductive film 42 is shown in a non-flat state) at the location of the second separation channel 320.
Further, in the present invention, the laser cuts the silicon substrate along the separation channel to a depth of 30% to 60% of the thickness of the silicon substrate. In specific implementation, one specific splitting mode is as follows: the silicon substrate 10 is first cut by laser to form a cut groove, and then a mechanical stress is applied by a splitting machine to split the cell along the cut groove to form the segmented cell 100. Another specific splitting mode is: firstly, a laser beam is used for scribing a short distance at one end part of the first separation channel 310 or the second separation channel 320 to induce cracks, then another laser beam is used for scanning along a preset direction to locally heat the battery piece, and simultaneously water flow or air flow and the like are introduced along the laser beam to locally cool, so that the generated thermal stress induces the initial cracks to grow and split along the laser scanning direction, and further the segmented battery is formed.
Further preferably, in an embodiment of the present invention, the surface of the silicon substrate 10 where the first intrinsic layer 21 is located is a light receiving surface, i.e. a surface directly receiving sunlight. In a direction from the silicon substrate 10 to the first collector electrode 51, the first doping layer 31 includes a first doped amorphous silicon film, a doped amorphous silicon oxide film, and a second doped amorphous silicon film (not shown) with a doping concentration higher than that of the first doped amorphous silicon film in this order; in a direction from the silicon substrate 10 toward the second collector electrode 52, the second doping layer 32 includes a third doped amorphous silicon film and a fourth doped amorphous silicon film (not shown) having a higher doping concentration than the third doped amorphous silicon film.
For the first doped layer 31 and the second doped layer 32, the first doped amorphous silicon film and the third doped amorphous silicon film near the substrate 10 have relatively low doping concentrations, which can reduce the doping atoms into the corresponding intrinsic amorphous layers (i.e. the first intrinsic layer 21 and the second intrinsic layer 22) to the maximum extent, thereby reducing the defect density of the corresponding intrinsic amorphous layers. The second doped amorphous silicon film and the fourth doped amorphous silicon film, which are far away from the silicon substrate 10, of the first doped layer 31 and the second doped layer 32 are favorable for field passivation due to high doping concentration, and contact resistance between the first doped layer 31 and the second doped layer 32 and corresponding outer layers (i.e., the first transparent conductive film layer 41 and the second transparent conductive film layer 42) can be reduced.
In addition, as for the first doping layer 31, since it is located on the light receiving surface side of the silicon substrate 10, the light transmittance thereof has a great influence on the photoelectric conversion efficiency of the cell, in the embodiment, the doped amorphous silicon oxide film is used to replace part of the amorphous silicon of the doping layer, so that the light transmittance of the first doping layer 31 can be effectively improved, and further, the photoelectric conversion efficiency of the corresponding cell is optimized.
Preferably, in some embodiments of the present invention, the average doping concentration of the first doped layer 31 is less than the average doping concentration of the second doped layer 32. For the heterojunction cell, the light receiving surface is the main surface of the photo-generated current, and the first doping layer 31 has relatively low average concentration, so that the mobility can be higher, and the transmission of the current on the light receiving surface of the heterojunction cell is facilitated; on the back side of the heterojunction cell, the resistance of the heterojunction cell can be reduced due to the relatively high average doping concentration of the second doping layer 32.
Further, the first intrinsic layer 21 and the second intrinsic layer 22 respectively include at least two intrinsic amorphous silicon films stacked, and of the two adjacent intrinsic amorphous silicon films, the hydrogen content of the intrinsic amorphous silicon film close to the silicon substrate 10 is greater than that of the intrinsic amorphous silicon film far from the silicon substrate 10.
It is easy to understand that the intrinsic films of the first intrinsic layer 21 and the second intrinsic layer 22 closer to the silicon substrate 10 have more obvious passivation effect on the intrinsic films, and the intrinsic amorphous silicon film closer to the silicon substrate 10 has the highest hydrogen content, so that the first intrinsic layer 21 and the second intrinsic layer 22 have the optimal passivation effect on the silicon substrate 10. Specifically, the intrinsic amorphous silicon film near the silicon substrate 10 has a higher hydrogen content, and can better passivate dangling bonds at the surface of the silicon substrate 10.
In the present invention, one embodiment of the step of providing the silicon substrate 10 is: selecting an n-type monocrystalline silicon wafer, removing a damage layer by using a KOH aqueous solution with the volume ratio of 15%, forming a pyramid suede structure on the surface of the n-type monocrystalline silicon wafer by using KOH and an anisotropic wool making additive solution, treating the n-type monocrystalline silicon wafer with the pyramid suede structure on the surface by using an ozone aqueous solution with the concentration of 10-50ppm, removing an oxide layer on the surface of the n-type monocrystalline silicon wafer by using a 2% HF solution, and finally washing and drying to obtain the silicon substrate 10. Generally, the height of the pyramid in the pyramid structure is 0.5-3um, and the reflectivity of the texture is about 10%.
The first intrinsic layer 21, the first doped layer 31, the second intrinsic layer 22 and the second doped layer 32 in the present invention may be formed by a PECVD process. Wherein, the thickness of the first intrinsic layer 21 is 4-5nm, the thickness of the first doped layer 31 is 4-5nm, the thickness of the second intrinsic layer 22 is 4-5nm, and the thickness of the second doped layer 32 is 5-6 nm. In practical implementation, the thickness of the second doped layer 32 is greater than that of the first doped layer 31, so that the first doped layer 31 on the light receiving surface has better light transmittance, and the second doped layer 32 on the backlight surface has better conductivity.
In the invention, the first transparent conductive film layer 41 and the second transparent conductive film layer 42 are usually formed on the surfaces of the first doped layer 31 and the second doped layer 32 by PVD deposition, RPD deposition or magnetron sputtering deposition, respectively. In the specific implementation process, the first transparent conductive film layer 41 extends toward the sidewall of the silicon substrate 10, thereby covering the edges of the first doped layer 31 and the first intrinsic layer 21, so as to ensure that the outer edges of the first doped layer 31 and the first intrinsic layer 21 are not exposed (not shown); accordingly, the second transparent conductive film layer 42 also extends toward the sidewall of the silicon substrate 10, thereby covering the edges of the second doped layer 32 and the second intrinsic layer 22 to ensure that the outer edges of the second doped layer 32 and the second intrinsic layer 22 are not exposed.
One specific implementation manner of the first transparent conductive film layer 41 and the second transparent conductive film layer 42 is as follows: heating a deposition chamber of the PVD equipment to 190 ℃; placing the silicon substrate 10 with the first doping layer 31 and the second doping layer 32 on a carrier plate and conveying the silicon substrate into a deposition chamber; ITO (In) is used on the surface of the first doped layer 312O3：SnO297: 3) coating a target to deposit a first transparent conductive film layer 41 with the thickness of 60-80 nm; ITO (In) is adopted on the surface of the second doping layer 322O3：SnO2When the ratio is 90: 10) the target is coated to deposit a second transparent conductive film layer 42 of 60-80 nm.
It can be understood that ITO (In)2O3：SnO297: 3) the target refers to In ITO target material2O3With SnO2The mass proportion is 97: 3, ITO (In)2O3：SnO290: 10) the target refers to In ITO target material2O3With SnO2The mass proportion is 90: 10. oxide SnO doped in first transparent conductive film layer 412The content of (b) is relatively low, so that the light transmittance of the first transparent conductive film layer 41 is better, which is beneficial toThe light receiving effect of the light receiving surface of the heterojunction cell; oxide SnO doped in the second transparent conductive film layer 422The content of (b) is relatively high so that the second transparent conductive film layer 42 has better conductivity, and the contact resistance between the second transparent conductive film layer 42 and the second collector electrode can be optimized.
It is understood that, in other embodiments of the present invention, the first transparent conductive film layer 41 and the second transparent conductive film layer 42 may also be a double-layer film or a multi-layer film, and the specific material of each layer may be adjusted according to the requirement.
In the present invention, one specific way to form the first collector electrode 51 and the second collector electrode 52 is as follows: respectively printing a layer of low-temperature conductive silver paste on the first transparent conductive film layer 41 and the second transparent conductive film layer 42 by a screen printing method, and then sintering at a low temperature of 150-300 ℃ to form good ohmic contact, thereby forming a first collector 51 and a second collector 52.
Referring to fig. 1 and 2, as a preferred embodiment of the present invention, when the surface of the silicon substrate 10 where the first intrinsic layer 21 is located is a light receiving surface, the distribution density of the front side sub-gates 512 is smaller than that of the back side sub-gates 522, for example, the number of the front side sub-gates 512 is 60 to 120, and the number of the back side sub-gates 522 is 80 to 180.
Therefore, the shielding area of the first collector electrode 51 to the silicon substrate 10 is smaller than that of the second collector electrode 52 to the silicon substrate 10, and the effective light receiving area of the high-slice cell can be improved to the greatest extent while the series resistance of the high-slice cell is reduced.
It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.
The above-listed detailed description is only a specific description of a possible embodiment of the present invention, and they are not intended to limit the scope of the present invention, and equivalent embodiments or modifications made without departing from the technical spirit of the present invention should be included in the scope of the present invention.
Claims (12)
1. A method for manufacturing a segmented battery is characterized by comprising the following steps:
providing a silicon substrate;
forming an intrinsic layer and a doped layer, wherein the intrinsic layer comprises a first intrinsic layer and a second intrinsic layer which are respectively positioned on two different surfaces of the silicon substrate, the doped layer comprises a first doped layer positioned on the outer surface of the first intrinsic layer and a second doped layer positioned on the outer surface of the second intrinsic layer, and the doping type of the second doped layer is opposite to that of the first doped layer;
forming a separation channel on at least one surface side of the silicon substrate, wherein the separation channel extends from the outer surface of the doping layer towards the silicon substrate in a concave mode and is connected to the silicon substrate;
forming a transparent conductive film layer, wherein the transparent conductive film layer comprises a first transparent conductive film layer positioned on the outer surface of the first doping layer and a second transparent conductive film layer positioned on the outer surface of the second doping layer, and the wall surface of the separation channel is covered by the transparent conductive film layer;
forming a first collector electrode and a second collector electrode respectively positioned on two different surface sides of the silicon substrate, wherein the first collector electrode and the second collector electrode respectively comprise auxiliary gates with extension directions consistent with the extension directions of the separation channels;
and splitting the silicon substrate along the separation channel to form the split cell.
2. The method for manufacturing the segmented cells according to claim 1, wherein the silicon substrate is an n-type single crystal silicon substrate, the first doped layer is an n-type doped layer, the second doped layer is a p-type doped layer, and the separation channel is formed at least on one side of the second doped layer.
3. The method for manufacturing the segmented battery according to claim 1, wherein the separation channels are disposed on both surfaces of the silicon substrate, the separation channels on two different surfaces of the silicon substrate are in one-to-one correspondence, and the projection positions of the two corresponding separation channels on one surface of the silicon substrate are the same.
4. The method for manufacturing the split cell battery as claimed in claim 1, wherein the first and second current collectors further have main grids vertically connected to the corresponding sub-grids, and the first and second current collectors have 6 to 18 main grids, respectively.
5. The method for manufacturing the segmented battery according to any one of claims 1 to 4, wherein the separation channel is positioned between two adjacent secondary grids, and the center line of the separation channel is equidistant from the two adjacent secondary grids.
6. The method for manufacturing the segmented battery according to any one of claims 1 to 4, wherein the depth of the separation channel is 8 to 12 μm, and the width of the separation channel is 10 to 300 μm.
7. The method for manufacturing the segmented battery according to any one of claims 1 to 4, wherein when the silicon substrate is split along the separation channel, a laser is used for cutting the silicon substrate along the separation channel.
8. The method for manufacturing the sliced battery as claimed in claim 7, wherein the depth of the laser cutting the silicon substrate along the separation channel is 30-60% of the thickness of the silicon substrate.
9. The method for manufacturing the segmented cell according to any one of claims 1 to 4, wherein the surface of the silicon substrate where the first intrinsic layer is located is a light receiving surface, and the first doping layer sequentially comprises a first doped amorphous silicon film, a doped amorphous silicon oxide film and a second doped amorphous silicon film with a doping concentration higher than that of the first doped amorphous silicon film in a direction from the silicon substrate to the first collector electrode; in a direction from the silicon substrate to the second collector, the second doping layer sequentially includes a third doped amorphous silicon film and a fourth doped amorphous silicon film having a doping concentration higher than that of the third doped amorphous silicon film.
10. The method for manufacturing the divided cell according to any one of claims 1 to 4, wherein the first intrinsic layer and the second intrinsic layer respectively comprise at least two layers of intrinsic amorphous silicon films which are stacked, and in two adjacent intrinsic amorphous silicon films, the hydrogen content of the intrinsic amorphous silicon film close to the silicon substrate is greater than that of the intrinsic amorphous silicon film far away from the silicon substrate.
11. A segmented battery manufactured by the method for manufacturing a segmented battery according to any one of claims 1 to 10.
12. A photovoltaic module comprising the segmented cell manufactured by the segmented cell manufacturing method according to any one of claims 1 to 10.
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