CN114628384A - Adjacent layer ring grid nanowire/CMOS structure - Google Patents

Adjacent layer ring grid nanowire/CMOS structure Download PDF

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CN114628384A
CN114628384A CN202111462244.8A CN202111462244A CN114628384A CN 114628384 A CN114628384 A CN 114628384A CN 202111462244 A CN202111462244 A CN 202111462244A CN 114628384 A CN114628384 A CN 114628384A
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pmos
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陈超
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Zhang Heming
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Changshu Xijundian Technology Transfer Co ltd
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    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes

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Abstract

The invention relates to a layer-to-layer gate nanowire/CMOS structure, which comprises: a substrate; an nMOS and a pMOS which are connected in series are arranged on the substrate; the nMOS includes a first nano-body structure and a first gate electrode surrounding the first nano-body structure, and the pMOS includes a second nano-body structure and a second gate electrode surrounding the second nano-body structure; the first nano-body structure and the second nano-body structure are arranged on two adjacent layers and are formed by semiconductor materials with the same conductivity type; the first gate electrode and the second gate electrode are formed of conductive materials having the same work function; the substrate material is bulk Si or SOI; the first nanostructure is made of Si and the second nanostructure is made of SiGe. The nano bodies of the nMOS and the pMOS are made of semiconductor materials with the same conductive type, and the gate electrodes are made of conductive materials with the same work function, so that the nano bodies can be prepared simultaneously, and the performance and the reliability of the CMOS structure and the integrated circuit thereof can be improved.

Description

Adjacent layer ring grid nanowire/sheet CMOS structure
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to an adjacent layer ring grid nanowire/CMOS structure.
Background
As integrated circuit feature sizes break through 10nm, short channel effects and drain induced barrier lowering effects can cause transistor performance to become very unstable. Meanwhile, the leakage current is significantly increased due to the quantum tunneling effect, further deteriorating the performance of the entire device. Moreover, the process is more complicated in the fabrication of transistors at this size, which makes the development of moore's law very challenging.
In order to suppress the short channel Effect, researchers have proposed various novel nano device structures, including a double gate, a triple gate, a pi-type gate, an S-type gate, an omega-type gate and a ring gate, which are expected to improve the performance of the conventional planar MOSFET as the size of the MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device is continuously reduced.
Among the new device structures, a gate-all-around nanowire Field Effect Transistor (GAA NWFET) and a gate-all-around nanowire Field Effect Transistor (GAA NSFET) can better suppress short channel Effect and Drain Induced Barrier Lowering Effect (DIBL) Effect, and thus have a greater development potential, and are compatible with a current CMOS (Complementary Metal Oxide Semiconductor Field Effect Transistor, CMOS) process, which is a promising key structure of the next generation CMOS.
However, the gate-all-around nanowire/chip field effect transistor still has the problems of multiple manufacturing process steps, complex technology, higher cost than the conventional CMOS and the like.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides an adjacent layer gate-all-around nanowire/chip CMOS structure. The technical problem to be solved by the invention is realized by the following technical scheme:
an adjacent layer gate-all-around nanowire/chip CMOS structure, comprising: a substrate; the substrate is provided with an nMOS and a pMOS which are connected in series; the nMOS comprises a first nanostructure and a first gate electrode surrounding the first nanostructure, the pMOS comprises a second nanostructure and a second gate electrode surrounding the second nanostructure;
the first and second nanostructure are disposed on two adjacent layers; and are formed of semiconductor materials of the same conductivity type;
the first gate electrode and the second gate electrode are formed of a conductive material having the same work function;
the substrate material is bulk Si or SOI;
the first nano-structure is made of Si, and the second nano-structure is made of SiGe.
In one embodiment of the present invention, the material of the first and second nano-body structures is an n-type semiconductor material with the same doping concentration.
In one embodiment of the present invention, the material of the first and second nano-body structures is a p-type semiconductor material with the same doping concentration.
In one embodiment of the present invention, the work functions of the first gate electrode and the second gate electrode are in a range of 4.6 to 5.1 eV.
In one embodiment of the present invention, the work functions of the first gate electrode and the second gate electrode are in a range of 4.1 to 4.5 eV.
In one embodiment of the present invention, the first gate electrode and the second gate electrode are the same conductive material.
In one embodiment of the present invention, the first source region and the first drain region of the nMOS are n-type doped, and the second source region and the second drain region of the pMOS are p-type doped.
In one embodiment of the present invention, the first nano-structure includes at least one first nano-body, when the number of the first nano-bodies is greater than or equal to two, all the first nano-bodies are arranged in a stacked manner, the second nano-structure includes at least one second nano-body, when the number of the second nano-bodies is greater than or equal to two, all the second nano-bodies are arranged in a stacked manner.
In one embodiment of the invention, the conductivity types of the first and second nano-body structures are formed during epitaxial growth of the stacked structure, or a subsequent process.
In one embodiment of the present invention, the first and second nanobody structures are prepared at the same time; the first gate electrode and the second gate electrode are simultaneously fabricated at one time.
The invention has the beneficial effects that:
the nMOS and pMOS of the present invention are fabricated on semiconductor materials of the same conductivity type and preferably the same doping concentration, thus eliminating the need to separately dope the semiconductor material forming the nanowires/sheets. Meanwhile, the gate electrodes of the nMOS and the pMOS are made of conductive materials with the same work function, preferably the same conductive material, so that the gate electrode of the nMOS and the gate electrode of the pMOS do not need to be prepared respectively, the adjacent layer gate-all-around nanowire/piece CMOS structure reduces the process steps for preparing the gate-all-around CMOS, reduces the process procedures, reduces the preparation cost and the process difficulty, and is greatly beneficial to enhancing the performance and the reliability of the adjacent layer gate-all-around nanowire/piece CMOS structure and the integrated circuit thereof.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a schematic diagram of a gate-all-around nanowire/chip CMOS with nMOS and pMOS in the same layer provided by the prior art;
FIG. 2 is a schematic diagram of a prior art CMOS structure with nMOS and pMOS on top and bottom adjacent layers;
fig. 3 is a schematic diagram of an adjacent layer gate-all-around nanowire/chip CMOS structure provided in an embodiment of the present invention;
FIG. 4 is a schematic diagram of a neighboring gate-all-around nanowire/CMOS chip structure according to an embodiment of the present invention;
fig. 5a to 5j are schematic diagrams illustrating a process of fabricating a stacked adjacent layer gate-all-around nanowire/CMOS chip according to an embodiment of the present invention;
fig. 6a to 6d are schematic diagrams of another stacked adjacent-layer gate-all-around nanowire/CMOS wafer manufacturing process according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
For better understanding of the present solution, before introducing the neighboring layer gate-all-around nanowire/CMOS structure provided by the present invention, an existing stacked gate-all-around nanowire/CMOS structure will be described first.
The gate-all-around (GAA) is a gate metal surrounding the channel region of the MOSFET, the difference between the gate-all-around nanowire and the gate-all-around nanosheet is that the gate-all-around nanowire is a linear semiconductor, the gate-all-around nanowire is a sheet semiconductor, the nanowire is a nano-scale linear semiconductor material, and the nanosheet is a nano-scale thick sheet semiconductor material.
The ring grid nanowire/sheet CMOS is formed by serially connecting a ring grid nanowire/sheet nMOS and a ring grid nanowire/sheet pMOS, the nanowire/sheet of the ring grid nMOS is a p-type semiconductor, and the nanowire/sheet of the ring grid pMOS is an n-type semiconductor. The nanowire/sheet of the ring-grid nanowire/sheet CMOS can be of a single layer or multiple layers, and when the nanowire/sheet is of a multiple layer, the stacked ring-grid nanowire/sheet CMOS is a stacked ring-grid nanowire/sheet CMOS, and the stacked ring-grid nanowire/sheet CMOS is a structure formed by metalized connection of stacked ring-grid nanowires/sheets nMOS and stacked ring-grid nanowires/sheets pMOS in the vertical direction.
In general, there are two types of stacked gate-all-around nanowire/sheet CMOS structures, the first is nMOS nanowires/sheets and pMOS nanowires/sheets on the same semiconductor layer, for example, see fig. 1, and the second is nMOS nanowires/sheets and pMOS nanowires/sheets on adjacent upper and lower semiconductor layers, for example, see fig. 2. The nano-wire is a nano-linear semiconductor material, and the nano-sheet is a nano-thick sheet semiconductor material.
For a gate-all-around nanowire/sheet CMOS structure, the nanowire/sheet of the nMOS is made of a p-type semiconductor material, and the nanowire/sheet of the pMOS is made of an n-type semiconductor material. The invention takes the example of a method for preparing a nanowire/sheet by a p-type semiconductor material and a nanowire/sheet by an n-type semiconductor material after forming a fin structure, and particularly, processes such as ion implantation or doping are carried out after forming the fin structure on a substrate, so that a p-type fin for preparing nMOS and an n-type fin for preparing pMOS are respectively formed, namely, the fin of the nMOS is p-type, so that p-type doping is needed, a medium is needed to shield a pMOS region during preparation, and the corresponding processes are adopted to carry out p-type doping on the fin of the nMOS region so as to prepare the p-type fin; and the fins of the pMOS are n-type, so n-type doping is needed, a medium is needed to shield the nMOS region during preparation, and the corresponding process is adopted to perform n-type doping on the fins of the pMOS region to prepare the n-type fins. Wherein the fin is as a material forming the nanowire/sheet.
In addition, when the gate electrode is prepared, firstly, gate dielectrics are deposited on the surfaces of the nanowire/sheet of the nMOS and the nanowire/sheet of the pMOS at the same time, and then, gate metals with different work functions are respectively deposited on the surfaces of the gate dielectrics of the nMOS and the gate dielectrics of the pMOS so as to respectively form the gate electrode of the nMOS and the gate electrode of the pMOS.
The ring grid nanosheet is different from the ring grid nanowire only in that the former is nanosheet-shaped, and the latter is nanowire-shaped. Therefore, when the stacked ring gate nano-sheet CMOS is prepared, the stacked ring gate nano-sheet CMOS is different from the stacked ring gate nano-wire CMOS only in the shape of the nano-sheet and the nano-wire.
In summary, in the current manufacturing technology, both the stacked gate-all nanosheets CMOS and the stacked gate-all nanowire CMOS have the following two disadvantages:
1. the nanosheet/wire of the ring grid nMOS and the nanosheet/wire of the ring grid pMOS need semiconductor materials of different conductive types;
2. the gate electrode of the ring gate nanosheet/wire nMOS and the gate electrode of the ring gate nanosheet/wire pMOS require conductive materials of different work functions.
Although only two technologies are used, the implementation of the two key technologies requires independent steps, methods and processes, and the processes are complicated, which not only increases the cost of the process, but also introduces process defects, which affect the performance and reliability of the devices and circuits, and thus, the two key technologies constitute a disadvantage of consistency for various types of ring-gate nanowires/CMOS chips, including stacked ring-gate nanowires/CMOS chips.
In order to solve the above disadvantages of the conventional stacked gate-all-around nanowire/CMOS, embodiments of the present invention provide an adjacent layer gate-all-around nanowire/CMOS structure. This structure will be described in detail below.
Referring to fig. 3, fig. 3 is a schematic diagram of an adjacent layer gate-all-around nanowire/CMOS chip structure according to an embodiment of the present invention, wherein fig. 3(1), fig. 3(3) are cross-sectional views of side views, and fig. 3(2) are cross-sectional views of front views. The adjacent layer gate-all-around nanowire/chip CMOS structure shown in FIG. 3 comprises a substrate 10; an nMOS and a pMOS connected in series are provided on the substrate 10; the nMOS includes a first nano-body structure 20 and a first gate electrode 30 surrounding the first nano-body structure 20, the pMOS includes a second nano-body structure 40 and a second gate electrode 50 surrounding the second nano-body structure 40; the first nano-body structure 20 and the second nano-body structure 40 are arranged on two adjacent layers and are formed by semiconductor materials with the same conductivity type; the first gate electrode 30 and the second gate electrode 50 are formed of conductive materials having the same work function; the material of the substrate 10 is bulk Si or SOI; the material of the first nanostructure 20 is Si and the material of the second nanostructure 40 is SiGe.
In the embodiment of the invention, the substrate 10 is selected to be bulk Si or SOI, the difference is only that the depth of the etched shallow groove is different when the fin structure is formed, and the finally prepared adjacent layer ring gate nanowire/CMOS structure is the same.
The materials of the first nano-structure 20 and the second nano-structure 40 may be semiconductor materials of Si, SiGe, Ge, SiC, iii-iv group, etc., as long as the materials of the first nano-structure 20 and the second nano-structure 40 can be mutually sacrificial materials when a stacked structure can be formed therebetween. In the embodiment of the present invention, the material of the first nano-structure 20 is Si, and the material of the second nano-structure 40 is SiGe, which are the best combinations, and can satisfy the high performance requirements of nMOS and pMOS at the same time.
It should be noted that the thickness and doping concentration of the first nano-body structure 20 and the second nano-body structure 40 should satisfy the requirement of complete depletion under the work function of the gate electrode.
In one embodiment, the materials of the first and second nano- body structures 20 and 40 are n-type semiconductor materials with the same doping concentration, the first source region 60 and the first drain region 70 of nMOS are n-type doped, and the second source region 80 and the second drain region 90 of pMOS are p-type doped.
Further, if the materials of the first nanostructure 20 and the second nanostructure 40 are n-type semiconductor materials with the same doping concentration, the same conductive material with work functions near the valence band top of the n-type semiconductor material is used as the first gate electrode 30 and the second gate electrode 50, and the work functions of the first gate electrode 30 and the second gate electrode 50 are selected to completely exhaust the nanostructure, preferably, the work functions of the first gate electrode 30 and the second gate electrode 50 are in the range of 4.6 to 5.1eV, and the specific value is determined by the parameters of the thickness and the doping concentration of the nanostructure, which is not limited herein. In addition, in order to reduce the process steps and improve the performance and reliability of the adjacent layer of surrounding gate nanowire/CMOS structure circuit, the first gate electrode and the second gate electrode are preferably made of the same conductive material, and the conductive material is made of a gate electrode material commonly used in the existing adjacent layer of surrounding gate nanowire/CMOS structure, which is not limited herein.
In another embodiment, the material of the first and second nano- body structures 20 and 40 is a p-type semiconductor material with the same doping concentration, the first source region 60 and the first drain region 70 of nMOS are n-type doped, and the second source region 80 and the second drain region 90 of pMOS are p-type doped.
Further, if the first nanostructure 20 and the second nanostructure 40 are both prepared on a p-type semiconductor material with the same doping concentration, the same conductive material with work function near the conduction band bottom of the p-type semiconductor material is used for the first gate electrode 30 and the second gate electrode 50, and the work functions of the first gate electrode 30 and the second gate electrode 50 are selected to completely exhaust the nanostructure, preferably, the work functions of the first gate electrode 30 and the second gate electrode 50 are in the range of 4.1 to 4.5eV, and the specific values are determined by the parameters of the thickness of the nanostructure, the doping concentration, and the like, which is not limited herein. Similarly, in order to reduce the process steps and improve the performance and reliability of the circuit with the adjacent-layer gate-all-around nanowire/CMOS structure, the first gate electrode and the second gate electrode are preferably made of the same conductive material, and the conductive material is made of a gate electrode material commonly used in the existing adjacent-layer gate-all-around nanowire/CMOS structure, which is not limited herein.
In an embodiment of the present invention, the first nano-body structure 20 includes at least one first nano-body, when the number of the first nano-bodies is greater than or equal to two, all the first nano-bodies are arranged in a stacked manner, and the second nano-body structure 40 includes at least one second nano-body, when the number of the second nano-bodies is greater than or equal to two, all the second nano-bodies are arranged in a stacked manner.
In the adjacent-layer gate-all-around nanowire/sheet CMOS structure of the embodiment of the present invention, the first nano-body structure 20 and the second nano-body structure 40 are formed of semiconductor materials of the same conductivity type, and the first gate electrode 30 and the second gate electrode 50 are formed of conductive materials of the same work function, so that the nMOS and the pMOS of the embodiment of the present invention can be simultaneously fabricated on the same substrate, that is, the first nano-body structure 20 and the second nano-body structure 40 are simultaneously fabricated at one time, and the first gate electrode 30 and the second gate electrode 50 are simultaneously fabricated at one time. Thus, the conductivity types of the first and second nanostructure may be formed during the epitaxial growth of the stacked structure, or may be formed in a subsequent process.
Referring to fig. 4, fig. 4 is a schematic diagram of a neighboring gate-all-around nanowire/CMOS chip structure according to an embodiment of the present invention. As can be seen from the adjacent layer gate-all-around nanowire/sheet CMOS structure provided by the embodiment of the invention and the graph shown in FIG. 5, when a positive voltage V is applied to a power supplyDAnd when the input end is not connected with voltage, namely when the power supply is suspended, the nMOS and the pMOS are both in a cut-off state, and the adjacent layer of the ring gate nanowire/CMOS structure does not work. When the input end is connected with 0V, the pMOS is conducted, and the output end is at a high level. Then, the pMOS gradually turns off and the nMOS gradually turns on as the input voltage gradually increases from 0V, and when the pMOS is turned off and the nMOS is turned on, the output is outputtedLow level.
The first nano-body structure of nMOS and the second nano-body structure of pMOS of the embodiment of the present invention are prepared on the same conductive type semiconductor material, and have the same or similar doping concentration, preferably the same doping concentration, i.e. the first nano-body structure of nMOS and the second nano-body structure of pMOS are prepared on a p-type semiconductor material with a certain doping concentration, or are prepared on an n-type semiconductor material with a certain doping concentration, so that there is no need to prepare different conductive type semiconductor materials for the nano-sheet/wire of ring gate nMOS and the nano-sheet/wire of ring gate pMOS, respectively, so that the adjacent layer ring gate nano-wire/sheet CMOS structure of the embodiment of the present invention can omit the process of preparing different conductive type semiconductor materials, although seemingly omitting the key process of preparing n-type semiconductor material or p-type semiconductor material, but it can reduce multiple process steps, which is very beneficial and advantageous to shorten the process cycle, control the process error, reduce the chip process cost, and improve the performance and reliability of the device and circuit, and the problem is just one of the core problems that the industry pays attention to and pays long attention to. Meanwhile, because the gate electrodes of the nMOS and the pMOS of the embodiment of the present invention are made of the same conductive material or preferably the same conductive material, when the same conductive material is used as the gate electrode, the gate electrode of the nMOS and the gate electrode of the pMOS do not need to be separately prepared. In addition, the gate electrode region of the adjacent layer ring gate nanowire/piece CMOS structure is a sensitive region, the gate electrode controls the performance of the CMOS, and the process of preparing the gate electrode can influence the performance of the CMOS, so that the gate electrode of the nMOS and the gate electrode of the pMOS adopt the same conductive material with the same work function, and only one preparation is needed, thereby being beneficial to improving the performance and the reliability of the adjacent layer ring gate nanowire/piece CMOS structure circuit.
In summary, the embodiment of the invention simplifies two key process technologies of the adjacent layer of the ring-gate nanowire/CMOS structure, reduces the process steps for preparing the adjacent layer of the ring-gate nanowire/CMOS structure, and reduces the process and process difficulty, thereby reducing the preparation cost, and further improving the yield, performance and reliability of the adjacent layer of the ring-gate nanowire/CMOS structure and the integrated circuit thereof. In addition, the adjacent layer ring gate nanowire/CMOS structure provided by the embodiment of the invention can also increase the threshold voltage regulation dimension, namely, the switching speed is increased.
The following describes a method for manufacturing a neighboring layer gate-all-around nanowire/CMOS chip structure according to an embodiment of the present invention.
Referring to fig. 5a to 5j, fig. 5a to 5j are schematic diagrams illustrating a process for manufacturing a stacked adjacent layer ring gate nanowire/CMOS, according to an embodiment of the present invention, based on the above description, the embodiment of the present invention further provides a method for manufacturing a stacked adjacent layer ring gate nanowire/CMOS, where a nanowire/sheet (second material layer) of nMOS is Si, and a nanowire/sheet (first material layer) of pMOS is SiGe, the method including:
step 1, please refer to fig. 5a, a semiconductor substrate 10 is provided.
Specifically, the semiconductor substrate 10 is SOI.
And 2, epitaxially growing a laminated material.
The stacked material will be nanowires/sheets of stacked gate-all-around CMOS, the conductivity type of the stacked material can be n-type or p-type, and the nMOS and pMOS of the embodiment of the present invention share the same conductivity type of semiconductor material according to the design requirement.
Specifically, referring to fig. 5b, SiGe layers 101 and Si layers 102 are alternately grown on the surface layer of the semiconductor substrate 10.
Further, the SiGe layer 101 and the Si layer 102 have a property of being selectively etchable with respect to each other. In the embodiment of the invention, the first epitaxial layer is made of SiGe, and then Si/SiGe grows alternately. The thickness and number of layers of the laminate in the embodiment of the present invention are in accordance with design requirements, and the embodiment of the present invention is not particularly limited thereto.
The conductive type of the laminated material in the embodiment of the invention can be realized by in-situ doping during laminated epitaxial growth, and can also be finished by processes such as ion implantation, diffusion and the like in the subsequent process.
And 3, forming a fin structure.
Referring to fig. 5c, in which fig. 5c (1) is a front view and fig. 5c (2) is a side view, the SiGe layer 101 and the Si layer 102 are simultaneously etched to etch the first material stack 100 and the second material stack 110, the first material stack 100 and the second material stack 110 are fin structures, and when the SiGe layer 101 and the Si layer 102 are etched, SiO of the SOI can be etched2A surface, wherein a first material stack 100 is used to form the nanowires/flakes of nMOS and a second material stack 110 is used to form the nanowires/flakes of pMOS, the geometric dimensions of the nanowires/flakes being prepared as required by the design.
Step 4, please refer to fig. 5d, wherein fig. 5d (1) and fig. 5d (3) are side views, and fig. 5d (2) is a cross-sectional view, in which a dielectric is deposited between the fin structures of the nMOS region to form a dielectric layer 120, the surface of the dielectric deposited between the fins of the nMOS region is aligned with the lower surface of the first layer SiGe, and no dielectric is deposited between the fins of the pMOS region.
And 5, forming pseudo gate dielectrics and pseudo gate electrodes.
Specifically, referring to fig. 5e, wherein fig. 5e (1) and fig. 5e (2) are side views, a dummy gate dielectric is first formed on first material stack 100 and second material stack 110, and then a dummy gate electrode 140 is formed on the dummy gate dielectric, the dummy gate dielectric is overlapped with dummy gate electrode 140, and dummy gate electrode 140 is formed for the subsequent formation of source and drain electrodes and for determining the channel length.
Step 6, please continue to refer to fig. 5e, wherein fig. 5e (1) and fig. 5e (2) are side views, an isolation layer 150 is formed on the side surface of the pseudo-gate electrode 140, and the isolation layer 150 is used to prevent the gate electrode of the device prepared as described below from being shorted with the source and drain electrodes thereof.
Step 7, please refer to fig. 5f, wherein fig. 5f (1) and fig. 5f (3) are side views, fig. 5f (2) is a cross-sectional view corresponding to fig. 5f (1), and fig. 5f (4) is a cross-sectional view corresponding to fig. 5f (3), the dummy gate electrode 140 and the fin outside the isolation layer 150 on the side surface thereof are etched, the SiGe portion blocked by the isolation layer is etched in the nMOS region by using an anisotropic etching method, the Si portion blocked by the isolation layer is etched in the pMOS region by using an anisotropic etching method, and the isolation layer 160 is formed in the etched sacrificial layer.
Step 8, please refer to fig. 5g, wherein a first source region 60 and a first drain region 70 of nMOS are formed for nMOS epitaxial n-type semiconductor material, and a second source region 80 and a second drain region 90 of pMOS are formed for pMOS epitaxial p-type semiconductor material, respectively, on both sides of the divided spacers of nMOS and pMOS.
Step 9, please refer to fig. 5h, wherein fig. 5h (1) and fig. 5h (2) are side views, pseudogate electrode 140 and the underlying gate-creating medium are etched away, isolation layer 150 on the side of pseudogate electrode 140 is reserved, a fin exposed from the lower surface of gate-creating medium 130 is bare, a SiGe layer in an nMOS region is etched away by using anisotropic etching characteristics of Si and SiGe, the Si layer is left to serve as a nanowire/sheet of nMOS, the Si layer in a pMOS region is etched away, the SiGe layer is left to serve as a nanowire/sheet of pMOS, the Si layer left serves as first nanobody structure 20 of nMOS, and the SiGe layer left serves as second nanobody structure 40 of pMOS.
And 10, depositing a gate dielectric layer and preparing a gate electrode.
Specifically, referring to fig. 5i, wherein fig. 5h (1) and 5h (2) are cross-sectional side views, a gate dielectric layer 170 is first co-deposited around the released bare-drain nMOS Si nanowires/slabs and pMOS SiGe nanowires/slabs; then, a gate metal with the same work function is co-deposited on the gate dielectric layer 170 around the Si nanowires/slabs of nMOS and the SiGe nanowires/slabs of pMOS to form the first gate electrode 30 and the second gate electrode 50.
It should be noted that the specific value of the work function of the gate electrode in the embodiment of the present invention is determined by optimizing the thickness and doping concentration of the nanowire/sheet based on the electrical characteristic requirement, and it is to ensure that the nanowire/sheet is fully depleted under zero offset.
And 11, metallization.
Specifically, please refer to fig. 5j, wherein fig. 5j (1) and 5j (3) are cross-sectional side views, fig. 5j (2) is a cross-sectional front view, and finally, a metallization connection is implemented by a metallization metal 180, the purpose of the metallization is to connect the first gate electrode 30 of the stacked ring-gate nanowire/piece nMOS and the second gate electrode 50 of the pMOS together, and connect the first drain region 70 of the nMOS and the second drain region 90 of the pMOS together, forming a stacked adjacent layer ring-gate nanowire/piece CMOS structure.
It should be noted that the nanowire/sheet in the embodiment of the present invention may be n-type or p-type, and the conductive type of the stacked nanowire/sheet may be formed by in-situ doping during the epitaxial growth of the stacked material, or may be formed in the subsequent process of exposing the material for forming the nanowire/sheet, such as ion implantation, diffusion, and the like.
In addition, when the semiconductor substrate 10 of the embodiment of the present invention is bulk Si, the difference from the semiconductor substrate 10 being bulk SOI is only in step 1 to step 4, and the remaining steps are the same as those when the semiconductor substrate 10 is SOI, so that the embodiment of the present invention only introduces step 1 to step 4 for stacked adjacent-layer gate-all-around nanowire/sheet CMOS in which the semiconductor substrate 10 is bulk Si, and referring to fig. 6a to 6d, when the semiconductor substrate 10 of the embodiment of the present invention is bulk Si, the preparation method includes:
step 1, please refer to fig. 6a, a semiconductor substrate 10 is provided.
Specifically, the semiconductor substrate 10 is bulk Si.
And 2, epitaxially growing a laminated material.
Specifically, referring to fig. 6b, SiGe layers 101 and Si layers 102 are alternately grown on the surface layer of the semiconductor substrate 10.
Further, the SiGe layer 101 and the Si layer 102 have a property of being selectively etchable with respect to each other. In the embodiment of the invention, the first epitaxial layer is made of SiGe, and then Si/SiGe grows alternately. The thickness and the number of layers of the lamination layer in the embodiment of the present invention are according to design requirements, and this is not specifically limited in the embodiment of the present invention.
The conductive type of the laminated material in the embodiment of the invention can be realized by in-situ doping during laminated epitaxial growth, and can also be finished by processes such as ion implantation, diffusion and the like in the subsequent process.
And 3, forming a fin structure.
Referring to fig. 6c, the SiGe layer 101 and the Si layer 102 are etched at the same time to etch a first material stack 100 and a second material stack 110, where the first material stack 100 and the second material stack 110 are fin structures, and when the SiGe layer 101 and the Si layer 102 are etched, the surface of the bulk Si may be etched, or the surface of the bulk Si may be etched, where the first material stack 100 is used to form nano wires/sheets of nMOS, the second material stack 110 is used to form nano wires/sheets of pMOS, and the geometric dimensions of the nano wires/sheets are prepared according to design requirements.
Step 4, please refer to fig. 6d, wherein fig. 6d (1) and 6d (3) are cross-sectional views of side views, and fig. 6d (2) is a cross-sectional view of a front view, and a dielectric layer 120 is formed by depositing a dielectric between the fin structures of the nMOS region and the fin structures of the pMOS region, wherein a surface of the dielectric deposited between the fins of the nMOS region is aligned with a lower surface of the SiGe, and a surface of the dielectric deposited between the fins of the pMOS region is aligned with a lower surface of the Si.
For the semiconductor substrate 10 being bulk Si, the steps after forming the dielectric layer 120 on the bulk Si are the same as the steps for manufacturing the semiconductor substrate 10 being SOI according to the embodiment of the present invention, and are not described herein again.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention relates, several simple deductions or substitutions may be made without departing from the spirit of the invention, which should be construed as belonging to the scope of the invention.

Claims (10)

1. An adjacent layer gate-all-around nanowire/chip CMOS structure, comprising: a substrate; the substrate is provided with an nMOS and a pMOS which are connected in series; the nMOS comprises a first nanostructure and a first gate electrode surrounding the first nanostructure, the pMOS comprises a second nanostructure and a second gate electrode surrounding the second nanostructure;
the first and second nanostructure are disposed on two adjacent layers; and are formed of semiconductor materials of the same conductivity type;
the first gate electrode and the second gate electrode are formed of a conductive material having the same work function;
the substrate material is bulk Si or SOI;
the first nano-structure is made of Si, and the second nano-structure is made of SiGe.
2. The adjacent-layer gate-all-around nanowire/sheet CMOS structure of claim 1, wherein the material of the first nano-body structure and the material of the second nano-body structure are n-type semiconductor materials with the same doping concentration.
3. The adjacent-layer gate-all-around nanowire/sheet CMOS structure of claim 1, wherein the material of the first nano-body structure and the second nano-body structure is p-type semiconductor material with the same doping concentration.
4. The adjacent-layer gate-all-around nanowire/sheet CMOS structure of claim 2, wherein the work functions of the first gate electrode and the second gate electrode are in the range of 4.6-5.1 eV.
5. The adjacent-layer gate-all-around nanowire/sheet CMOS structure of claim 3, wherein the work functions of the first gate electrode and the second gate electrode are in the range of 4.1-4.5 eV.
6. The vicinal-gate-all-around nanowire/slice CMOS structure of claim 1, wherein the first gate electrode and the second gate electrode are the same conductive material.
7. The adjacent-layer gate-all-around nanowire/slice CMOS structure of claim 1, wherein a first source region and a first drain region of the nMOS are doped n-type, and a second source region and a second drain region of the pMOS are doped p-type.
8. The adjacent-layer gate-all-around nanowire/chip CMOS structure according to claim 1, wherein the first nano-body structure comprises at least one first nano-body, when the number of the first nano-bodies is greater than or equal to two, all the first nano-bodies are arranged in a stacked manner, the second nano-body structure comprises at least one second nano-body, when the number of the second nano-bodies is greater than or equal to two, all the second nano-bodies are arranged in a stacked manner.
9. The adjacent-layer gate-all-around nanowire/chip CMOS structure according to claim 1 or 8, wherein the conductivity types of the first and second nano-body structures are formed during the epitaxial growth of the stacked structure or formed in a subsequent process.
10. The adjacent-layer gate-all-around nanowire/chip CMOS structure according to claim 1 or 8, wherein the first nano-body structure and the second nano-body structure are simultaneously prepared at one time; the first gate electrode and the second gate electrode are simultaneously manufactured at one time.
CN202111462244.8A 2020-12-23 2021-12-02 Adjacent layer ring grid nanowire/CMOS structure Withdrawn CN114628384A (en)

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