CN114627920A - Magnetic memory and performance adjusting method thereof - Google Patents
Magnetic memory and performance adjusting method thereof Download PDFInfo
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Abstract
The application discloses a method for adjusting the performance of a magnetic memory, which comprises the steps of receiving a performance adjusting instruction; acquiring a parallel state turning voltage and an anti-parallel state turning voltage of a magnetic tunnel junction when the magnetic tunnel junction is connected with a CMOS circuit in series; and adjusting the parallel state switching voltage or the anti-parallel state switching voltage to adjust the performance of the magnetic tunnel junction. Therefore, after receiving the performance adjusting instruction, the method for adjusting the performance of the magnetic memory obtains the parallel state overturning voltage and the anti-parallel state overturning voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected with the CMOS circuit in series, and adjusts the parallel state overturning voltage or the anti-parallel state overturning voltage, so that the performance of the magnetic memory is adjusted, and the writing difficulty and the erasing resistant times of the magnetic memory are optimized. In addition, the application also provides a magnetic memory.
Description
Technical Field
The present application relates to the field of magnetic memory technologies, and in particular, to a magnetic memory and a performance adjusting method thereof.
Background
Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a new type of Memory, and needs to be integrated with CMOS (Complementary Metal-Oxide-Semiconductor) circuit when in use. The STT-MRAM and the CMOS circuit are integrated in such a way that a Magnetic Tunnel Junction (MTJ) of a basic memory cell of the STT-MRAM is connected in series with a source at one side of one or more CMOS circuits, a drain (drain electrode) is externally connected to a word line (BL), a gate (gate electrode) is connected to a bit line (WL), and a source (source electrode) is connected to a Source Line (SL), as shown in fig. 1.
The switching of the MTJ is driven by current, and because the resistance difference between the parallel state and the anti-parallel state is large, and the switching currents of the two states are different and affected by the CMOS current supply capability, the switching voltages of the two states of the MTJ also have a large difference, as shown in fig. 2, where the abscissa is voltage and the ordinate is resistance. When BL is pressurized and inverted, the CMOS partial pressure is small, the drain voltage is low, the source electrode is grounded, and V isgate-VdrainThe current capacity of the CMOS is higher, the resistance of the CMOS is smaller, and the MTJ partial pressure is higher; when switching from SL pressurization, the CMOS source drain voltage is high due to MTJ partial pressure, Vgate-VdrianLow current capacity of CMOS, increased resistance of CMOS, and low MTJ voltage division. When the source line voltage is increased to a certain degree, the voltage on the MTJ is continuously pressurized to be basically unchanged, so the partial pressure difference of the MTJ in two overturning states is large, and the write-in difficulty of the MTJ is high. On the other hand, normally, the endurance count of the MTJ is significantly lower in one direction than in the other direction, for example, the endurance count from the parallel state to the anti-parallel state is significantly smaller than the endurance count from the anti-parallel state to the parallel state, or the endurance count from the parallel state to the anti-parallel state is significantly larger than the endurance count from the anti-parallel state to the parallel state, resulting in low overall endurance count of the MTJ. However, currently, the two properties of the MTJ cannot be optimally adjusted.
Therefore, how to solve the above technical problems should be a great concern to those skilled in the art.
Disclosure of Invention
The purpose of the present application is to provide a magnetic memory and a performance adjusting method thereof to optimize the performance of the magnetic memory.
In order to solve the above technical problem, the present application provides a method for adjusting performance of a magnetic memory, including:
receiving a performance adjustment instruction;
acquiring a parallel state switching voltage and an anti-parallel state switching voltage of a magnetic tunnel junction when the magnetic tunnel junction is connected with a CMOS circuit in series;
and adjusting the parallel state switching voltage or the anti-parallel state switching voltage to adjust the performance of the magnetic tunnel junction.
Optionally, when the performance adjusting instruction is to reduce the writing difficulty, the adjusting the parallel state switching voltage or the anti-parallel state switching voltage to adjust the performance of the magnetic tunnel junction includes:
determining the magnitude relation between the parallel state overturning voltage and the anti-parallel state overturning voltage;
when the anti-parallel state switching voltage is larger than the parallel state switching voltage, increasing the parallel state switching voltage or reducing the anti-parallel state switching voltage, and adjusting a magnetic bias field of the magnetic tunnel junction in a forward direction to balance the parallel state switching voltage and the anti-parallel state switching voltage;
when the anti-parallel state turning voltage is smaller than the parallel state turning voltage, reducing the parallel state turning voltage or increasing the anti-parallel state turning voltage, and adjusting the magnetic bias field to the negative direction to balance the parallel state turning voltage and the anti-parallel state turning voltage;
the magnetic tunnel junction at least comprises a pinning layer, a reference layer, a tunneling layer and a free layer, wherein the direction of the magnetic bias field points to the same direction of the magnetic moment of the reference layer as a positive direction.
Optionally, when the performance adjusting instruction is to increase the endurance number, the adjusting the parallel state switching voltage or the anti-parallel state switching voltage to adjust the performance of the magnetic tunnel junction includes:
obtaining a first endurance writing time from a parallel state to an antiparallel state and a second endurance writing time from the antiparallel state to the parallel state of the magnetic tunnel junction;
determining a magnitude relationship of the first endurance count and the second endurance count;
when the first endurance writing times are larger than the second endurance writing times, increasing the parallel state switching voltage or reducing the anti-parallel state switching voltage, and adjusting the magnetic bias field of the magnetic tunnel junction in the forward direction to balance the first endurance writing times and the second endurance writing times;
when the first endurance writing times are less than the second endurance writing times, reducing the parallel state overturning voltage or increasing the anti-parallel state overturning voltage, and adjusting the magnetic bias field to the negative direction so as to balance the first endurance writing times and the second endurance writing times;
the magnetic tunnel junction at least comprises a pinning layer, a reference layer, a tunneling layer and a free layer, and the direction of the magnetic bias field points to the same direction of the magnetic moment of the reference layer as a positive direction.
Optionally, the increasing the parallel state flipping voltage or decreasing the anti-parallel state flipping voltage includes:
the number of layers of the first ferromagnetic repeat unit in the pinned layer is decreased or the number of layers of the second ferromagnetic repeat unit in the reference layer is increased.
Optionally, the increasing the parallel state flipping voltage or decreasing the anti-parallel state flipping voltage includes:
reducing an etching angle of the magnetic tunnel junction, wherein a thickness of the reference layer is greater than a thickness of the pinning layer.
Optionally, the increasing the parallel state flipping voltage or decreasing the anti-parallel state flipping voltage includes:
adjusting a first material of a first ferromagnetic repeat unit or adjusting a second material of a second ferromagnetic repeat unit such that a saturation magnetization of the first material is less than a saturation magnetization of the second material.
Optionally, the decreasing the parallel state flipping voltage or increasing the anti-parallel state flipping voltage includes:
increasing the number of layers of the first ferromagnetic repeating unit in the pinned layer or decreasing the number of layers of the second ferromagnetic repeating unit in the reference layer.
Optionally, the decreasing the parallel state flipping voltage or increasing the anti-parallel state flipping voltage includes:
and increasing the etching angle of the magnetic tunnel junction, wherein the thickness of the reference layer is not more than that of the pinning layer.
Optionally, the decreasing the parallel state flipping voltage or increasing the anti-parallel state flipping voltage includes:
adjusting a first material of a first ferromagnetic repeat unit or adjusting a second material of a second ferromagnetic repeat unit such that a saturation magnetization of the first material is greater than a saturation magnetization of the second material.
Optionally, the method further includes:
and thinning the thickness of the first ferromagnetic repeating unit or increasing the thickness of the second ferromagnetic repeating unit.
Optionally, the method further includes:
increasing the thickness of the first ferromagnetic repeating unit or decreasing the thickness of the second ferromagnetic repeating unit.
Optionally, the obtaining of the parallel state switching voltage and the antiparallel state switching voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected in series with the CMOS circuit includes:
measuring the testkey of the series connection of the magnetic tunnel junction and the CMOS circuit to obtain the parallel state turning voltage and the anti-parallel state turning voltage;
or, performing circuit simulation on the series circuit of the magnetic tunnel junction and the CMOS circuit, and inputting the electrical parameters of the magnetic tunnel junction to obtain the parallel state switching voltage and the anti-parallel state switching voltage.
Optionally, the reference layer is CoxFeyBzAnd (CoPt)nWherein n is more than or equal to 1; the pinning layer is (CoPt)mA magnetic layer, wherein m is not less than 1 and m>n。
The present application also provides a magnetic memory for implementing any of the above-described magnetic memory performance adjusting methods.
The method for adjusting the performance of the magnetic memory comprises the steps of receiving a performance adjusting instruction; acquiring a parallel state switching voltage and an anti-parallel state switching voltage of a magnetic tunnel junction when the magnetic tunnel junction is connected with a CMOS circuit in series; and adjusting the parallel state switching voltage or the anti-parallel state switching voltage to adjust the performance of the magnetic tunnel junction.
Therefore, after receiving the performance adjusting instruction, the method for adjusting the performance of the magnetic memory obtains the parallel state overturning voltage and the anti-parallel state overturning voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected with the CMOS circuit in series, and adjusts the parallel state overturning voltage or the anti-parallel state overturning voltage, so that the performance of the magnetic memory is adjusted, and the writing difficulty and the erasing resistant times of the magnetic memory are optimized.
In addition, the application also provides a magnetic memory.
Drawings
For a clearer explanation of the embodiments or technical solutions of the prior art of the present application, the drawings needed for the description of the embodiments or prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a circuit diagram of a magnetic tunnel junction in series with a CMOS circuit;
FIG. 2 is a schematic diagram of switching voltages for parallel and antiparallel states of a magnetic tunnel junction;
FIG. 3 is a flow chart of a method for adjusting performance of a magnetic memory according to an embodiment of the present application;
FIG. 4 is a flow chart of another method for adjusting the performance of a magnetic memory according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a magnetic tunnel junction structure;
FIG. 6 is a schematic illustration of a magnetic bias field;
FIG. 7 is a schematic structural diagram of a magnetic tunnel junction at a small etching angle;
FIG. 8 is a schematic structural diagram of a magnetic tunnel junction at a large etching angle
FIG. 9 is a flow chart of another method for adjusting the performance of a magnetic memory according to an embodiment of the present application;
FIG. 10 is a schematic diagram of the adjustment of the magnetic bias field when the first endurance count is greater than the second endurance count;
FIG. 11 is a schematic diagram illustrating adjustment of the anti-parallel state switching voltage when the first endurance count is greater than the second endurance count.
Detailed Description
In order that those skilled in the art will better understand the disclosure, the following detailed description will be given with reference to the accompanying drawings. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
As described in the background section, when the MTJ is flipped from BL under voltage, the CMOS voltage division is small, the drain voltage is low, the source is grounded, Vgate-VdrainThe current capacity of the CMOS is higher, the resistance of the CMOS is smaller, and the MTJ partial pressure is higher; when switching from SL pressurization, the CMOS source drain voltage is high due to MTJ partial pressure, Vgate-VdrianLow current capacity of CMOS, increased resistance of CMOS, and low MTJ voltage division. When the source line voltage is increased to a certain degree, the voltage on the MTJ is continuously pressurized to be basically unchanged, so the partial pressure difference of the MTJ in two overturning states is large, and the write-in difficulty of the MTJ is high. On the other hand, the endurance count of the MTJ is typically significantly lower in one direction than in the other, resulting in a low overall endurance count of the MTJ. However, at present, it is not possible to optimally adjust these two properties of the MTJ.
In view of the above, the present application provides a method for adjusting performance of a magnetic memory, please refer to fig. 3, where fig. 3 is a flowchart of a method for adjusting performance of a magnetic memory according to an embodiment of the present application, the method including:
step S101: a performance adjustment instruction is received.
Step S102: and acquiring the parallel state turning voltage and the anti-parallel state turning voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected with the CMOS circuit in series.
The magnetic tunnel junction includes at least a pinned layer, a reference layer, a tunnel layer and a free layer, the reference layer and the pinned layer are strongly antiferromagnetically coupled by an antiferromagnetically coupling layer so that their magnetic moments are arranged in antiparallel. The parallel state overturning voltage is a voltage which is required to be added for overturning the magnetic moment of the free layer from the direction parallel to the magnetic moment of the reference layer to the anti-parallel direction; the antiparallel state switching voltage is the voltage required to switch the magnetic moment of the free layer from antiparallel to the magnetic moment of the reference layer to parallel.
Optionally, the obtaining of the parallel state switching voltage and the antiparallel state switching voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected in series with the CMOS circuit includes:
and measuring the testkey of the magnetic tunnel junction and the CMOS circuit in series to obtain the parallel state turning voltage and the anti-parallel state turning voltage.
Or, performing circuit simulation on the series circuit of the magnetic tunnel junction and the CMOS circuit, and inputting the electrical parameters of the magnetic tunnel junction to obtain the parallel state switching voltage and the anti-parallel state switching voltage.
The electrical parameter of the magnetic tunnel junction includes, but is not limited to, a parallel state switching voltage V when the magnetic tunnel junction is not connected to the CMOS circuitc-P to APAntiparallel switching voltage Vc-AP to PParallel state resistance RpAntiparallel state resistor RapCoercivity Hc, Hoff values.
Specifically, the applied gate voltage VWLMay be 1.6V.
When the magnetic tunnel junction is connected with the CMOS circuit in series, the parallel state switching voltage of the magnetic tunnel junction is recorded as VSL-P to APThe antiparallel switching voltage is denoted as VBL-AP to P。
Step S103: and adjusting the parallel state switching voltage or the anti-parallel state switching voltage to adjust the performance of the magnetic tunnel junction.
According to the magnetic memory performance adjusting method, after a performance adjusting instruction is received, the parallel state overturning voltage and the anti-parallel state overturning voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected with the CMOS circuit in series are obtained, and the parallel state overturning voltage or the anti-parallel state overturning voltage is adjusted, so that the performance of the magnetic memory is adjusted, and the writing difficulty and the scratch-resistant times of the magnetic memory are optimized.
The method for adjusting the performance of the magnetic memory according to the different performance adjustment instructions is explained in detail below.
First, when the performance adjusting command is to reduce the difficulty of writing, please refer to fig. 4, where fig. 4 is a flowchart of another method for adjusting performance of a magnetic memory according to an embodiment of the present application, the method includes:
step S201: a performance adjustment instruction is received.
Step S202: and acquiring the parallel state turning voltage and the anti-parallel state turning voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected with the CMOS circuit in series.
Step S203: and determining the magnitude relation between the parallel state overturning voltage and the anti-parallel state overturning voltage.
Step S204: and when the anti-parallel state overturning voltage is larger than the parallel state overturning voltage, increasing the parallel state overturning voltage or reducing the anti-parallel state overturning voltage, and adjusting the magnetic bias field of the magnetic tunnel junction in the forward direction to balance the parallel state overturning voltage and the anti-parallel state overturning voltage.
As shown in fig. 5, the magnetic tunnel junction includes a free layer 1, a reference layer 2, and a pinned layer 3, the magnetization directions of the free layer 1, the reference layer 2, and the pinned layer 3 being perpendicular magnetizations; the magnetic bias field is equivalent to a static magnetic field applied to the free layer by the integration of stray fields generated by other magnetic layers outside the free layer of the magnetic tunnel junction, and the MTJ is more stable in a certain state due to the directionality of the magnetic bias field, as shown in fig. 6. The magnetic bias field affects the electrical switching, and when the MTJ magnetic bias field is biased to a certain state, the switching voltage of the state increases, and vice versa, the switching voltage decreases.
Optionally, there are three ways to increase the parallel state flipping voltage or decrease the anti-parallel state flipping voltage, which are described below respectively.
First, the number of layers of the first ferromagnetic repeating unit in the pinned layer is decreased or the number of layers of the second ferromagnetic repeating unit in the reference layer is increased. At this time, the Hoff value is adjusted in the forward direction, and the magnetic bias field is adjusted in the forward direction.
When the antiparallel state flips the voltage VBL-AP to PGreater than the parallel-state switching voltage VSL-P to APIn the meantime, it is necessary to reduce the antiparallel switching voltage V when the magnetic tunnel junction is not connected to the CMOS circuitc-AP to PThe stray field generated by the pinning layer can be reduced by reducing the number of layers of the first ferromagnetic repeating unit in the pinning layer, the direction of the stray field generated by the pinning layer is opposite to the direction of the magnetic moment of the reference layer, namely the direction of the stray field generated by the pinning layer is negative, the stray field generated by the reference layer can be increased by increasing the number of layers of the second ferromagnetic repeating unit in the reference layer, the direction of the stray field of the reference layer is the same as the direction of the magnetic moment of the reference layer, namely the direction of the stray field generated by the reference layer is positive, and the Hoff value is adjusted towards positive, so that the magnetic bias field is adjusted towards positive, and the parallel state reversal voltage V is adjusted towards positiveSL-P to APIncreasing and antiparallel state switching voltage VBL-AP to PBecome smaller, VSL-P to APAnd VBL-AP to PThe difference between the two is reduced to realize VSL-P to APAnd VBL-AP to PThe sizes are substantially equal.
Second, an etching angle of the magnetic tunnel junction is reduced, wherein a thickness of the reference layer is greater than a thickness of the pinning layer.
It will be appreciated that in this case the reference layer and the pinned layer have the same other parameters and the thickness is a single variable.
When the antiparallel state flips the voltage VBL-AP to PGreater than the parallel-state switching voltage VSL-P to APWhen the thickness of the reference layer in the magnetic tunnel junction is larger than that of the pinning layer, the schematic structural diagram of the magnetic tunnel junction is shown in fig. 7 by reducing the etching angle, so that the volume of the reference layer is larger than that of the pinning layer, the direction of a stray field generated by the pinning layer is negative, the direction of the stray field generated by the reference layer is positive, and the Hoff value is adjusted to be positive, so that the magnetic bias field is adjusted to be positive, and the antiparallel state switching voltage V is adjusted to be positiveBL-AP to PReduced, parallel state switching voltage VSL-P to APBecomes large to realize VSL-P to APAnd VBL-AP to PThe sizes are substantially equal.
Third, the first material of the first ferromagnetic repeat unit or the second material of the second ferromagnetic repeat unit is adjusted such that the saturation magnetization of the first material is less than the saturation magnetization of the second material.
It should be noted that the types of the first material and the second material are not specifically limited in this application, as long as the saturation magnetization of the first material is ensured to be smaller than that of the second material.
When the antiparallel state flips the voltage VBL-AP to PGreater than the parallel state flip voltage VSL-P to APThe saturation magnetization of the first material is less than the saturation magnetization of the second material so that the total magnetic moment of the pinned layer is less than the total magnetic moment of the reference layer, the Hoff value being adjusted in the forward direction so that the magnetic bias field is adjusted in the forward direction.
Optionally, for the first and second modes, the reference layer is CoxFeyBzAnd (CoPt)nWherein n is more than or equal to 1; the pinning layer is (CoPt)mA magnetic layer, wherein m is not less than 1 and m>n is the same as the formula (I). Accordingly, the ferromagnetic repeat units are CoPt thin film layers.
Step S205: when the anti-parallel state turning voltage is smaller than the parallel state turning voltage, reducing the parallel state turning voltage or increasing the anti-parallel state turning voltage, and adjusting the magnetic bias field to the negative direction to balance the parallel state turning voltage and the anti-parallel state turning voltage; the magnetic tunnel junction at least comprises a pinning layer, a reference layer, a tunneling layer and a free layer, and the direction of the magnetic bias field points to the same direction of the magnetic moment of the reference layer as a positive direction.
Optionally, there are three ways to decrease the parallel state flipping voltage or increase the anti-parallel state flipping voltage, which are described below respectively.
First, the number of layers of the first ferromagnetic repeating unit in the pinned layer is increased or the number of layers of the second ferromagnetic repeating unit in the reference layer is decreased.
The stray field generated by the pinning layer can be increased by increasing the number of layers of the first ferromagnetic repeating unit in the pinning layer, the direction of the stray field generated by the pinning layer is opposite to the direction of the magnetic moment of the reference layer, namely the direction of the stray field generated by the pinning layer is negative, the stray field generated by the reference layer can be reduced by reducing the number of layers of the second ferromagnetic repeating unit in the reference layer, the direction of the stray field of the reference layer is the same as the direction of the magnetic moment of the reference layer, namely the direction of the stray field generated by the reference layer is positive, and the Hoff value is adjusted towards negative direction, so that the magnetic bias field is adjusted towards negative direction, and the parallel state switching voltage V is adjusted towards negative directionSL-P to APDiminished antiparallel state switching voltage VBL-AP to PBecome large, VSL-P to APAnd VBL-AP to PThe difference between the two is reduced to realize VSL-P to APAnd VBL-AP to PThe sizes are substantially equal.
Secondly, the etching angle of the magnetic tunnel junction is increased, wherein the thickness of the reference layer is not more than that of the pinning layer.
When the antiparallel state flips the voltage VBL-AP to PLess than the parallel-state switching voltage VSL-P to APWhen the thickness of the reference layer is not larger than that of the pinning layer, the etching angle of the magnetic tunnel junction is increased, the schematic structural diagram of the magnetic tunnel junction is shown in fig. 8, the larger the etching angle is, the larger the volume difference between the pinning layer and the reference layer is, the direction of a stray field generated by the pinning layer is negative, the direction of the stray field generated by the reference layer is positive, and the Hoff value is adjusted to the negative, so that the magnetic bias field is adjusted to the negative, and the antiparallel state reverse voltage V is adjusted to the negativeBL-AP to PIncreased, parallel state reversal voltage VSL-P to APIs made smaller to realize VSL-P to APAnd VBL-AP to PThe sizes are substantially equal.
Third, the first material of the first ferromagnetic repeat unit or the second material of the second ferromagnetic repeat unit is adjusted such that the saturation magnetization of the first material is greater than the saturation magnetization of the second material.
It should be noted that the types of the first material and the second material are not particularly limited in this application as long as the saturation magnetization of the first material is ensured to be larger than that of the second material.
When the antiparallel state flips the voltage VBL-AP to PLess than the parallel-state switching voltage VSL-P to APThe saturation magnetization of the first material is greater than the saturation magnetization of the second material, such that the total magnetic moment of the pinned layer is greater than the total magnetic moment of the reference layer, and the Hoff value is adjusted in the negative direction, such that the magnetic bias field is adjusted in the negative direction.
Optionally, for the first and second modes, the reference layer is CoxFeyBzAnd (CoPt)nWherein n is more than or equal to 1; the pinning layer is (CoPt)mA magnetic layer, wherein m is not less than 1 and m>n is the same as the formula (I). Accordingly, the ferromagnetic repeat units are CoPt thin film layers.
In this embodiment, the parallel state switching voltage and the antiparallel state switching voltage are adjusted to balance the parallel state switching voltage and the antiparallel state switching voltage, so that the difficulty of switching between the parallel state and the antiparallel state is reduced, and the difficulty of writing in the magnetic memory is reduced. Wherein the difference between the parallel state switching voltage and the anti-parallel state switching voltage of the adjusted magnetic memory is less than 10%.
Further, on the basis of the above-mentioned embodiments, in an embodiment of the present application, when the adjustment is performed in such a manner that the number of layers of the first ferromagnetic repeating unit in the pinned layer is decreased or the number of layers of the second ferromagnetic repeating unit in the reference layer is increased, the method further includes:
and thinning the thickness of the first ferromagnetic repeating unit or increasing the thickness of the second ferromagnetic repeating unit.
Further, on the basis of the above-described embodiments, in an embodiment of the present application, when increasing the number of layers of the first ferromagnetic repeating unit in the pinned layer or decreasing the number of layers of the second ferromagnetic repeating unit in the reference layer is adopted, the method further includes:
increasing the thickness of the first ferromagnetic repeating unit or decreasing the thickness of the second ferromagnetic repeating unit.
The first ferromagnetic repeating unit and the second ferromagnetic repeating unit are fixed in composition, so that the first ferromagnetic repeating unit is increased or decreasedThe number of layers of the first ferromagnetic repeating unit and the second ferromagnetic repeating unit is too large to adjust the Hoff value continuously, so that the continuous adjustment of the magnetic bias field cannot be realizedSL-P to APAnd an antiparallel state switching voltage VBL-AP to PThe two are closer together.
Note that when the thicknesses of the first ferromagnetic repeating unit and the second ferromagnetic repeating unit are adjusted, the thickness adjustment needs to be within a certain range to maintain the magnetic stability.
Secondly, when the performance adjusting command is to increase the endurance count, please refer to fig. 9, where fig. 9 is a flowchart of another method for adjusting performance of a magnetic memory according to an embodiment of the present application, the method includes:
step S301: a performance adjustment instruction is received.
Step S302: and acquiring the parallel state turning voltage and the anti-parallel state turning voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected with the CMOS circuit in series.
Step S303: and obtaining a first endurance writing time of the magnetic tunnel junction from a parallel state to an anti-parallel state and a second endurance writing time of the magnetic tunnel junction from the anti-parallel state to the parallel state.
Step S304: determining a magnitude relationship of the first endurance count and the second endurance count.
Step S305: and when the first endurance writing times are greater than the second endurance writing times, increasing the parallel state switching voltage or reducing the anti-parallel state switching voltage, and adjusting the magnetic bias field of the magnetic tunnel junction in the forward direction to balance the first endurance writing times and the second endurance writing times.
Optionally, there are three ways to increase the parallel state flipping voltage or decrease the anti-parallel state flipping voltage, which are described below respectively.
First, the number of layers of the first ferromagnetic repeating unit in the pinned layer is decreased or the number of layers of the second ferromagnetic repeating unit in the reference layer is increased. At this time, the Hoff value is adjusted in the forward direction, and the magnetic bias field is adjusted in the forward direction.
When the antiparallel state flips the voltage VBL-AP to PGreater than the parallel-state switching voltage VSL-P to APIn the meantime, it is necessary to reduce the antiparallel switching voltage V when the magnetic tunnel junction is not connected to the CMOS circuitc-AP to PThe stray field generated by the pinning layer can be reduced by reducing the number of layers of the first ferromagnetic repeating unit in the pinning layer, the direction of the stray field generated by the pinning layer is opposite to the direction of the magnetic moment of the reference layer, namely the direction of the stray field generated by the pinning layer is negative, the stray field generated by the reference layer can be increased by increasing the number of layers of the second ferromagnetic repeating unit in the reference layer, the direction of the stray field of the reference layer is the same as the direction of the magnetic moment of the reference layer, namely the direction of the stray field generated by the reference layer is positive, and the Hoff value is adjusted to the positive direction, so that the magnetic bias field is adjusted to the positive direction, and the parallel state switching voltage V is adjusted to the positive directionSL-P to APIncreasing and antiparallel state switching voltage VBL-AP to PBecome smaller, VSL-P to APAnd VBL-AP to PThe difference between the two is reduced to realize VSL-P to APAnd VBL-AP to PThe sizes are substantially equal.
Second, an etching angle of the magnetic tunnel junction is reduced, wherein a thickness of the reference layer is greater than a thickness of the pinning layer.
It will be appreciated that in this case the reference layer and the pinned layer have the same other parameters and the thickness is a single variable.
When the antiparallel state flips the voltage VBL-AP to PGreater than the parallel-state switching voltage VSL-P to APWhen the thickness of the reference layer in the magnetic tunnel junction is larger than that of the pinning layer, by reducing the etching angle, the schematic structural diagram of the magnetic tunnel junction is shown in fig. 7, the volume of the reference layer is larger than that of the pinning layer, the direction of a stray field generated by the pinning layer is negative, the direction of the stray field generated by the reference layer is positive, and the Hoff value is adjusted to the positive direction, so that the magnetic bias field is adjusted to the positive direction, and the antiparallel state flip voltage V is adjusted to the positive directionBL-AP to PReduced, parallel state switching voltage VSL-P to APBecomes large to realize VSL-P to APAnd VBL-AP to PThe sizes are substantially equal.
Third, the first material of the first ferromagnetic repeating unit or the second material of the second ferromagnetic repeating unit is adjusted so that the saturation magnetization of the first material is smaller than the saturation magnetization of the second material.
It should be noted that the types of the first material and the second material are not specifically limited in this application, as long as the saturation magnetization of the first material is ensured to be smaller than that of the second material. For example, when the first material uses a material with low saturation magnetization, such as inserting a non-magnetic metal layer in CoFeB or doping a non-magnetic material, the second material uses a material with high saturation magnetization, such as CoFe alloy or (Co)xFe1-x)yB1-yWherein x is 0.2-0.7 and y is 0.5-1.
When the antiparallel state flips the voltage VBL-AP to PGreater than the parallel-state switching voltage VSL-P to APThe saturation magnetization of the first material is less than the saturation magnetization of the second material so that the total magnetic moment of the pinned layer is less than the total magnetic moment of the reference layer, the Hoff value being adjusted in the forward direction so that the magnetic bias field is adjusted in the forward direction.
Optionally, for the first and second modes, the reference layer is CoxFeyBzAnd (CoPt)nWherein n is more than or equal to 1; the pinning layer is (CoPt)mA magnetic layer, wherein m is not less than 1 and m>n is the same as the formula (I). Accordingly, the ferromagnetic repeat units are CoPt thin film layers.
When the first endurance count is greater than the second endurance count, please refer to fig. 10 and fig. 11 for the adjustment of the magnetic bias field and the anti-parallel state flip voltage, respectively.
Step S306: when the first endurance writing times are less than the second endurance writing times, reducing the parallel state overturning voltage or increasing the anti-parallel state overturning voltage, and adjusting the magnetic bias field to the negative direction so as to balance the first endurance writing times and the second endurance writing times; the magnetic tunnel junction at least comprises a pinning layer, a reference layer, a tunneling layer and a free layer, and the direction of the magnetic bias field points to the same direction of the magnetic moment of the reference layer as a positive direction.
Optionally, there are three ways to decrease the parallel state flipping voltage or increase the anti-parallel state flipping voltage, which are described below respectively.
First, the number of layers of the first ferromagnetic repeating unit in the pinned layer is increased or the number of layers of the second ferromagnetic repeating unit in the reference layer is decreased.
The stray field generated by the pinning layer can be increased by increasing the number of layers of the first ferromagnetic repeating unit in the pinning layer, the direction of the stray field generated by the pinning layer is opposite to the direction of the magnetic moment of the reference layer, namely the direction of the stray field generated by the pinning layer is negative, the stray field generated by the reference layer can be reduced by reducing the number of layers of the second ferromagnetic repeating unit in the reference layer, the direction of the stray field of the reference layer is the same as the direction of the magnetic moment of the reference layer, namely the direction of the stray field generated by the reference layer is positive, and the Hoff value is adjusted towards negative direction, so that the magnetic bias field is adjusted towards negative direction, and the parallel state switching voltage V is adjusted towards negative directionSL-P to APDiminished antiparallel state switching voltage VBL-AP to PBecome large, VSL-P to APAnd VBL-AP to PThe difference between the two is reduced to realize VSL-P to APAnd VBL-AP to PThe sizes are substantially equal.
Secondly, the etching angle of the magnetic tunnel junction is increased, wherein the thickness of the reference layer is not more than that of the pinning layer.
When the antiparallel state flips the voltage VBL-AP to PLess than the parallel-state switching voltage VSL-P to APWhen the thickness of the reference layer is not larger than that of the pinning layer, the etching angle of the magnetic tunnel junction is increased, the structural schematic diagram of the magnetic tunnel junction is shown in FIG. 8, the larger the etching angle is, the larger the volume difference between the pinning layer and the reference layer is, the direction of a stray field generated by the pinning layer is negative, the direction of the stray field generated by the reference layer is positive, and the Hoff value is adjusted to be negative, so that the magnetic bias field is adjusted to be negative, and the antiparallel state switching voltage V is adjusted to be negativeBL-AP to PIncreased parallel state switching voltage VSL-P to APIs made smaller to realize VSL-P to APAnd VBL-AP to PThe sizes are substantially equal.
Third, the first material of the first ferromagnetic repeat unit or the second material of the second ferromagnetic repeat unit is adjusted such that the saturation magnetization of the first material is greater than the saturation magnetization of the second material.
It should be noted that the types of the first material and the second material are not particularly limited in this application as long as the saturation magnetization of the first material is ensured to be larger than that of the second material.
When the antiparallel state flips the voltage VBL-AP to PLess than the parallel state flip voltage VSL-P to APThe saturation magnetization of the first material is greater than the saturation magnetization of the second material, such that the total magnetic moment of the pinned layer is greater than the total magnetic moment of the reference layer, and the Hoff value is adjusted in the negative direction, such that the magnetic bias field is adjusted in the negative direction.
Optionally, for the first and second modes, the reference layer is CoxFeyBzAnd (CoPt)nWherein n is more than or equal to 1; the pinning layer is (CoPt)mA magnetic layer, wherein m is not less than 1 and m>n is the same as the formula (I). Accordingly, the ferromagnetic repeat units are CoPt thin film layers.
In this embodiment, when the first endurance count and the second endurance count are balanced, the parallel state inversion voltage and the anti-parallel state inversion voltage are also adjusted, and it should be noted that, when the first endurance count and the second endurance count are balanced, the parallel state inversion voltage and the anti-parallel state inversion voltage are not close to or equal to each other, that is, the first endurance count and the second endurance count are balanced, and the magnitude relationship between the parallel state inversion voltage and the anti-parallel state inversion voltage is not required to be concerned. The first endurance count and the second endurance count are balanced, and the overall endurance count of the magnetic memory can be effectively improved.
The present application also provides a magnetic memory for use in the method of adjusting the performance of a magnetic memory according to any of the above embodiments.
After the adjustment for reducing the writing difficulty is performed on the magnetic memory, the parallel state overturning voltage and the anti-parallel state overturning voltage of the magnetic memory are balanced, one power supply can be shared, the overturning difficulty of the parallel state and the anti-parallel state is low, and the writing difficulty of the magnetic memory is reduced.
When the adjustment for improving the scratch resistance times is carried out on the magnetic memory, the whole milk scratch resistance times of the magnetic memory are improved.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The magnetic memory and the method for adjusting the switching voltage thereof provided by the present application are described in detail above. The principles and embodiments of the present application are explained herein using specific examples, which are provided only to help understand the method and the core idea of the present application. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.
Claims (14)
1. A method of tuning performance of a magnetic memory, comprising:
receiving a performance adjustment instruction;
acquiring a parallel state turning voltage and an anti-parallel state turning voltage of a magnetic tunnel junction when the magnetic tunnel junction is connected with a CMOS circuit in series;
and adjusting the parallel state switching voltage or the anti-parallel state switching voltage to adjust the performance of the magnetic tunnel junction.
2. The method of adjusting performance of a magnetic memory according to claim 1, wherein when the performance adjustment command is to reduce difficulty of writing, the adjusting the parallel state switching voltage or the anti-parallel state switching voltage to adjust the performance of the magnetic tunnel junction includes:
determining the magnitude relation between the parallel state overturning voltage and the anti-parallel state overturning voltage;
when the anti-parallel state switching voltage is larger than the parallel state switching voltage, increasing the parallel state switching voltage or reducing the anti-parallel state switching voltage, and adjusting a magnetic bias field of the magnetic tunnel junction in a forward direction to balance the parallel state switching voltage and the anti-parallel state switching voltage;
when the antiparallel state switching voltage is smaller than the parallel state switching voltage, reducing the parallel state switching voltage or increasing the antiparallel state switching voltage, and adjusting the magnetic bias field in the negative direction to balance the parallel state switching voltage and the antiparallel state switching voltage;
the magnetic tunnel junction at least comprises a pinning layer, a reference layer, a tunneling layer and a free layer, and the direction of the magnetic bias field points to the same direction of the magnetic moment of the reference layer as a positive direction.
3. The method of adjusting performance of a magnetic memory according to claim 1, wherein when the performance adjustment command is to increase the endurance count, the adjusting the parallel state switching voltage or the anti-parallel state switching voltage to adjust the performance of the magnetic tunnel junction includes:
obtaining a first endurance writing time from a parallel state to an antiparallel state and a second endurance writing time from the antiparallel state to the parallel state of the magnetic tunnel junction;
determining a magnitude relationship of the first endurance count and the second endurance count;
when the first endurance writing times are larger than the second endurance writing times, increasing the parallel state switching voltage or reducing the anti-parallel state switching voltage, and adjusting the magnetic bias field of the magnetic tunnel junction in the forward direction to balance the first endurance writing times and the second endurance writing times;
when the first endurance writing times are less than the second endurance writing times, reducing the parallel state overturning voltage or increasing the anti-parallel state overturning voltage, and adjusting the magnetic bias field to the negative direction so as to balance the first endurance writing times and the second endurance writing times;
the magnetic tunnel junction at least comprises a pinning layer, a reference layer, a tunneling layer and a free layer, and the direction of the magnetic bias field points to the same direction of the magnetic moment of the reference layer as a positive direction.
4. The method of adjusting performance of a magnetic memory according to claim 2 or 3, wherein the increasing the parallel state switching voltage or decreasing the anti-parallel state switching voltage comprises:
the number of layers of the first ferromagnetic repeating unit in the pinned layer is decreased or the number of layers of the second ferromagnetic repeating unit in the reference layer is increased.
5. The method of adjusting performance of a magnetic memory according to claim 2 or 3, wherein the increasing the parallel state switching voltage or decreasing the anti-parallel state switching voltage comprises:
reducing an etching angle of the magnetic tunnel junction, wherein a thickness of the reference layer is greater than a thickness of the pinning layer.
6. The method of adjusting performance of a magnetic memory according to claim 2 or 3, wherein the increasing the parallel state switching voltage or decreasing the anti-parallel state switching voltage comprises:
adjusting a first material of a first ferromagnetic repeat unit or adjusting a second material of a second ferromagnetic repeat unit such that a saturation magnetization of the first material is less than a saturation magnetization of the second material.
7. The method of adjusting performance of a magnetic memory according to claim 2 or 3, wherein the reducing the parallel state switching voltage or increasing the anti-parallel state switching voltage comprises:
increasing the number of layers of the first ferromagnetic repeating unit in the pinned layer or decreasing the number of layers of the second ferromagnetic repeating unit in the reference layer.
8. The method of adjusting performance of a magnetic memory according to claim 2 or 3, wherein the reducing the parallel state switching voltage or increasing the anti-parallel state switching voltage comprises:
and increasing the etching angle of the magnetic tunnel junction, wherein the thickness of the reference layer is not more than that of the pinning layer.
9. The method of adjusting performance of a magnetic memory according to claim 2 or 3, wherein the reducing the parallel state switching voltage or increasing the anti-parallel state switching voltage comprises:
adjusting a first material of a first ferromagnetic repeat unit or adjusting a second material of a second ferromagnetic repeat unit such that a saturation magnetization of the first material is greater than a saturation magnetization of the second material.
10. The method of adjusting performance of a magnetic memory of claim 4, further comprising:
and thinning the thickness of the first ferromagnetic repeating unit or increasing the thickness of the second ferromagnetic repeating unit.
11. The method of adjusting performance of a magnetic memory of claim 7, further comprising:
increasing the thickness of the first ferromagnetic repeating unit or decreasing the thickness of the second ferromagnetic repeating unit.
12. The method of claim 1, wherein obtaining the parallel state switching voltage and the anti-parallel state switching voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected in series with a CMOS circuit comprises:
measuring the testkey of the magnetic tunnel junction and the CMOS circuit in series to obtain the parallel state turning voltage and the anti-parallel state turning voltage;
or, performing circuit simulation on the series circuit of the magnetic tunnel junction and the CMOS circuit, and inputting the electrical parameters of the magnetic tunnel junction to obtain the parallel state switching voltage and the anti-parallel state switching voltage.
13. A method of tuning the performance of a magnetic memory as claimed in claim 2 or 3 wherein the reference layer is CoxFeyBzAnd (CoPt)nWherein n is more than or equal to 1; the pinning layer is (CoPt)mA magnetic layer, wherein m is not less than 1 and m>n。
14. A magnetic memory characterized in that it is used to implement the magnetic memory performance adjusting method according to any one of claims 1 to 13.
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