JP2020155441A - Magnetic storage device - Google Patents

Abstract

To suppress erroneous writing of data.SOLUTION: A magnetic storage device includes a memory cell containing a magnetoresistance effect element and a switching element that are connected to each other in series. The magnetoresistance effect element is configured to be shifted from a first resistance state to a second resistance state lower than the first resistance state according to a first writing operation in which current flows in the memory cell in a first direction, and shifts from the second resistance state to the first resistance state according to a second writing operation in which current flows in the memory cell in a second direction opposite to the first direction. The switching element has a first hold voltage associated with the first direction, and has a second hold voltage which is associated with the second direction and lower than the first hold voltage.SELECTED DRAWING: Figure 7

Description

The embodiment relates to a magnetic storage device.

A magnetic storage device (MRAM: Magnetoresistive Random Access Memory) using a magnetoresistive element as a storage element is known.

JP-A-2010-679942

Suppress erroneous writing of data.

The magnetic storage device of the embodiment includes a memory cell including a magnetoresistive element and a switching element connected in series. The magnetoresistive sensor changes from the first resistance state to the second resistance state lower than the first resistance state according to the first writing operation in which the current flows in the memory cell in the first direction, and the magnetic resistance effect element changes into the second resistance state in the memory cell. It is configured to change from the second resistance state to the first resistance state according to the second writing operation in which the current flows in the second direction opposite to the first direction. The switching element has a first hold voltage associated with the first direction, and has a second hold voltage associated with the second direction and lower than the first hold voltage.

The block diagram for demonstrating the structure of the magnetic storage device which concerns on 1st Embodiment. The circuit diagram for demonstrating the structure of the memory cell array of the magnetic storage device which concerns on 1st Embodiment. The cross-sectional view for demonstrating the structure of the memory cell array of the magnetic storage device which concerns on 1st Embodiment. The cross-sectional view for demonstrating the structure of the memory cell array of the magnetic storage device which concerns on 1st Embodiment. The cross-sectional view for demonstrating the structure of the memory cell of the magnetic storage apparatus which concerns on 1st Embodiment. The schematic diagram for demonstrating the selection operation of the memory cell in the magnetic storage device which concerns on 1st Embodiment. The diagram for demonstrating the relationship between the writing operation and the reading operation in the magnetic storage device which concerns on 1st Embodiment, and the current-voltage characteristic of a memory cell. The diagram for demonstrating the relationship between the write operation and read operation in the magnetic storage device which concerns on a comparative example, and the current-voltage characteristic of a memory cell.

Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration are designated by a common reference code. Further, when distinguishing a plurality of components having a common reference code, a subscript is added to the common reference code to distinguish them. When it is not necessary to distinguish a plurality of components, only a common reference code is attached to the plurality of components, and no subscript is added. Here, the subscript is not limited to the subscript and the superscript, and includes, for example, a lowercase alphabet added to the end of the reference code, an index meaning an array, and the like.

1. 1. First Embodiment The magnetic storage device according to the first embodiment will be described. In the magnetic storage device according to the first embodiment, for example, an element having a magnetoresistive effect (MTJ element or also referred to as a magnetoresistive effect element) by a magnetic tunnel junction (MTJ) is a resistance changing element. It is a magnetic storage device by the vertical magnetization method used as.

1.1 Configuration First, the configuration of the magnetic storage device according to the first embodiment will be described.

1.1.1 Configuration of Magnetic Storage Device FIG. 1 is a block diagram showing a configuration of a magnetic storage device according to the first embodiment. As shown in FIG. 1, the magnetic storage device 1 includes a memory cell array 10, a row selection circuit 11, a column selection circuit 12, a decoding circuit 13, a write circuit 14, a read circuit 15, a voltage generation circuit 16, an input / output circuit 17, and an input / output circuit 17. A control circuit 18 is provided.

The memory cell array 10 includes a plurality of memory cell MCs, each of which is associated with a set of rows and columns. Specifically, the memory cells MC in the same row are connected to the same word line WL, and the memory cells MC in the same column are connected to the same bit line BL.

The row selection circuit 11 is connected to the memory cell array 10 via the word line WL. The row selection circuit 11 is supplied with the decoding result (low address) of the address ADD from the decoding circuit 13. The row selection circuit 11 sets the word line WL corresponding to the line based on the decoding result of the address ADD in the selected state. In the following, the word line WL set in the selected state is referred to as a selected word line WL. Further, the word line WL other than the selected word line WL is referred to as a non-selected word line WL.

The column selection circuit 12 is connected to the memory cell array 10 via the bit line BL. The column selection circuit 12 is supplied with the decoding result (column address) of the address ADD from the decoding circuit 13. The column selection circuit 12 sets the column based on the decoding result of the address ADD in the selected state. In the following, the bit line BL set in the selected state is referred to as a selected bit line BL. The bit line BL other than the selected bit line BL is referred to as a non-selected bit line BL.

The decoding circuit 13 decodes the address ADD from the input / output circuit 17. The decoding circuit 13 supplies the decoding result of the address ADD to the row selection circuit 11 and the column selection circuit 12. Address ADD includes selected column addresses and row addresses.

The writing circuit 14 writes data to the memory cell MC. The write circuit 14 includes, for example, a write driver (not shown).

The read circuit 15 reads data from the memory cell MC. The readout circuit 15 includes, for example, a sense amplifier (not shown).

The voltage generation circuit 16 uses a power supply voltage provided from the outside (not shown) of the magnetic storage device 1 to generate voltages for various operations of the memory cell array 10. For example, the voltage generation circuit 16 generates various voltages required for the writing operation and outputs them to the writing circuit 14. Further, for example, the voltage generation circuit 16 generates various voltages required for the read operation and outputs them to the read circuit 15.

The input / output circuit 17 transfers the address ADD from the outside of the magnetic storage device 1 to the decoding circuit 13. The input / output circuit 17 transfers the command CMD from the outside of the magnetic storage device 1 to the control circuit 18. The input / output circuit 17 transmits and receives various control signal CNTs between the outside of the magnetic storage device 1 and the control circuit 18. The input / output circuit 17 transfers the data DAT from the outside of the magnetic storage device 1 to the writing circuit 14, and outputs the data DAT transferred from the reading circuit 15 to the outside of the magnetic storage device 1.

The control circuit 18 includes a row selection circuit 11 in the magnetic storage device 1, a column selection circuit 12, a decoding circuit 13, a writing circuit 14, a reading circuit 15, a voltage generation circuit 16, and an input based on the control signal CNT and the command CMD. Controls the operation of the output circuit 17.

1.1.2 Configuration of memory cell array Next, the configuration of the memory cell array of the magnetic storage device according to the first embodiment will be described with reference to FIG. FIG. 2 is a circuit diagram showing a configuration of a memory cell array of the magnetic storage device according to the first embodiment. In FIG. 2, the word line WL is shown classified by a subscript containing two lowercase alphabets (“u” and “d”) and an index (“<>”).

As shown in FIG. 2, the memory cells MC (MCu and MCd) are arranged in a matrix in the memory cell array 10, and a plurality of bit lines BL (BL <0>, BL <1>, ..., BL <N> )) And a plurality of word lines WLd (WLd <0>, WLd <1>, ..., WLd <M>) and WLu (WLu <0>, WLu <1>, ..., WLu <M >) Is associated with a pair of and (M and N are arbitrary integers). That is, the memory cells MCd <i, j> (0 ≦ i ≦ M, 0 ≦ j ≦ N) are connected between the word line WLd <i> and the bit line BL <j>, and the memory cells MCu <i <i. , J> are connected between the word line WLu <i> and the bit line BL <j>.

The subscripts "d" and "u" refer to a plurality of memory cells MC, one provided below (for example, with respect to the bit line BL) and one provided above. It is for convenience of identification. An example of the three-dimensional structure of the memory cell array 10 will be described later.

The memory cells MCd <i, j> include switching elements SELd <i, j> and magnetoresistive elements MTJd <i, j> connected in series. The memory cells MCU <i, j> include switching elements SELu <i, j> and magnetoresistive elements MTJu <i, j> connected in series.

The switching element SEL has a function as a selector that controls the supply of current to the magnetoresistive element MTJ at the time of writing and reading data to the corresponding magnetoresistive element MTJ. More specifically, for example, when the voltage applied to the memory cell MC is equal to or less than the threshold voltage Vt, the switching element SEL in a certain memory cell MC cuts off the current as an insulator having a large resistance value (off). When the threshold voltage Vt is exceeded, a current is passed as a conductor having a small resistance value (the state is turned on). That is, the switching element SEL has a function of switching whether to flow or cut off the current according to the magnitude of the voltage applied to the memory cell MC regardless of the direction of the flowing current.

The magnetic resistance effect element MTJ can switch the resistance value between the low resistance state and the high resistance state by the current whose supply is controlled by the switching element SEL. The magnetoresistive effect element MTJ can write data according to the change in its resistance state, holds the written data non-volatile, and functions as a readable storage element.

Next, the cross-sectional structure of the memory cell array 10 will be described with reference to FIGS. 3 and 4. 3 and 4 show an example of a cross-sectional view for explaining the configuration of the memory cell array of the magnetic storage device according to the first embodiment. 3 and 4 are cross-sectional views of the memory cell array 10 as viewed from different directions intersecting each other.

As shown in FIGS. 3 and 4, the memory cell array 10 is provided on the semiconductor substrate 20. In the following description, the plane parallel to the surface of the semiconductor substrate 20 is the XY plane, and the direction perpendicular to the XY plane is the Z direction. Further, the direction along the word line WL is the X direction, and the direction along the bit line BL is the Y direction. That is, FIGS. 3 and 4 are cross-sectional views of the memory cell array 10 as viewed from the Y direction and the X direction, respectively.

For example, a plurality of conductors 21 are provided on the semiconductor substrate 20. The plurality of conductors 21 have conductivity and function as a word line WLd. The plurality of conductors 21 are provided side by side along the Y direction, for example, and each extends along the X direction. Although FIGS. 3 and 4 have described the case where the plurality of conductors 21 are provided on the semiconductor substrate 20, the present invention is not limited to this. For example, the plurality of conductors 21 may be provided apart from each other above without being in contact with the semiconductor substrate 20.

A plurality of elements 22, each of which functions as a switching element SELd, are provided on the upper surface of one conductor 21. A plurality of elements 22 provided on the upper surface of one conductor 21 are provided side by side in the X direction, for example. That is, a plurality of elements 22 arranged along the X direction are commonly connected to the upper surface of one conductor 21. The details of the configuration of the element 22 will be described later.

An element 23 that functions as a magnetoresistive element MTJd is provided on the upper surface of each of the plurality of elements 22. The upper surface of each of the plurality of elements 23 is connected to any one of the plurality of conductors 24. The plurality of conductors 24 have conductivity and function as bit wires BL. The plurality of conductors 24 are provided side by side along the X direction, for example, and each extends along the Y direction. That is, a plurality of elements 23 arranged in the Y direction are commonly connected to one conductor 24. Although FIGS. 3 and 4 have described the case where each of the plurality of elements 23 is provided on the element 22 and the conductor 24, the present invention is not limited to this. For example, each of the plurality of elements 23 may be connected to the element 22 and the conductor 24 via a conductive contact plug (not shown).

A plurality of elements 25, each of which functions as a switching element SELu, are provided on the upper surface of one conductor 24. A plurality of elements 25 provided on the upper surface of one conductor 24 are provided side by side in the Y direction, for example. That is, a plurality of elements 25 arranged along the Y direction are commonly connected to the upper surface of one conductor 24. The element 25 has, for example, the same configuration as the element 22.

An element 26 that functions as a magnetoresistive element MTJu is provided on the upper surface of each of the plurality of elements 25. The upper surface of each of the plurality of elements 26 is connected to any one of the plurality of conductors 27. The plurality of conductors 27 have conductivity and function as a word line WLu. The plurality of conductors 27 are provided side by side along the Y direction, for example, and each extends along the X direction. That is, a plurality of elements 26 arranged in the X direction are commonly connected to one conductor 27. Although FIGS. 3 and 4 have described the case where each of the plurality of elements 26 is provided on the element 25 and the conductor 27, the present invention is not limited to this. For example, each of the plurality of elements 26 may be connected to the element 25 and the conductor 27 via a conductive contact plug (not shown).

With the above configuration, the memory cell array 10 has a structure in which a pair of two word lines WLd and WLu corresponds to one bit line BL. The memory cell array 10 is provided with a memory cell MCd between the word line WLd and the bit line BL, and a memory cell MCu is provided between the bit line BL and the word line WLu, and has different heights in the Z direction. It has a structure in which a plurality of layers provided at the positions function as the memory cell array 10. In the structure shown in FIGS. 3 and 4, the memory cell MCd is associated with the lower layer and the memory cell MCU is associated with the upper layer. That is, of the two memory cell MCs commonly connected to one bit line BL, the memory cell MC provided in the upper layer of the bit line BL corresponds to the memory cell MCu with the subscript "u" and is in the lower layer. The memory cell MC provided in the above corresponds to the memory cell MCd with the subscript "d".

1.1.3 Memory cell Next, the configuration of the memory cell of the magnetic storage device according to the first embodiment will be described with reference to FIG. FIG. 5 is a cross-sectional view showing the configuration of a memory cell of the magnetic storage device according to the first embodiment. FIG. 5 shows, for example, an example of a cross section obtained by cutting the memory cells MCd shown in FIGS. 3 and 4 along a plane perpendicular to the Z direction (for example, an XZ plane). Since the memory cell MCU has the same configuration as the memory cell MCd, its illustration is omitted.

11.3.1 Magnetoresistive element First, the magnetoresistive element MTJ in the memory cell MC will be described.

As shown in FIG. 5, the magnetoresistive sensor MTJ includes, for example, a ferromagnetic material 31 that functions as a storage layer SL (Storage layer), a non-magnetic material 32 that functions as a tunnel barrier layer TB (Tunnel barrier layer), and a reference layer. It includes a ferromagnetic material 33 that functions as an RL (Reference layer), a non-magnetic material 34 that functions as a spacer layer SP (Spacer layer), and a ferromagnetic material 35 that functions as a shift canceling layer SCL (Shift canceling layer).

The magnetoresistive sensor MTJd includes, for example, a ferromagnetic material 35, a non-magnetic material 34, a ferromagnetic material 33, a non-magnetic material 32, and a strong material from the word line WLd side toward the bit line BL side (in the Z-axis direction). A plurality of films are laminated in the order of the magnetic material 31. The magnetoresistive sensor MTJu includes, for example, a ferromagnetic material 35, a non-magnetic material 34, a ferromagnetic material 33, a non-magnetic material 32, and a strong material from the bit wire BL side to the word wire WLu side (in the Z-axis direction). A plurality of films are laminated in the order of the magnetic material 31. The magnetoresistive sensor MTJd and MTJu function as, for example, a perpendicular magnetization type MTJ element in which the magnetization directions of the magnetic materials constituting the magnetoresistive sensor MTJd and MTJu are oriented perpendicular to the film surface. The magnetoresistive element MTJ may include a further layer (not shown) between any of the above-mentioned ferromagnets 31 to 35.

The ferromagnet 31 has ferromagnetism and has an axial direction for easy magnetization in a direction perpendicular to the film surface. The ferromagnet 31 has a magnetization direction toward either the bit line BL side or the word line WL side. The ferromagnet 31 contains at least one of iron (Fe), cobalt (Co), and nickel (Ni). Further, the ferromagnet 31 may further contain boron (B). More specifically, for example, the ferromagnet 31 may contain cobalt iron boron (CoFeB) or iron tetraboride (FeB) and may have a body-centered cubic crystal structure.

The non-magnetic material 32 is a non-magnetic insulating film and contains, for example, magnesium oxide (MgO). The non-magnetic body 32 is provided between the ferromagnetic material 31 and the ferromagnetic material 33, and forms a magnetic tunnel junction together with these two ferromagnetic materials. Further, the non-magnetic material 32 has a body-centered cubic crystal structure (a NaCl crystal structure in which the film surface is oriented toward the (001) plane), and is ferromagnetic in the crystallization treatment of the adjacent ferromagnetic materials 31 and 33. It can also function as a core seed material for growing crystalline films from the interface with bodies 31 and 33.

The ferromagnet 33 has ferromagnetism and has an axial direction for easy magnetization in a direction perpendicular to the film surface. The ferromagnet 33 has a magnetization direction toward either the bit line BL side or the word line WL side. The ferromagnet 33 contains, for example, at least one of iron (Fe), cobalt (Co), and nickel (Ni). Further, the ferromagnet 33 may further contain boron (B). More specifically, for example, the ferromagnet 33 may contain cobalt iron boron (CoFeB) or iron tetraboride (FeB) and have a body-centered cubic crystal structure. The magnetization direction of the ferromagnet 33 is fixed, and in the example of FIG. 5, it faces the direction of the ferromagnet 35. Note that "the magnetization direction is fixed" means that the magnetization direction does not change due to a current (spin torque) having a magnitude capable of reversing the magnetization direction of the ferromagnetic material 31.

Although not shown in FIG. 5, the ferromagnetic material 33 may be a laminated body composed of a plurality of layers. Specifically, for example, the laminate constituting the ferromagnet 33 is non-magnetic on the surface of the interface layer containing the above-mentioned cobalt iron boron (CoFeB) or iron borate (FeB) on the ferromagnet 35 side. The structure may be such that further ferromagnets are laminated via the conductor. The non-magnetic conductors in the laminate constituting the ferromagnetic material 33 include, for example, tantalum (Ta), hafnium (Hf), tungsten (W), zirconium (Zr), molybdenum (Mo), niobium (Nb), and It may contain at least one metal selected from titanium (Ti). Further ferromagnets in the laminate constituting the ferromagnet 33 include, for example, a multilayer film of cobalt (Co) and platinum (Pt) (Co / Pt multilayer film), cobalt (Co) and nickel (Ni). It may include at least one multilayer film selected from the above multilayer film (Co / Ni multilayer film) and the multilayer film of cobalt (Co) and palladium (Pd) (Co / Pd multilayer film).

The non-magnetic material 34 is a non-magnetic conductive film and contains, for example, ruthenium (Ru).

The ferromagnet 35 has ferromagnetism and has an axial direction for easy magnetization in a direction perpendicular to the film surface. The ferromagnet 35 comprises at least one alloy selected from, for example, cobalt platinum (CoPt), cobalt nickel (CoNi), and cobalt palladium (CoPd). Like the ferromagnet 35, the ferromagnet 35 may be a laminated body composed of a plurality of layers. In that case, the ferromagnetic material 35 is, for example, a multilayer film of cobalt (Co) and platinum (Pt) (Co / Pt multilayer film), or a multilayer film of cobalt (Co) and nickel (Ni) (Co / Ni multilayer film). Membranes) and at least one multilayer film selected from a multilayer film of cobalt (Co) and palladium (Pd) (Co / Pd multilayer film).

The ferromagnet 35 has a magnetization direction toward either the bit line BL side or the word line WL side. The magnetization direction of the ferromagnet 35 is fixed in the same manner as that of the ferromagnet 33, and in the example of FIG. 5, it faces the direction of the ferromagnet 33.

Ferromagnets 33 and 35 are antiferromagnetically coupled by a non-magnetic material 34. That is, the ferromagnets 33 and 35 are coupled so as to have magnetization directions antiparallel to each other. Therefore, in the example of FIG. 5, the magnetization directions of the ferromagnets 33 and 35 are oriented so as to face each other. Such a bonded structure of the ferromagnetic material 33, the non-magnetic material 34, and the ferromagnetic material 35 is called a SAF (Synthetic Anti-Ferromagnetic) structure. Thereby, the ferromagnet 35 can cancel the influence of the leakage magnetic field of the ferromagnet 33 on the magnetization direction of the ferromagnet 31. Therefore, asymmetry occurs in the easiness of reversing the magnetization of the ferromagnet 31 due to an external factor caused by the leakage magnetic field of the ferromagnet 33 (that is, the direction of magnetization of the ferromagnet 31 is reversed). The easiness of reversing is different between the case of reversing from one side to the other and the case of reversing in the opposite direction).

In the first embodiment, a write current is directly passed through such a magnetoresistive element MTJ, and a spin torque is injected into the storage layer SL and the reference layer RL by this write current, so that the magnetization direction of the storage layer SL and the reference layer RL A spin injection writing method that controls the magnetization direction is adopted. The magnetoresistive element MTJ can take either a low resistance state or a high resistance state depending on whether the relative relationship between the magnetization directions of the storage layer SL and the reference layer RL is parallel or antiparallel.

When a write current Iapp of a certain magnitude is passed through the magnetoresistive sensor MTJ in the direction of arrow A1 in FIG. 5, that is, in the direction from the storage layer SL to the reference layer RL, the magnetization directions of the storage layer SL and the reference layer RL The relative relationship of is parallel. In this parallel state, the resistance value of the magnetoresistive element MTJ is the lowest, and the magnetoresistive element MTJ is set to the low resistance state. This low resistance state is called a "P (Parallel) state" and is defined as, for example, a state of data "0".

Further, when a write current Ipup larger than the write current Iap is passed through the magnetoresistive sensor MTJ in the direction of arrow A2 in FIG. The relative relationship of the magnetization directions of the layer SL and the reference layer RL is antiparallel. In this antiparallel state, the resistance value of the magnetoresistive element MTJ is the highest, and the magnetoresistive element MTJ is set to the high resistance state. This high resistance state is called an "AP (Anti-Parallel) state" and is defined as, for example, a state of data "1".

In the following description, the method of defining the data will be described according to the above-mentioned method of defining the data, but the method of defining the data “1” and the data “0” is not limited to the above-mentioned example. For example, the P state may be defined as data “1” and the AP state may be defined as data “0”.

11.3.2 Switching element Next, the switching element SEL will be described with reference to FIG.

In the example of FIG. 5, the switching element SEL is provided on the magnetoresistive element MTJ. However, the switching element SEL may be connected to the magnetoresistive element MTJ via a contact (not shown).

The switching element SEL includes an electrode material 41 that functions as a top electrode TEL, a selector material 42, and an electrode material 43 that functions as a bottom electrode BEL. As a whole, the switching element SEL functions as a two-terminal (two-terminal type) switching element, and when the voltage applied between the two terminals is equal to or less than the threshold voltage, the switching element is in a "high resistance" state, for example, electrically. It is in a non-conducting state. When the voltage applied between the two terminals exceeds the threshold voltage, the switching element changes to a "low resistance" state, for example, an electrically conductive state. The switching element may have this function regardless of the polarity of the voltage.

In the switching element SELd, for example, a plurality of films are laminated in the order of the electrode material 43, the selector material 42, and the electrode material 41 from the word line WLd side to the bit line BL side (in the Z-axis direction). In the switching element SELu, for example, a plurality of films are laminated in the order of the electrode material 43, the selector material 42, and the electrode material 41 from the bit line BL side to the word line WLu side (in the Z-axis direction). That is, in the example of FIG. 5, the direction from the electrode material 41 to the electrode material 43 is the direction from the ferromagnetic material 31 (storage layer SL) to the ferromagnetic material 33 (reference layer RL), that is, the magnetoresistive sensor MTJ. Corresponds to the flow direction (arrow A1) of the write current Iapp in the low resistance state. Further, the direction from the electrode material 43 to the electrode material 41 is the direction from the ferromagnet 33 (reference layer RL) to the ferromagnet 31 (storage layer SL), that is, writing that puts the magnetoresistive element MTJ in a high resistance state. It corresponds to the direction in which the current Ipap flows (arrow A2).

The electrode material 41 has a function as a conductor that suppresses an increase in the parasitic resistance of the switching element SEL. The electrode material 41 includes, for example, at least one selected from carbon (C), carbon nitride (CN), tungsten nitride (WN), and titanium nitride (TiN).

The selector material 42 is a core portion for the above-mentioned switching element SEL to function as a two-terminal (two-terminal type) switching element. The selector material 42 may contain, for example, at least one chalcogen element selected from the group consisting of tellurium (Te), selenium (Se) and sulfur (S). Alternatively, for example, it may contain chalcogenide, which is a compound containing the chalcogen element. Other selector materials 42 include, for example, boron (B), aluminum (Al), gallium (Ga), indium (In), carbon (C), silicon (Si), germanium (Ge), tin (Sn), and the like. It may contain at least one or more elements selected from the group consisting of arsenic (As), phosphorus (P), antimony (Sb), titanium (Ti), and bismuth (Bi). More specifically, the selector material 42 is selected from germanium (Ge), antimony (Sb), tellurium (Te), titanium (Ti), arsenic (As), indium (In), and bismuth (Bi). It may contain at least two elements. Further, the selector material 42 is at least selected from titanium (Ti), vanadium (V), chromium (Cr), niobium (Nb), molybdenum (Mo), hafnium (Hf), and tungsten (W). It may contain an oxide of one element.

Like the electrode material 41, the electrode material 43 has a function as a conductor that suppresses an increase in the parasitic resistance of the switching element SEL. On the other hand, a substance different from that of the electrode material 41 is used for the electrode material 43. For example, the electrode material 43 contains at least one selected from substances not contained in the electrode material 41 among carbon (C), carbon nitride (CN), tungsten nitride (WN), and titanium nitride (TiN). ..

By adopting different substances for the electrode materials 41 and 43, polarity is generated in the switching characteristics of the switching element SEL. That is, the switching characteristics of the switching element SEL are when a positive voltage is applied from the electrode material 41 toward the electrode material 43 (that is, in the direction of the arrow A1) and when a positive voltage is applied from the electrode material 43 toward the electrode material 41 (that is,). That is, there is a difference (asymmetry) between the case where a positive voltage is applied (in the direction of arrow A2) and the case where a positive voltage is applied. As a result, the characteristics of the entire memory cell MC including the switching characteristics of the switching element SEL are polarized. In the following description, for convenience, the polarity of the memory cell MC when a positive voltage is applied from the electrode material 41 toward the electrode material 43 is defined as “first polarity”, and the polarity is defined as “first polarity” from the electrode material 43 toward the electrode material 41. The polarity of the memory cell MC when a positive voltage is applied is defined as the “second polarity”.

1.2 Operation Next, the operation of the magnetic storage device according to the first embodiment will be described.

1.2.1 Memory cell selection operation The memory cell selection operation in the magnetic storage device according to the first embodiment will be described with reference to FIG. In the following description, the memory cell MC to be written or read, that is, the memory cell MC associated with the set of the selected word line WL and the selected bit line BL is selected as the selected memory cell MC (or the selected memory cell MC). Say.

FIG. 6 is a schematic diagram for explaining an outline of a memory cell selection operation of the magnetic storage device according to the first embodiment. In FIG. 6, as an example, the bit lines BL <0> and BL <1> are connected to the word lines WLu <0>, WLd <0>, WLu <1>, and WLd <1> 8 One memory cell MC is shown.

As shown in FIG. 6, the row selection circuit 11 and the column selection circuit 12 control so that a voltage Vsel is applied between the selection word line WL and the selection bit line BL. The voltage Vsel is a voltage larger than the threshold voltage Vt of the switching element SEL. In the example of FIG. 5, as an example, a case where the voltage VSS is applied to the selection word line WLd <0> and the voltage VSS is applied to the selection bit line BL <1> is shown. The voltage VSS is a ground voltage, for example 0V.

A voltage Vsel is applied to the selected memory cell MC. Therefore, a voltage equal to or higher than the threshold voltage Vt is applied to the switching element SEL in the selected memory cell MC. As a result, the switching element SEL in the selected memory cell MC is turned on, and a write current or a read current can be passed through the magnetoresistive effect element MTJ in the selected memory cell MC. When it is desired to reverse the direction of the flowing current, the row selection circuit 11 and the column selection circuit 12 apply a voltage VSS to the selection bit line BL <1> and a voltage VSS to the selection word line WLd <0>. It may be controlled so as to apply.

Further, the row selection circuit 11 and the column selection circuit 12 control so that the voltage Vsel / 2 is supplied to the non-selection word line WL and the non-selection bit line BL. The voltage Vsel / 2 is a voltage smaller than the threshold voltage Vt at which the switching element SEL is turned on. In the example of FIG. 6, as an example, a case where the voltage Vsel / 2 is applied to the word lines WLu <0>, WLd <1>, WLu <1>, and the bit line BL <0> is shown. The memory cell MC provided between the selected bit line BL and the non-selected word line WL and the memory cell MC provided between the selected word line WL and the non-selected word line BL are semi-selected memory cell MC (or half). Memory cell MC in the selected state). A voltage Vsel / 2 is applied to the semi-selective memory cell MC. Therefore, a voltage less than the threshold voltage Vt is applied to the switching element SEL in the semi-selective memory cell MC. As a result, the switching element SEL in the semiselective memory cell MC is turned off, and it is possible to suppress the flow of the write current or the read current to the magnetoresistive effect element MTJ in the semiselective memory cell MC.

Further, the memory cell MC provided between the non-selected bit line BL and the non-selected word line WL is referred to as a non-selected memory cell MC (or a memory cell MC in a non-selected state). Since the voltage Vsel / 2 is applied to both the non-selected bit line BL and the non-selected word line WL, no voltage drop occurs in the non-selected memory cell MC. Therefore, the switching element SEL in the non-selective memory cell MC is turned off, and it is possible to suppress the flow of the write current or the read current to the magnetoresistive effect element MTJ in the non-selective memory cell MC.

1.2.2 IV Characteristics of Memory Cell Next, FIG. 7 shows the current-voltage characteristics (hereinafter, also referred to as IV characteristics) of the memory cell MC due to the polarity of the switching element SEL of the magnetic storage device according to the first embodiment. It will be described using.

FIG. 7 is a diagram for explaining the relationship between the writing operation and the reading operation in the magnetic storage device according to the first embodiment and the IV characteristics of the memory cell. In FIG. 7, the current-voltage characteristic of the memory cell MC when the voltage applied to the memory cell MC is linearly plotted on the horizontal axis and the absolute value of the current flowing through the memory cell MC is linearly plotted on the vertical axis. IV characteristics) are shown. In FIG. 7, the horizontal axis from the center of the paper surface to the right corresponds to the first polarity (voltage V1), and the horizontal axis from the center of the paper surface to the left corresponds to the second polarity (voltage V2). To do.

As shown in FIG. 7, the IV characteristics of the memory cell MC are represented by the lines Rap and Rp. The line Rap is a voltage V1 applied to the memory cell MC in the direction of the arrow A1 in FIG. 5 when the magnetoresistive element MTJ is in a high resistance state, and a current | I | flowing in the memory cell MC at that time. It is a plot of the relationship. The line Rp is a voltage V2 applied to the memory cell MC in the direction of the arrow A2 in FIG. 5 when the magnetoresistive element MTJ is in a low resistance state, and a current | I | flowing in the memory cell MC at that time. It is a plot of the relationship.

First, the first polarity of the memory cell MC will be described. At the first polarity, the writing operation of the data “0” (that is, the writing operation of changing the magnetoresistive element MTJ from the high resistance state to the low resistance state) is executed. Hereinafter, the magnetoresistive element MTJ will be described as being in a high resistance state.

As described above, since the switching element SEL is in a high resistance state when the voltage V1 is equal to or less than the threshold voltage Vt, no current | I | flows through the memory cell MC in this case. On the other hand, the switching element SEL can be regarded as a constant resistance having a voltage drop amount Vh1 after the voltage V1 increases and the switching element SEL switches to a low resistance state when the threshold voltage Vt is exceeded. Therefore, immediately after the switching element SEL is switched to the low resistance state, the voltage VS_app = (Vt-Vh1) is applied to the magnetoresistive effect element MTJ, and the spike current VS_app / Rap flows. The voltage Vh1 is also referred to as a hold voltage of the switching element SEL in the first polarity.

When reading data from the memory cell MC, the data can be read with a smaller read current by executing the read operation when the magnetoresistive element MTJ is in the high resistance state. For example, the magnitude of the read current Ir can be set to the minimum value of the amount of current flowing through the magnetoresistive element MTJ in the high resistance state, that is, the magnitude of the spike current VS_app / Rap as described above.

After that, when the voltage V1 is further increased, the current | I | flowing through the memory cell MC increases along the line Rap. Then, when the voltage V1 increases to the voltage Vapp, the amount of voltage drop in the magnetoresistive element MTJ becomes Vmtj_appp (= Vapp-Vh1), and the current | I | reaches the write current Iapp. The write operation of the data "0" is executed under such a condition.

As described above, in the data “0” writing operation, the voltage V1 corresponding to the voltage Vapp / 2 is applied to the semi-selected memory cell MC. Therefore, the threshold voltage Vt of the switching element SEL is set to a value larger than the voltage Vapp / 2 as a condition for preventing the semi-selected memory cell MC from being erroneously selected.

Next, the second polarity will be described. In the second polarity, the writing operation of the data “1” (that is, the writing operation of changing the magnetoresistive element MTJ from the low resistance state to the high resistance state) is executed. In such a second polarity, the switching element SEL has a hold voltage Vh2 lower than the hold voltage Vh1 in the first polarity. Hereinafter, the magnetoresistive element MTJ will be described as being in a low resistance state.

As described above, since the switching element SEL is in a high resistance state when the voltage V2 is equal to or less than the threshold voltage Vt, no current | I | flows through the memory cell MC in this case. On the other hand, the switching element SEL can be regarded as a constant resistor having a voltage drop amount Vh2 after the voltage V2 increases and the switching element SEL switches to a low resistance state when the threshold voltage Vt is exceeded. Therefore, immediately after the switching element SEL is switched to the low resistance state, the voltage VS_pap = (Vt-Vh2) is applied to the magnetoresistive effect element MTJ, and the spike current VS_pap / Rp flows. Under the condition that the threshold voltage Vt does not change depending on the polarity, the voltage VS_pap is higher than the voltage VS_app because the hold voltage Vh2 is lower than the hold voltage Vh1.

After that, when the voltage V2 is further increased, the current | I | flowing through the memory cell MC increases along the line Rp. Then, when the voltage V2 increases to the voltage Vpap, the amount of voltage drop in the magnetoresistive element MTJ becomes Vmtj_pap (= Vpap-Vh2), and the current | I | reaches the write current Ipap. By lowering the hold voltage Vh2 to lower than the hold voltage Vh1, the voltage Vpup can be lowered to about the voltage Vhap. That is, the voltage Vpap may be higher than the voltage Vapp and may be equal to the voltage Vapp. The write operation of the data "1" is executed under such a condition.

As described above, in the writing operation of the data "1", the voltage V2 corresponding to the voltage Vpap / 2 is applied to the semi-selected memory cell MC. Therefore, the threshold voltage Vt of the switching element SEL is set to a value larger than the voltage Vpap / 2 as a condition for preventing the semi-selected memory cell MC from being erroneously selected.

1.3. Regarding the effect according to the present embodiment According to the first embodiment, erroneous writing of data can be suppressed. This effect will be described below with reference to FIG.

FIG. 8 is a diagram for explaining the relationship between the writing operation and the reading operation of the magnetic storage device according to the comparative example and the IV characteristics of the memory cell. FIG. 8 corresponds to FIG. 7 and shows a case where the hold voltage Vh'is the same value without shifting regardless of the polarity. That is, the hold voltage Vh'according to the comparative example is lower than the hold voltage Vh1 and higher than the hold voltage Vh2 according to the first embodiment.

As shown in FIG. 8, in the first polarity, the switching element SEL switches to a low resistance state when the voltage V1 exceeds the threshold voltage Vt, and thereafter, it is regarded as a constant resistance having a voltage drop amount Vh'. As a result, immediately after the switching element SEL is switched to the low resistance state, the voltage VS_app'= (Vt-Vh') is applied to the magnetoresistive effect element MTJ, and the spike current VS_appp'/ Rap flows. Since the hold voltage Vh'is lower than the hold voltage Vh1, the voltage VS_app' is higher than the voltage VS_appp. Therefore, the spike current VS_app'/ Rap is larger than the spike current VS_appp / Rap. Further, the read current Ir'when reading data from the memory cell MC has a magnitude of about VS_app'/ Rap, which is larger than the read current Ir shown in FIG. 7.

It is desirable that the spike current and the read current are set to smaller values because the data of the magnetoresistive element MTJ may be unintentionally written. According to the first embodiment, the switching element SEL is set so that the hold voltage Vh1 in the first polarity is higher than the hold voltage Vh'. As a result, the spike current VS_app / Rap and the read current Ir can be made smaller than the spike current VS_app'/ Rap and the read current Ir', respectively, and erroneous writing can be suppressed.

This will be described again with reference to FIG. In the second polarity, the switching element SEL is regarded as a constant resistor having a voltage drop amount Vh'after that, when the voltage V2 increases and the threshold voltage Vt is exceeded, the switching element SEL switches to a low resistance state. After that, when the voltage V2 is further increased, the magnetoresistive element MTJ increases the current | I | along the line Rp. Then, when the voltage V2 increases to the voltage Vpap, the amount of voltage drop in the magnetoresistive element MTJ becomes Vmtj_pap (= Vpap'-Vh'), and the current | I | reaches the write current Ipap. Therefore, the voltage Vpap'applied to the memory cell MC when the write current Ipap flows is higher than the voltage Vpap by the difference between the hold voltage Vh'and the hold voltage Vh2.

It is desirable that the write voltages Vpap and Vapp are set to lower values so that the half value exceeds the threshold voltage Vt and the half-selected memory cell MC is not erroneously selected. In particular, the voltage Vpap may be higher than the voltage Vpap due to the write current Ipap being larger than the write current Ipp, and the constraint on the threshold voltage Vt may become stricter. According to the first embodiment, the switching element SEL is set so that the hold voltage Vh2 in the second polarity is lower than the hold voltage Vh'. As a result, the write voltage Vpap can be made lower than the write voltage Vpap', and by extension, erroneous writing due to erroneous selection of the semi-selected memory cell MC can be suppressed.

2. 2. Modifications and the like Not limited to the above-described first embodiment, various modifications can be applied.

The switching element SEL described in the first embodiment described above has described the case where the threshold voltage Vt has no polarity, but the present invention is not limited to this. That is, by providing the configuration described in FIG. 5, the switching element SEL can also give polarity to the threshold voltage Vt. For example, when the threshold voltage Vt is shifted in the same direction as the hold voltage Vh is shifted, the threshold voltage Vt in the second polarity can be made lower than that shown in FIG. 7. As a result, the voltage VS_pap (= Vt-Vh2) can be made lower, and the spike current in the second polarity can be suppressed. Further, when the threshold voltage Vt is shifted in the direction opposite to the shift direction of the hold voltage Vh, the threshold voltage Vt in the first polarity can be made higher than in the case shown in FIG. 7. As a result, the restriction (Vapp / 2 <Vt) for not erroneously selecting the semi-selected memory cell MC during the writing operation of the data “0” can be relaxed.

Further, in the memory cell MC described in the first embodiment described above, the case where the magnetoresistive element MTJ is provided below the switching element SEL has been described, but the magnetoresistive element MTJ is provided above the switching element SEL. You may.

Further, although the magnetoresistive element MTJ described in the first embodiment described above has a top-free structure in which the storage layer SL is provided above the reference layer RL, the storage layer SL is below the reference layer RL. It may have a bottom-free structure provided in. In this case, the direction of the write current is opposite to that shown in FIG. 5, but the polarity of the switching element SEL is also reversed accordingly. That is, by setting the direction from the electrode material 41 toward the electrode material 43 to be the direction of the write current of the data “0”, the same effect as that of the first embodiment can be achieved.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

1 ... Magnetic storage device, 10 ... Memory cell array, 11 ... Row selection circuit, 12 ... Column selection circuit, 13 ... Decoding circuit, 14 ... Write circuit, 15 ... Read circuit, 16 ... Voltage generation circuit, 17 ... Input / output circuit, 18 ... control circuit, 20 ... semiconductor substrate, 21,24,27 ... conductor, 22,23,25,26 ... element, 31,33,35 ... ferromagnetic material, 32,34 ... non-magnetic material, 41,43 … Electrode material, 42… Selector material.

Claims (12)

A memory cell including a magnetoresistive element and a switching element connected in series is provided.
The magnetoresistive element is
In response to the first write operation in which a current flows in the memory cell in the first direction, the first resistance state is changed to the second resistance state lower than the first resistance state.
It is configured to change from the second resistance state to the first resistance state in response to a second write operation in which a current flows in the memory cell in a second direction opposite to the first direction.
The switching element is
It has a first hold voltage associated with the first direction.
A magnetic storage device associated with the second direction and having a second hold voltage lower than the first hold voltage. The switching element is
With the first electrode material
A second electrode material containing a substance different from that of the first electrode material,
A switching material between the first electrode material and the second electrode material,
including,
The magnetic storage device according to claim 1. The absolute value of the first write voltage applied to the memory cell in the first write operation is equal to the absolute value of the second write voltage applied to the memory cell in the second write operation.
The magnetic storage device according to claim 1. The first electrode material and the second electrode material contain at least one substance selected from carbon (C), carbon nitride (CN), tungsten nitride (WN), and titanium nitride (TiN).
The magnetic storage device according to claim 2. The switching element is
The first threshold voltage associated with the first direction and
The second threshold voltage associated with the second direction and
Have,
The magnetic storage device according to claim 1. The first threshold voltage and the second threshold voltage are equal,
The magnetic storage device according to claim 5. The first threshold voltage and the second threshold voltage are different from each other.
The magnetic storage device according to claim 5. The first threshold voltage is larger than half of the first write voltage applied to the memory cell in the first write operation.
The second threshold voltage is larger than half of the second write voltage applied to the memory cell in the second write operation.
The magnetic storage device according to claim 5. The switching material comprises at least one chalcogen element selected from tellurium (Te), selenium (Se), and sulfur (S).
The magnetic storage device according to claim 2. The switching material includes boron (B), aluminum (Al), gallium (Ga), indium (In), carbon (C), silicon (Si), germanium (Ge), tin (Sn), arsenic (As), and the like. It further comprises at least one element selected from phosphorus (P), antimony (Sb), titanium (Ti), and bismuth (Bi).
The magnetic storage device according to claim 9. The magnetoresistive element is
The first ferromagnet and
The second ferromagnet and
A non-magnetic material between the first ferromagnet and the second ferromagnet,
including,
The magnetic storage device according to claim 1. The switching element is a two-terminal switching element.
The magnetic storage device according to claim 1.