WO2022127426A1 - Magnetic memory and performance adjustment method therefor - Google Patents

Abstract

A magnetic memory and a performance adjustment method therefor. The method comprises: receiving a performance adjustment instruction (S101); acquiring a parallel-state reversal voltage and an anti-parallel-state reversal voltage of a magnetic tunnel junction when the magnetic tunnel junction is connected to a CMOS circuit in series (S102); and adjusting the parallel-state reversal voltage or the anti-parallel-state reversal voltage, so as to adjust the performance of the magnetic tunnel junction (S103). It can be seen that in the present performance adjustment method for a magnetic memory, after a performance adjustment instruction is received, a parallel-state reversal voltage and an anti-parallel-state reversal voltage of a magnetic tunnel junction when the magnetic tunnel junction is connected to a CMOS circuit in series are acquired, and the performance of the magnetic memory is adjusted by means of adjusting the parallel-state reversal voltage or the anti-parallel-state reversal voltage, such that the writing difficulty of the magnetic memory and the number of times of same resisting erasure are optimized.

Description

A kind of magnetic memory and its performance adjustment method

This application claims the priority of the Chinese patent application filed on December 14, 2020 with the application number 202011465986.1 and the invention titled "A magnetic memory and a method for adjusting its performance", the entire contents of which are incorporated herein by reference Applying.

technical field

The present application relates to the technical field of magnetic memory, and in particular, to a magnetic memory and a method for adjusting its performance.

Background technique

Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a new type of memory that needs to be integrated with CMOS (Complementary Metal-Oxide-Semiconductor, Complementary Metal-Oxide-Semiconductor) circuits when used. . The integration method of STT-MRAM and CMOS circuit is to connect the magnetic tunnel junctions (MTJ) of the basic storage unit of STT-MRAM to one or more sources of one or more CMOS circuits in series, and the drain electrode is connected to the external word. Line (bite line, BL), gate (gate electrode) to bit line (word line, WL), source (source electrode) to source line (source line, SL), as shown in Figure 1.

The reversal of MTJ is driven by current. Due to the huge difference between the resistance values of the parallel state and the anti-parallel state, and the reversal current of the two states is also different, and is affected by the current supply capability of CMOS, the reversal voltage of the two states of the MTJ is also very high. Large gap, as shown in Figure 2, in the figure, the abscissa is the voltage, and the ordinate is the resistance. When switching from BL, the CMOS voltage divider is small, the drain voltage is low, the source is grounded, the V _gate -V _drain is high, the CMOS current capacity is strong, the CMOS resistance is small, and the MTJ voltage divider is more; When the pressure is turned over, due to the MTJ voltage division, the CMOS source-drain voltage is high, the V _gate -V _{drian is} low, the CMOS current capacity is weak, the CMOS resistance increases, and the MTJ voltage division is small. When the source line voltage increases to a certain level, the voltage on the MTJ will remain basically unchanged. Therefore, the voltage division of the MTJ in the two inversion states is quite different, and the writing difficulty of the MTJ is high. On the other hand, under normal circumstances, the endurance of MTJ in one direction will be significantly lower than the other direction. , or, the endurance times from the parallel state to the anti-parallel state are significantly greater than those from the anti-parallel state to the parallel state, resulting in a low overall endurance times of the MTJ. However, it is not currently possible to optimize these two properties of the MTJ.

Therefore, how to solve the above technical problems should be the focus of those skilled in the art.

SUMMARY OF THE INVENTION

The purpose of the present application is to provide a magnetic memory and a method for adjusting its performance to optimize the performance of the magnetic memory.

In order to solve the above technical problems, the present application provides a method for adjusting the performance of a magnetic memory, including:

Receive performance adjustment instructions;

acquiring the parallel state switching voltage and the antiparallel switching voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected in series with the CMOS circuit;

The parallel state switching voltage or the anti-parallel state switching voltage is adjusted to adjust the performance of the magnetic tunnel junction.

Optionally, when the performance adjustment command is to reduce the difficulty of writing, the adjusting the parallel state switching voltage or the anti-parallel state switching voltage to adjust the performance of the magnetic tunnel junction includes:

determining the magnitude relationship between the parallel state inversion voltage and the antiparallel state inversion voltage;

When the anti-parallel state inversion voltage is greater than the parallel state inversion voltage, the parallel state inversion voltage is increased or the anti-parallel state inversion voltage is decreased, and the magnetic bias field of the magnetic tunnel junction is adjusted to the forward direction , to balance the parallel state switching voltage and the anti-parallel state switching voltage;

When the anti-parallel state inversion voltage is smaller than the parallel state inversion voltage, the parallel state inversion voltage is decreased or the anti-parallel state inversion voltage is increased, and the magnetic bias field is adjusted in a negative direction to balance all the the parallel state inversion voltage and the anti-parallel state inversion voltage;

Wherein, the magnetic tunnel junction at least includes a pinned layer, a reference layer, a tunnel layer and a free layer, and the direction of the magnetic bias field is a positive direction in the same direction as the magnetic moment pointing to the reference layer.

Optionally, when the performance adjustment instruction is to increase the number of times of resistance to erasing and writing, the adjusting the parallel state switching voltage or the anti-parallel state switching voltage to adjust the performance of the magnetic tunnel junction includes:

obtaining the first time of erasing and writing of the magnetic tunnel junction from the parallel state to the anti-parallel state and the second time of erasing and writing from the anti-parallel state to the parallel state;

Determine the magnitude relationship between the first number of times of erasing and writing and the second number of times of erasing and writing;

When the first number of times of erasing and writing is greater than the number of times of resistance to erasing and writing, the parallel state switching voltage is increased or the anti-parallel state switching voltage is decreased, and the magnetic field of the magnetic tunnel junction is adjusted to the positive direction. a bias field to balance the first endurance times and the second endurance times;

When the first number of times of erasing and writing is less than the second number of times of resistance to erasing and writing, the parallel state switching voltage is decreased or the anti-parallel state switching voltage is increased, and the magnetic bias field is adjusted in a negative direction, to balance the first number of endurance times and the second number of endurance times;

Wherein, the magnetic tunnel junction at least includes a pinned layer, a reference layer, a tunnel layer and a free layer, and the direction of the magnetic bias field is a positive direction in the same direction as the magnetic moment pointing to the reference layer.

Optionally, the increasing the parallel state inversion voltage or reducing the anti-parallel state inversion voltage includes:

Decrease the number of layers of the first ferromagnetic repeating unit in the pinned layer or increase the number of layers of the second ferromagnetic repeating unit in the reference layer.

Optionally, the increasing the parallel state inversion voltage or reducing the anti-parallel state inversion voltage includes:

The etching angle of the magnetic tunnel junction is reduced, wherein the thickness of the reference layer is greater than the thickness of the pinning layer.

Optionally, the increasing the parallel state inversion voltage or reducing the anti-parallel state inversion voltage includes:

The first material of the first ferromagnetic repeating unit or the second material of the second ferromagnetic repeating unit is adjusted so that the saturation magnetization of the first material is smaller than the saturation magnetization of the second material.

Optionally, the reducing the parallel state inversion voltage or increasing the anti-parallel state inversion voltage includes:

Increase the number of layers of the first ferromagnetic repeating unit in the pinned layer or decrease the number of layers of the second ferromagnetic repeating unit in the reference layer.

Optionally, the reducing the parallel state inversion voltage or increasing the anti-parallel state inversion voltage includes:

The etching angle of the magnetic tunnel junction is increased, wherein the thickness of the reference layer is not greater than the thickness of the pinning layer.

Optionally, the reducing the parallel state inversion voltage or increasing the anti-parallel state inversion voltage includes:

The first material of the first ferromagnetic repeating unit or the second material of the second ferromagnetic repeating unit is adjusted so that the saturation magnetization of the first material is greater than the saturation magnetization of the second material.

Optionally, also include:

The thickness of the first ferromagnetic repeating unit is thinned or the thickness of the second ferromagnetic repeating unit is increased.

Optionally, also include:

The thickness of the first ferromagnetic repeating unit is increased or the thickness of the second ferromagnetic repeating unit is thinned.

Optionally, obtaining the parallel state switching voltage and the anti-parallel switching voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected in series with the CMOS circuit includes:

Measuring the magnetic tunnel junction and the CMOS circuit in series testkey to obtain the parallel state switching voltage and the anti-parallel switching voltage;

Alternatively, circuit simulation is performed on a series circuit of the magnetic tunnel junction and a CMOS circuit, and electrical parameters of the magnetic tunnel junction are input to obtain the parallel state switching voltage and the antiparallel state switching voltage.

Optionally, the reference layer _{is a coupling structure layer of CoxFeyBz and (CoPt)n , where n≥1} ; the pinned layer is a (CoPt) _m magnetic layer, where m≥1 and m >n.

The present application also provides a magnetic memory, which is used to implement any one of the above-mentioned methods for adjusting the performance of a magnetic memory.

A method for adjusting the performance of a magnetic memory provided by the present application includes receiving a performance adjustment instruction; acquiring the parallel state switching voltage and the anti-parallel switching voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected in series with a CMOS circuit; and adjusting the parallel state switching voltage Alternatively, the antiparallel state flips the voltage to tune the performance of the magnetic tunnel junction.

It can be seen that the magnetic memory performance adjustment method in this application obtains the parallel state switching voltage and the anti-parallel state switching voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected in series with the CMOS circuit after receiving the performance adjustment command. The parallel state inversion voltage is adjusted, so as to adjust the performance of the magnetic memory, and optimize the writing difficulty and the number of times of erasing and writing of the magnetic memory.

In addition, the present application also provides a magnetic memory.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present application or the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only For some embodiments of the present application, for those of ordinary skill in the art, other drawings can also be obtained according to these drawings without any creative effort.

Fig. 1 is a circuit diagram of a magnetic tunnel junction and a CMOS circuit in series;

FIG. 2 is a schematic diagram of the switching voltage of the parallel state and the antiparallel state of the magnetic tunnel junction;

3 is a flowchart of a method for adjusting the performance of a magnetic memory provided by an embodiment of the present application;

4 is a flowchart of another method for adjusting the performance of a magnetic memory provided by an embodiment of the present application;

5 is a schematic structural diagram of a magnetic tunnel junction;

6 is a schematic diagram of a magnetic bias field;

7 is a schematic structural diagram of a magnetic tunnel junction at a small etching angle;

FIG. 8 is a schematic diagram of the structure of the magnetic tunnel junction at a large etching angle

9 is a flowchart of another method for adjusting the performance of a magnetic memory provided by an embodiment of the present application;

10 is a schematic diagram of the adjustment of the magnetic bias field when the first number of times of resistance to erasing and writing is greater than the number of times of resistance to erasing and writing;

FIG. 11 is a schematic diagram of adjustment of the anti-parallel state inversion voltage adjustment when the first number of endurance times is greater than the second number of endurance times.

Detailed ways

In order to make those skilled in the art better understand the solution of the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

As mentioned in the Background section, when the MTJ is turned over from the BL, the CMOS voltage divider is small, the drain voltage is low, the source is grounded, the V _gate -V _drain is high, the CMOS current capacity is strong, and the CMOS resistance is relatively high. When the voltage is small, the MTJ voltage divides more; when the SL is pressurized and turned over, due to the MTJ voltage division, the CMOS source-drain voltage is high, the V _gate -V _{drian is} low, the CMOS current capacity is weak, the CMOS resistance increases, and the MTJ voltage divider is relatively low. Small. When the source line voltage increases to a certain level, the voltage on the MTJ will remain basically unchanged. Therefore, the voltage division of the MTJ in the two inversion states is quite different, and the writing difficulty of the MTJ is high. On the other hand, under normal circumstances, the endurance of MTJ in one direction is significantly lower than that in the other direction, resulting in a low overall endurance of MTJ. However, it is not currently possible to optimize these two properties of the MTJ.

In view of this, the present application provides a method for adjusting the performance of a magnetic memory. Please refer to FIG. 3 , which is a flowchart of a method for adjusting the performance of a magnetic memory provided by an embodiment of the present application, and the method includes:

Step S101: Receive a performance adjustment instruction.

Step S102 : acquiring the parallel state switching voltage and the antiparallel switching voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected in series with the CMOS circuit.

The magnetic tunnel junction at least includes a pinned layer, a reference layer, a tunnel layer and a free layer. The reference layer and the pinned layer are formed by an antiferromagnetic coupling layer to form a strong antiferromagnetic coupling so that their magnetic moments are aligned antiparallel. Among them, the parallel state flip voltage is the voltage required to flip the magnetic moment of the free layer from the direction parallel to the magnetic moment of the reference layer to the antiparallel direction; the antiparallel state flip voltage is the magnetic moment of the free layer from antiparallel to the reference layer The voltage required to flip the direction of the magnetic moment of the layer to the parallel direction.

Optionally, obtaining the parallel state switching voltage and the anti-parallel switching voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected in series with the CMOS circuit includes:

The magnetic tunnel junction is measured in series with the CMOS circuit testkey to obtain the parallel state inversion voltage and the antiparallel state inversion voltage.

Alternatively, circuit simulation is performed on a series circuit of the magnetic tunnel junction and a CMOS circuit, and electrical parameters of the magnetic tunnel junction are input to obtain the parallel state switching voltage and the anti-parallel state switching voltage.

The electrical parameters of the magnetic tunnel junction include, but are not limited to, the parallel-state switching voltage V _{cP to AP} , the anti-parallel switching voltage V _{c-AP to P} , the parallel-state resistance R _p , the anti-parallel switching voltage when the magnetic tunnel junction is not connected to the CMOS circuit On-state resistance R _ap , coercive force Hc, Hoff value.

Specifically, the applied gate voltage V _WL may be 1.6V.

When the magnetic tunnel junction is connected in series with the CMOS circuit, the parallel state switching voltage of the magnetic tunnel junction is recorded as V _{SL-P to AP} , and the anti-parallel state switching voltage is recorded as V _{BL-AP to P} .

Step S103 : adjusting the parallel state switching voltage or the anti-parallel switching voltage to adjust the performance of the magnetic tunnel junction.

The magnetic memory performance adjustment method in the present application obtains the parallel state switching voltage and antiparallel state switching voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected in series with the CMOS circuit after receiving the performance adjustment instruction. The inversion voltage is adjusted, thereby adjusting the performance of the magnetic memory, and optimizing the writing difficulty and the number of times of erasing and writing of the magnetic memory.

The method for adjusting the performance of the magnetic memory in the present application will be described in detail below according to different performance adjusting instructions.

First, when the performance adjustment instruction is to reduce the difficulty of writing, please refer to FIG. 4 , which is a flowchart of another magnetic memory performance adjustment method provided by an embodiment of the present application, and the method includes:

Step S201: Receive a performance adjustment instruction.

Step S202: Acquire the parallel state switching voltage and the antiparallel switching voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected in series with the CMOS circuit.

Step S203: Determine the magnitude relationship between the parallel state inversion voltage and the anti-parallel state inversion voltage.

Step S204 : when the anti-parallel state inversion voltage is greater than the parallel state inversion voltage, increase the parallel state inversion voltage or decrease the anti-parallel state inversion voltage, and adjust the magnetic field of the magnetic tunnel junction in a forward direction. a bias field to balance the parallel state flip voltage and the antiparallel state flip voltage.

As shown in Figure 5, the magnetic tunnel junction includes a free layer 1, a reference layer 2 and a pinned layer 3. The magnetization directions of the free layer 1, the reference layer 2 and the pinned layer 3 are perpendicular magnetization; the magnetic bias field is freed by the magnetic tunnel junction The synthesis of stray fields generated by other magnetic layers outside the layer is equivalent to a static magnetic field applied to the free layer. Due to the directionality of the magnetic bias field, the MTJ will be more stable in a certain state, please refer to Figure 6 . The magnetic bias field will affect the electrical inversion. When the MTJ magnetic bias field is biased towards a certain state, the inversion voltage of this state will increase, and vice versa.

Optionally, there are three ways to increase the parallel state inversion voltage or decrease the anti-parallel state inversion voltage, which will be introduced separately below.

First, reduce the number of layers of the first ferromagnetic repeating unit in the pinning layer or increase the number of layers of the second ferromagnetic repeating unit in the reference layer. At this time, the Hoff value is adjusted to the positive direction, and the magnetic bias field is adjusted to the positive direction.

When the anti-parallel state inversion voltage V _{BL-AP to P} is greater than the parallel state inversion voltage V _{SL-P to AP} , it is necessary to reduce the anti-parallel state inversion voltage V _{c-AP to P} when the magnetic tunnel junction is not connected to the CMOS circuit, Reducing the number of layers of the first ferromagnetic repeating unit in the pinning layer can reduce the stray field generated by the pinning layer. The direction of the stray field generated by the pinning layer is opposite to the direction of the magnetic moment of the reference layer. The direction of the stray field is negative. Increasing the number of layers of the second ferromagnetic repeating unit in the reference layer can increase the stray field generated by the reference layer. The direction of the stray field of the reference layer is the same as the direction of the magnetic moment of the reference layer, that is, the reference layer generates The direction of the stray field is positive, and the Hoff value is adjusted to the positive direction, so the magnetic bias field is adjusted to the positive direction, the parallel state switching voltage V _{SL-P to AP} becomes larger, and the anti-parallel state switching voltage V _{BL-AP to P} becomes small, the difference between V _{SL-P to AP} and V _{BL-AP to P} is reduced, so that V _{SL-P to AP} and V _{BL-AP to P} are substantially equal in size.

Second, the etching angle of the magnetic tunnel junction is reduced, wherein the thickness of the reference layer is greater than the thickness of the pinning layer.

It can be understood that in this case, the reference layer is the same as the other parameters of the pinned layer, and the thickness is a single variable.

When the anti-parallel state switching voltage V _{BL-AP to P} is greater than the parallel state switching voltage V _{SL-P to AP} , under the condition that the thickness of the reference layer in the magnetic tunnel junction is greater than the thickness of the pinning layer, by reducing the etching angle, The schematic diagram of the structure of the magnetic tunnel junction is shown in Figure 7. It can realize that the volume of the reference layer is larger than that of the pinned layer, the direction of the stray field generated by the pinned layer is negative, the direction of the stray field generated by the reference layer is positive, and the Hoff value Adjust to the positive direction, so the magnetic bias field is adjusted to the positive direction, the anti-parallel state switching voltage V _{BL-AP to P} becomes smaller, and the parallel state switching voltage V _{SL-P to AP} becomes larger, so as to realize V _{SL-P to AP} It is basically the same size as V _{BL-AP to P.}

The third method is to adjust the first material of the first ferromagnetic repeating unit or the second material of the second ferromagnetic repeating unit, so that the saturation magnetization of the first material is smaller than the saturation magnetization of the second material.

It should be pointed out that the types of the first material and the second material are not specifically limited in this application, as long as the saturation magnetization of the first material is less than that of the second material.

When the anti-parallel state switching voltage V _{BL-AP to P} is greater than the parallel state switching voltage V _{SL-P to AP} , the saturation magnetization of the first material is smaller than that of the second material, so that the total magnetic moment of the pinned layer is less than For the total magnetic moment of the reference layer, the Hoff value is adjusted to the positive direction, so the magnetic bias field is adjusted to the positive direction.

Optionally, for the first and second methods above, the reference layer is a coupling structure layer of Co _x Fe _y B _z and (CoPt) _n , where n≥1; the pinned layer is (CoPt) _m magnetic layers, where m≧1 and m>n. Correspondingly, the ferromagnetic repeating unit is a CoPt thin film layer.

Step S205: when the anti-parallel state inversion voltage is smaller than the parallel state inversion voltage, reduce the parallel state inversion voltage or increase the anti-parallel state inversion voltage, and adjust the magnetic bias field in a negative direction, in order to balance the parallel state switching voltage and the anti-parallel state switching voltage; wherein, the magnetic tunnel junction at least includes a pinned layer, a reference layer, a tunnel layer and a free layer, and the direction of the magnetic bias field is directed to the The same direction of the magnetic moment of the reference layer is the positive direction.

Optionally, there are three ways to reduce the parallel state inversion voltage or increase the anti-parallel state inversion voltage, which will be introduced separately below.

First, increase the number of layers of the first ferromagnetic repeating unit in the pinned layer or decrease the number of layers of the second ferromagnetic repeating unit in the reference layer.

Increasing the number of layers of the first ferromagnetic repeating unit in the pinned layer can increase the stray field generated by the pinned layer. The direction of the stray field generated by the pinned layer is opposite to the direction of the magnetic moment of the reference layer, that is, the stray field generated by the pinned layer. The direction is negative. Reducing the number of layers of the second ferromagnetic repeating unit in the reference layer can reduce the stray field generated by the reference layer. The direction of the stray field of the reference layer is the same as the direction of the magnetic moment of the reference layer, that is, the The direction of the stray field is positive, the Hoff value is adjusted in the negative direction, so the magnetic bias field is adjusted in the negative direction, the parallel state switching voltage V _{SL-P to AP} becomes smaller, and the anti-parallel state switching voltage V _{BL-AP to P} becomes larger , the difference between V _{SL-P to AP} and V _{BL-AP to P} is reduced, so that V _{SL-P to AP} and V _{BL-AP to P} are substantially equal in size.

Second, the etching angle of the magnetic tunnel junction is increased, wherein the thickness of the reference layer is not greater than the thickness of the pinning layer.

When the anti-parallel state switching voltage V _{BL-AP to P} is smaller than the parallel state switching voltage V _{SL-P to AP} , and under the condition that the thickness of the reference layer is not greater than that of the pinned layer, increasing the etching angle of the magnetic tunnel junction, the magnetic The schematic diagram of the tunnel junction structure is shown in Figure 8. The larger the etching angle, the larger the volume difference between the pinned layer and the reference layer, the direction of the stray field generated by the pinned layer is negative, and the direction of the stray field generated by the reference layer is positive The _Hoff value is adjusted in the negative direction, so the magnetic _bias field is adjusted in the negative direction _{. -P to AP} and V _{BL-AP to P} are basically equal in size.

The third method is to adjust the first material of the first ferromagnetic repeating unit or adjust the second material of the second ferromagnetic repeating unit, so that the saturation magnetization of the first material is greater than the saturation magnetization of the second material.

It should be pointed out that the types of the first material and the second material are not specifically limited in this application, as long as the saturation magnetization of the first material is greater than that of the second material.

When the anti-parallel state switching voltage V _{BL-AP to P} is less than the parallel state switching voltage V _{SL-P to AP} , the saturation magnetization of the first material is greater than that of the second material, so that the total magnetic moment of the pinned layer is greater than The total magnetic moment of the reference layer, the Hoff value is adjusted to the negative direction, so the magnetic bias field is adjusted to the negative direction.

Optionally, for the first and second methods above, the reference layer is a coupling structure layer of Co _x Fe _y B _z and (CoPt) _n , where n≥1; the pinned layer is (CoPt) _m magnetic layers, where m≧1 and m>n. Correspondingly, the ferromagnetic repeating unit is a CoPt thin film layer.

In this embodiment, the parallel state switching voltage and the antiparallel switching voltage are adjusted to balance the parallel switching voltage and the antiparallel switching voltage, thereby reducing the difficulty of switching between the parallel and antiparallel states and reducing the magnetic memory. writing difficulty. Wherein, the difference between the parallel state inversion voltage and the anti-parallel state inversion voltage of the adjusted magnetic memory is less than 10%.

Further, on the basis of the above embodiment, in an embodiment of the present application, when the number of layers of the first ferromagnetic repeating unit in the pinned layer is reduced or the layer of the second ferromagnetic repeating unit in the reference layer is increased, When adjusted in this way, it also includes:

The thickness of the first ferromagnetic repeating unit is thinned or the thickness of the second ferromagnetic repeating unit is increased.

Further, on the basis of the above embodiment, in an embodiment of the present application, when the number of layers of the first ferromagnetic repeating unit in the pinned layer is increased or the layer of the second ferromagnetic repeating unit in the reference layer is decreased, hours, including:

The thickness of the first ferromagnetic repeating unit is increased or the thickness of the second ferromagnetic repeating unit is thinned.

Since the composition of the first ferromagnetic repeating unit and the second ferromagnetic repeating unit is fixed, increasing or decreasing the number of layers of the first ferromagnetic repeating unit and the second ferromagnetic repeating unit may make the adjustment of the Hoff value too large, so that continuous adjustment cannot be achieved. Therefore, the continuous adjustment of the magnetic bias field cannot be realized. By adjusting the thickness of the first ferromagnetic repeating unit and the second ferromagnetic repeating unit, the step size of adjusting the Hoff value can be reduced, and the parallel state switching voltage V _{SL-P to AP} It is closer to the anti-parallel state switching voltage V _{BL-AP to P.}

It should be pointed out that when adjusting the thickness of the first ferromagnetic repeating unit and the second ferromagnetic repeating unit, the thickness adjustment needs to be within a certain range to maintain magnetic stability.

Second, when the performance adjustment instruction is to increase the number of times of erasing and writing, please refer to FIG. 9 , which is a flowchart of another magnetic memory performance adjustment method provided by an embodiment of the present application, and the method includes:

Step S301: Receive a performance adjustment instruction.

Step S302: Acquire the parallel state switching voltage and the antiparallel switching voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected in series with the CMOS circuit.

Step S303: Obtain the first time of erasing and writing of the magnetic tunnel junction from the parallel state to the anti-parallel state and the second time of erasing and writing of the magnetic tunnel junction from the anti-parallel state to the parallel state.

Step S304: Determine the magnitude relationship between the first number of times of erasing and writing and the second number of times of erasing and writing.

Step S305 : when the first number of endurance times is greater than the second number of endurance times, increase the parallel state inversion voltage or decrease the anti-parallel state inversion voltage, and adjust the magnetic tunnel to the positive direction The magnetic bias field of the junction is used to balance the first endurance times and the second endurance times.

Optionally, there are three ways to increase the parallel state inversion voltage or decrease the anti-parallel state inversion voltage, which will be introduced separately below.

First, reduce the number of layers of the first ferromagnetic repeating unit in the pinning layer or increase the number of layers of the second ferromagnetic repeating unit in the reference layer. At this time, the Hoff value is adjusted to the positive direction, and the magnetic bias field is adjusted to the positive direction.

When the anti-parallel state inversion voltage V _{BL-AP to P} is greater than the parallel state inversion voltage V _{SL-P to AP} , it is necessary to reduce the anti-parallel state inversion voltage V _{c-AP to P} when the magnetic tunnel junction is not connected to the CMOS circuit, Reducing the number of layers of the first ferromagnetic repeating unit in the pinning layer can reduce the stray field generated by the pinning layer. The direction of the stray field generated by the pinning layer is opposite to the direction of the magnetic moment of the reference layer. The direction of the stray field is negative. Increasing the number of layers of the second ferromagnetic repeating unit in the reference layer can increase the stray field generated by the reference layer. The direction of the stray field of the reference layer is the same as the direction of the magnetic moment of the reference layer, that is, the reference layer generates The direction of the stray field is positive, and the Hoff value is adjusted to the positive direction, so the magnetic bias field is adjusted to the positive direction, the parallel state switching voltage V _{SL-P to AP} becomes larger, and the anti-parallel state switching voltage V _{BL-AP to P} becomes small, the difference between V _{SL-P to AP} and V _{BL-AP to P} is reduced, so that V _{SL-P to AP} and V _{BL-AP to P} are substantially equal in size.

Second, the etching angle of the magnetic tunnel junction is reduced, wherein the thickness of the reference layer is greater than the thickness of the pinning layer.

It can be understood that in this case, the reference layer is the same as the other parameters of the pinned layer, and the thickness is a single variable.

When the anti-parallel state switching voltage V _{BL-AP to P} is greater than the parallel state switching voltage V _{SL-P to AP} , under the condition that the thickness of the reference layer in the magnetic tunnel junction is greater than that of the pinning layer, by reducing the etching angle, The schematic diagram of the structure of the magnetic tunnel junction is shown in Figure 7. The volume of the reference layer can be larger than that of the pinned layer. The direction of the stray field generated by the pinned layer is negative, the direction of the stray field generated by the reference layer is positive, and the Hoff value Adjust to the positive direction, so the magnetic bias field is adjusted to the positive direction, the anti-parallel state switching voltage V _{BL-AP to P} becomes smaller, and the parallel state switching voltage V _{SL-P to AP} becomes larger, so as to realize V _{SL-P to AP} It is basically the same size as V _{BL-AP to P.}

Third, adjust the first material of the first ferromagnetic repeating unit or adjust the second material of the second ferromagnetic repeating unit, so that the saturation magnetization of the first material is smaller than that of the second material Saturation magnetization.

It should be pointed out that the types of the first material and the second material are not specifically limited in this application, as long as the saturation magnetization of the first material is less than that of the second material. For example, when the first material uses a material with low saturation magnetization, such as inserting a non-magnetic metal layer in CoFeB or incorporating a non-magnetic material, the second material uses _a material with high saturation magnetization, such as CoFe alloy or (Cox Fe _{1 -x} ) _y B _1-y , where x is between 0.2 and 0.7 and y is between 0.5 and 1.

When the antiparallel state switching voltage V _{BL-AP to P} is greater than the parallel state switching voltage V _{SL-P to AP} , the saturation magnetization of the first material is smaller than that of the second material, so that the total magnetic moment of the pinned layer is less than For the total magnetic moment of the reference layer, the Hoff value is adjusted to the positive direction, so the magnetic bias field is adjusted to the positive direction.

Optionally, for the first and second methods above, the reference layer is a coupling structure layer of Co _x Fe _y B _z and (CoPt) _n , where n≥1; the pinned layer is (CoPt) _m magnetic layers, where m≧1 and m>n. Correspondingly, the ferromagnetic repeating unit is a CoPt thin film layer.

When the first erasing and writing endurance times are greater than the second erasing and writing endurance times, please refer to FIG. 10 and FIG. 11 for adjustment diagrams of the magnetic bias field and the adjustment of the anti-parallel state inversion voltage, respectively.

Step S306 : when the first number of endurance times is less than the second number of endurance times, reduce the parallel state switching voltage or increase the anti-parallel state switching voltage, and adjust the magnetic bias in a negative direction setting a field to balance the first and second endurance times; wherein, the magnetic tunnel junction at least includes a pinned layer, a reference layer, a tunnel layer and a free layer, and the magnetic bias The direction of the field is positive in the same direction as the magnetic moment pointing to the reference layer.

Optionally, there are three ways to reduce the parallel state inversion voltage or increase the anti-parallel state inversion voltage, which will be introduced separately below.

First, increase the number of layers of the first ferromagnetic repeating unit in the pinned layer or decrease the number of layers of the second ferromagnetic repeating unit in the reference layer.

Increasing the number of layers of the first ferromagnetic repeating unit in the pinned layer can increase the stray field generated by the pinned layer. The direction of the stray field generated by the pinned layer is opposite to the direction of the magnetic moment of the reference layer, that is, the stray field generated by the pinned layer. The direction is negative. Reducing the number of layers of the second ferromagnetic repeating unit in the reference layer can reduce the stray field generated by the reference layer. The direction of the stray field of the reference layer is the same as the direction of the magnetic moment of the reference layer, that is, the The direction of the stray field is positive, the Hoff value is adjusted in the negative direction, so the magnetic bias field is adjusted in the negative direction, the parallel state switching voltage V _{SL-P to AP} becomes smaller, and the anti-parallel state switching voltage V _{BL-AP to P} becomes larger , the difference between V _{SL-P to AP} and V _{BL-AP to P} is reduced, so that V _{SL-P to AP} and V _{BL-AP to P} are substantially equal in size.

The second is to increase the etching angle of the magnetic tunnel junction, wherein the thickness of the reference layer is not greater than the thickness of the pinning layer.

When the anti-parallel state switching voltage V _{BL-AP to P} is smaller than the parallel state switching voltage V _{SL-P to AP} , and under the condition that the thickness of the reference layer is not greater than that of the pinned layer, increasing the etching angle of the magnetic tunnel junction, the magnetic The schematic diagram of the tunnel junction structure is shown in Figure 8. The larger the etching angle, the larger the volume difference between the pinned layer and the reference layer, the direction of the stray field generated by the pinned layer is negative, and the direction of the stray field generated by the reference layer is positive The _Hoff value is adjusted in the negative direction, so the magnetic _bias field is adjusted in the negative direction _{. -P to AP} and V _{BL-AP to P} are basically equal in size.

Third, adjust the first material of the first ferromagnetic repeating unit or adjust the second material of the second ferromagnetic repeating unit, so that the saturation magnetization of the first material is greater than that of the second material Saturation magnetization.

It should be pointed out that the types of the first material and the second material are not specifically limited in this application, as long as the saturation magnetization of the first material is greater than that of the second material.

When the anti-parallel state switching voltage V _{BL-AP to P} is less than the parallel state switching voltage V _{SL-P to AP} , the saturation magnetization of the first material is greater than that of the second material, so that the total magnetic moment of the pinned layer is greater than The total magnetic moment of the reference layer, the Hoff value is adjusted to the negative direction, so the magnetic bias field is adjusted to the negative direction.

Optionally, for the first and second methods above, the reference layer is a coupling structure layer of Co _x Fe _y B _z and (CoPt) _n , where n≥1; the pinned layer is (CoPt) _m magnetic layers, where m≧1 and m>n. Correspondingly, the ferromagnetic repeating unit is a CoPt thin film layer.

In this embodiment, when balancing the first and second endurance times, the parallel state switching voltage and the anti-parallel state switching voltage are also adjusted. It should be pointed out that when the first and second endurance times are When the two endurance times reach a balance, the parallel state switching voltage and the anti-parallel state switching voltage are not close or equal, that is, at this time, the purpose is to balance the size of the first and second endurance times. It is not necessary to pay attention to the magnitude relationship between the parallel state inversion voltage and the antiparallel state inversion voltage. Balancing the first and second endurance times can effectively improve the overall endurance times of the magnetic memory.

The present application further provides a magnetic memory, which is used in the method for adjusting the performance of the magnetic memory according to any one of the above embodiments.

When the above-mentioned adjustment to reduce the difficulty of writing is performed on the magnetic memory, the parallel state switching voltage and the anti-parallel state switching voltage of the magnetic memory are balanced, and a power supply can be shared. The writing difficulty of magnetic memory is reduced.

After the above adjustment for increasing the number of times of erasing and writing is performed on the magnetic memory, the overall number of times of resistance to erasing and writing of the magnetic memory is increased.

The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments may be referred to each other. As for the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant part can be referred to the description of the method.

The magnetic memory and the method for adjusting the inversion voltage provided by the present application are described in detail above. Specific examples are used herein to illustrate the principles and implementations of the present application, and the descriptions of the above embodiments are only used to help understand the methods and core ideas of the present application. It should be pointed out that for those of ordinary skill in the art, without departing from the principles of the present application, several improvements and modifications can also be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims (14)

1. A method for adjusting the performance of a magnetic memory, comprising:

   Receive performance adjustment instructions;

   acquiring the parallel state switching voltage and the antiparallel switching voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected in series with the CMOS circuit;

   The parallel state switching voltage or the anti-parallel state switching voltage is adjusted to adjust the performance of the magnetic tunnel junction.
2. The method for adjusting the performance of a magnetic memory according to claim 1, wherein when the performance adjusting command is to reduce the difficulty of writing, the parallel state switching voltage or the anti-parallel switching voltage is adjusted to adjust the magnetic tunnel. The properties of the junction include:

   determining the magnitude relationship between the parallel state inversion voltage and the antiparallel state inversion voltage;

   When the anti-parallel state inversion voltage is greater than the parallel state inversion voltage, the parallel state inversion voltage is increased or the anti-parallel state inversion voltage is decreased, and the magnetic bias field of the magnetic tunnel junction is adjusted to the forward direction , to balance the parallel state switching voltage and the anti-parallel state switching voltage;

   When the anti-parallel state inversion voltage is smaller than the parallel state inversion voltage, the parallel state inversion voltage is decreased or the anti-parallel state inversion voltage is increased, and the magnetic bias field is adjusted in a negative direction to balance all the the parallel state inversion voltage and the anti-parallel state inversion voltage;

   Wherein, the magnetic tunnel junction at least includes a pinned layer, a reference layer, a tunnel layer and a free layer, and the direction of the magnetic bias field is a positive direction in the same direction as the magnetic moment pointing to the reference layer.
3. The method for adjusting the performance of a magnetic memory according to claim 1, wherein when the performance adjusting command is to increase the number of times of resistance to erasing and writing, adjusting the parallel state switching voltage or the anti-parallel switching voltage to adjust the magnetic Tunnel junction capabilities include:

   obtaining the first time of erasing and writing of the magnetic tunnel junction from the parallel state to the anti-parallel state and the second time of erasing and writing from the anti-parallel state to the parallel state;

   Determine the magnitude relationship between the first number of times of erasing and writing and the second number of times of erasing and writing;

   When the first number of times of erasing and writing is greater than the second number of times of resistance to erasing and writing, the parallel state switching voltage is increased or the anti-parallel state switching voltage is decreased, and the magnetic field of the magnetic tunnel junction is adjusted to the positive direction. a bias field to balance the first endurance times and the second endurance times;

   When the first number of endurance times is less than the second number of endurance times, the parallel state switching voltage is decreased or the anti-parallel state switching voltage is increased, and the magnetic bias field is adjusted in a negative direction, to balance the first number of endurance times and the second number of endurance times;

   Wherein, the magnetic tunnel junction at least includes a pinned layer, a reference layer, a tunnel layer and a free layer, and the direction of the magnetic bias field is a positive direction in the same direction as the magnetic moment pointing to the reference layer.
4. The method for adjusting the performance of a magnetic memory according to claim 2 or 3, wherein the increasing the parallel state switching voltage or reducing the anti-parallel state switching voltage comprises:

   Decrease the number of layers of the first ferromagnetic repeating unit in the pinned layer or increase the number of layers of the second ferromagnetic repeating unit in the reference layer.
5. The method for adjusting the performance of a magnetic memory according to claim 2 or 3, wherein the increasing the parallel state switching voltage or reducing the anti-parallel state switching voltage comprises:

   The etching angle of the magnetic tunnel junction is reduced, wherein the thickness of the reference layer is greater than the thickness of the pinning layer.
6. The method for adjusting the performance of a magnetic memory according to claim 2 or 3, wherein the increasing the parallel state switching voltage or reducing the anti-parallel state switching voltage comprises:

   The first material of the first ferromagnetic repeating unit or the second material of the second ferromagnetic repeating unit is adjusted so that the saturation magnetization of the first material is smaller than the saturation magnetization of the second material.
7. The method for adjusting the performance of a magnetic memory according to claim 2 or 3, wherein the reducing the parallel state inversion voltage or increasing the anti-parallel state inversion voltage comprises:

   Increase the number of layers of the first ferromagnetic repeating unit in the pinned layer or decrease the number of layers of the second ferromagnetic repeating unit in the reference layer.
8. The method for adjusting the performance of a magnetic memory according to claim 2 or 3, wherein the reducing the parallel state inversion voltage or increasing the anti-parallel state inversion voltage comprises:

   The etching angle of the magnetic tunnel junction is increased, wherein the thickness of the reference layer is not greater than the thickness of the pinning layer.
9. The method for adjusting the performance of a magnetic memory according to claim 2 or 3, wherein the reducing the parallel state inversion voltage or increasing the anti-parallel state inversion voltage comprises:

   The first material of the first ferromagnetic repeating unit or the second material of the second ferromagnetic repeating unit is adjusted so that the saturation magnetization of the first material is greater than the saturation magnetization of the second material.
10. The method for adjusting the performance of a magnetic memory according to claim 4, further comprising:

    The thickness of the first ferromagnetic repeating unit is thinned or the thickness of the second ferromagnetic repeating unit is increased.
11. The method for adjusting the performance of a magnetic memory according to claim 7, further comprising:

    The thickness of the first ferromagnetic repeating unit is increased or the thickness of the second ferromagnetic repeating unit is thinned.
12. The method for adjusting the performance of a magnetic memory according to claim 1, wherein the acquiring the parallel state switching voltage and the antiparallel switching voltage of the magnetic tunnel junction when the magnetic tunnel junction is connected in series with the CMOS circuit comprises:

    Measuring the magnetic tunnel junction and the CMOS circuit in series testkey to obtain the parallel state switching voltage and the anti-parallel state switching voltage;

    Alternatively, circuit simulation is performed on a series circuit of the magnetic tunnel junction and a CMOS circuit, and electrical parameters of the magnetic tunnel junction are input to obtain the parallel state switching voltage and the anti-parallel state switching voltage.
13. The method for adjusting the performance of a magnetic memory according to claim 2 or 3, wherein the reference layer _{is a coupling structure layer of CoxFeyBz and (CoPt)n , wherein n≥1} ; the pinned layer is a (CoPt) _m magnetic layer, where m≧1 and m>n.
14. A magnetic memory, characterized in that the magnetic memory is used to implement the method for adjusting the performance of a magnetic memory according to any one of claims 1 to 13.

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