CN114614805A - High-voltage integrated circuit - Google Patents

High-voltage integrated circuit Download PDF

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Publication number
CN114614805A
CN114614805A CN202210250667.1A CN202210250667A CN114614805A CN 114614805 A CN114614805 A CN 114614805A CN 202210250667 A CN202210250667 A CN 202210250667A CN 114614805 A CN114614805 A CN 114614805A
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CN
China
Prior art keywords
circuit
electrically connected
dmos
gate
output
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Pending
Application number
CN202210250667.1A
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Chinese (zh)
Inventor
冯宇翔
左安超
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Guangdong Huixin Semiconductor Co Ltd
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Guangdong Huixin Semiconductor Co Ltd
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Priority to CN202210250667.1A priority Critical patent/CN114614805A/en
Publication of CN114614805A publication Critical patent/CN114614805A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/168—Modifications for eliminating interference voltages or currents in composite switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors

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Abstract

The invention discloses a high-voltage integrated circuit, which comprises a Schmitt circuit, a filter, a level conversion circuit, a double-pulse generator, a single DMOS (double diffusion metal oxide semiconductor) drive circuit and an output circuit, wherein the Schmitt circuit is connected with the filter; the input end of the Schmitt circuit is electrically connected with an input signal, the output end of the Schmitt circuit is electrically connected with the input end of the filter, the output end of the filter is electrically connected with the input end of the level switching circuit, the output end of the level switching circuit is electrically connected with the input end of the double-pulse generator, the output end of the double-pulse generator is electrically connected with the input end of the single DMOS driving circuit, and the output end of the single DMOS driving circuit is electrically connected with the output circuit; the single DMOS driving circuit is used for combining and dividing the two paths of pulse signals from the double-pulse generator; the application aims at providing a high-voltage integrated circuit, mutual interference among DMOS tubes in the circuit is reduced by adopting a single DMOS driving circuit, and meanwhile, the design space is reduced.

Description

High-voltage integrated circuit
Technical Field
The invention relates to the technical field of semiconductor power devices, in particular to a high-voltage integrated circuit.
Background
A high voltage integrated circuit, HVIC, is an integrated circuit product that converts MCU signals to drive IGBT signals. The HVIC integrates a PMOS tube, an NMOS tube, a triode, a diode, a voltage regulator tube, a resistor and a capacitor together to form a combined circuit. The HVIC receives the control signal of the MCU on one hand and drives the subsequent IGBT or MOS to work, and sends the state detection signal of the system back to the MCU on the other hand, and the HVIC is a key chip in the IPM.
At present, the mainstream high-voltage drive HVIC in the market is characterized in that each high-side drive circuit uses two DMOS tubes to convert low and high-voltage drive signals, a drive circuit consisting of the two DMOS tubes is adopted, the two DMOS tubes are easy to generate mutual interference when the drive circuit works, and meanwhile, the occupied area of module design can be increased by the aid of the DMOS tubes, and the miniaturization of a module is not facilitated.
Disclosure of Invention
The invention aims to provide a high-voltage integrated circuit, which reduces mutual interference among DMOS tubes in the circuit by adopting a single DMOS driving circuit and reduces design space at the same time.
In order to achieve the purpose, the invention adopts the following technical scheme: a high-voltage integrated circuit comprises a Schmitt circuit, a filter, a level conversion circuit, a double-pulse generator, a single DMOS drive circuit and an output circuit; the input end of the Schmitt circuit is electrically connected with an input signal, the output end of the Schmitt circuit is electrically connected with the input end of the filter, the output end of the filter is electrically connected with the input end of the level switching circuit, the output end of the level switching circuit is electrically connected with the input end of the double-pulse generator, the output end of the double-pulse generator is electrically connected with the input end of the single DMOS driving circuit, and the output end of the single DMOS driving circuit is electrically connected with the output circuit; the single DMOS driving circuit is used for combining and dividing the two paths of pulse signals from the double-pulse generator.
Preferably, the single DMOS driving circuit includes an or gate, a first DMOS transistor Q1, a not gate, a divide-by-two circuit and a resistor R1; the input end of the or gate is electrically connected with the output end of the double-pulse generator, the output end of the or gate is electrically connected with the gate of the first DMOS tube Q1, the source of the first DMOS tube Q1 is grounded, the drain of the first DMOS tube Q1 is electrically connected with the input end of the not gate and one end of the resistor R1, the other end of the resistor R1 is electrically connected with the output circuit, the output end of the not gate is electrically connected with the input end of the divide-by-two circuit, and the output end of the divide-by-two circuit is electrically connected with the input end of the output circuit.
Preferably, the inverter further comprises an electrostatic discharge circuit, one end of the electrostatic discharge circuit is electrically connected to the input end of the not gate, and the other end of the electrostatic discharge circuit is grounded.
Preferably, the electrostatic discharge circuit comprises a zener diode D1, a negative terminal of the zener diode D1 is electrically connected to the input terminal of the not gate, and a positive terminal of the zener diode D1 is grounded.
Preferably, the electrostatic discharge circuit comprises a MOS transistor Q4, the drain of the MOS transistor Q4 is electrically connected to the input terminal of the not gate, and the source and the gate of the MOS transistor Q4 are grounded.
Preferably, the output circuit comprises a MOS transistor Q2, a MOS transistor Q3, a resistor R2 and a resistor R3; the grid electrode of the MOS tube Q2 and the grid electrode of the MOS tube Q3 are both electrically connected with the output end of the two-frequency dividing circuit, and the drain electrode of the MOS tube Q2 is electrically connected with the other end of the resistor R1 and serves as a module output end VB; the source electrode of the MOS transistor Q2 is electrically connected with one end of a resistor R2, and the other end of the resistor R2 is electrically connected with one end of a resistor R3 and serves as a module output end HO; the drain electrode of the MOS transistor Q3 is electrically connected with the other end of the resistor R3, and the source electrode of the MOS transistor Q3 is used as the output end VS.
The technical scheme of the invention has the beneficial effects that: the single DMOS driving circuit adopts a single DMOS tube to complete the conversion of driving signals, replaces the original two DMOS tubes to perform the conversion of high-voltage and low-voltage driving signals, does not have the mutual interference between the two DMOS tubes, can reduce the circuit design area of a high-voltage transition region and a low-voltage transition region by adopting the single DMOS tube, and reduces the interference problem generated when the high-voltage DMOS tube works at high frequency. Compared with the existing two DMOS tube circuits, the single DMOS tube reduces the electrostatic discharge capacity of a high-voltage region when receiving high-voltage pulse, and has higher reliability.
Drawings
FIG. 1 is a schematic circuit connection diagram of one embodiment of the present invention;
FIG. 2 is a schematic connection diagram of an electrostatic discharge circuit according to embodiment 1 of the present invention;
fig. 3 is a schematic connection diagram of an electrostatic discharge circuit according to embodiment 2 of the present invention.
Wherein: the circuit comprises a Schmitt circuit 1, a filter 2, a level conversion circuit 3, a double-pulse generator 4, a single DMOS drive circuit 5, an OR gate 51, a NOT gate 52, a frequency-halving circuit 53, an electrostatic discharge circuit 54 and an output circuit 6.
Detailed Description
The technical scheme of the invention is further explained by the specific implementation mode in combination with the attached drawings.
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
In the description of the present invention, "a plurality" means two or more unless otherwise specified.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Example 1
Referring to fig. 1 and 2, a high voltage integrated circuit includes a schmitt circuit 1, a filter 2, a level shift circuit 3, a double pulse generator 4, a single DMOS driving circuit 5, and an output circuit 6; the input end of the schmitt circuit 1 is electrically connected with an input signal, the output end of the schmitt circuit 1 is electrically connected with the input end of the filter 2, the output end of the filter 2 is electrically connected with the input end of the level shift circuit 3, the output end of the level shift circuit 3 is electrically connected with the input end of the double-pulse generator 4, the output end of the double-pulse generator 4 is electrically connected with the input end of the single DMOS driving circuit 5, and the output end of the single DMOS driving circuit 5 is electrically connected with the output circuit 6; the single DMOS driving circuit 5 is configured to combine and divide the frequency of the two pulse signals from the double pulse generator 4.
The single DMOS driving circuit 5 adopts a single DMOS tube to complete the conversion of driving signals, replaces the original two DMOS tubes to perform the conversion of high-voltage and low-voltage driving signals, does not have mutual interference between the two DMOS tubes, can reduce the circuit design area of a high-voltage transition region and a low-voltage transition region by adopting the single DMOS tube, and reduces the interference problem generated when the high-voltage DMOS tube works at high frequency. Compared with the existing two DMOS tube circuits, the single DMOS tube reduces the electrostatic discharge capacity of a high-voltage area when receiving high-voltage pulse, and has higher reliability.
Preferably, the single DMOS driving circuit 5 includes an or gate 51, a first DMOS transistor Q1, a not gate 52, a divide-by-two circuit 53 and a resistor R1; the input end of the or gate 51 is electrically connected to the output end of the double pulse generator 4, the output end of the or gate 51 is electrically connected to the gate of the first DMOS transistor Q1, the source of the first DMOS transistor Q1 is grounded, the drain of the first DMOS transistor Q1 is electrically connected to the input end of the not gate 52 and one end of the resistor R1, the other end of the resistor R1 is electrically connected to the output circuit 6, the output end of the not gate 52 is electrically connected to the input end of the divide-by-two circuit 53, and the output end of the divide-by-two circuit 53 is electrically connected to the input end of the output circuit 6.
With the structure, after the input end of the double-pulse generator 4 receives a high-level signal, the double-pulse generator 4 detects the rising edge and the falling edge of the signal, the double-pulse generator 4 outputs two paths of high-level pulse signals a1 and b1 which are several times of nanoseconds from two output ends, when any one of the two paths of high-level pulse signals a1 and b1 is high from the two output ends, the or gate 51 outputs a high-level signal G1, the high-level signal G1 output by the or gate 51 drives the first DMOS tube Q1 to be turned on and off, the input end of the not gate 52 is used for detecting the voltage of the drain of the first DMOS tube Q1, the output end of the not gate 52 outputs a pulse signal with the same pulse width and polarity as the high-level signal G1, the input end of the halving frequency circuit 53 detects the pulse signal output by the not gate 52, the output end of the halving frequency circuit 53 outputs a pulse signal, the frequency of the pulse signal is one-half of the frequency of the pulse signal output by the not gate 52, thereby completing the function of transmitting the pulse signal of the low voltage area to the high voltage area. By adopting the circuit, a single DMOS tube is used as a driving circuit, the switching frequency is twice of that of a traditional double DMOS tube driving circuit, and the frequency division is carried out by a frequency division circuit 53 to obtain an output signal consistent with that of the traditional double DMOS tube driving circuit.
Specifically, the electrostatic discharge circuit 54 is further included, one end of the electrostatic discharge circuit 54 is electrically connected to the input end of the not gate 52, and the other end of the electrostatic discharge circuit 54 is grounded.
Meanwhile, the electrostatic discharge circuit 54 includes a zener diode D1, a negative terminal of the zener diode D1 is electrically connected to the input terminal of the not gate 52, and a positive terminal of the zener diode D1 is grounded.
In this embodiment, a zener diode D1 is connected in parallel to the first DMOS transistor Q1 to serve as an esd protection circuit 54, which has better reliability than the conventional driving circuit.
Preferably, the output circuit 6 includes a MOS transistor Q2, a MOS transistor Q3, a resistor R2, and a resistor R3; the grid electrode of the MOS tube Q2 and the grid electrode of the MOS tube Q3 are both electrically connected with the output end of the two-frequency dividing circuit 53, and the drain electrode of the MOS tube Q2 is electrically connected with the other end of the resistor R1 and serves as a module output end VB; the source electrode of the MOS transistor Q2 is electrically connected with one end of a resistor R2, and the other end of the resistor R2 is electrically connected with one end of a resistor R3 and serves as a module output end HO; the drain of the MOS transistor Q3 is electrically connected to the other end of the resistor R3, and the source of the MOS transistor Q3 is used as the output terminal VS.
Example 2
Referring to fig. 3, the structure of the present embodiment is substantially the same as that of embodiment 1, except that: the electrostatic discharge circuit 54 includes a MOS transistor Q4, a drain of the MOS transistor Q4 is electrically connected to the input terminal of the not gate 52, and a source and a gate of the MOS transistor Q4 are grounded.
In this embodiment, the MOS transistor Q4 is connected in parallel to the first DMOS transistor Q1 to serve as the esd protection circuit 54, which has better reliability than the conventional driving circuit.
In the description herein, references to the description of the terms "embodiment," "example," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The technical principle of the present invention is described above in connection with specific embodiments. The description is made for the purpose of illustrating the principles of the invention and should not be taken in any way as limiting the scope of the invention. Based on the explanations herein, those skilled in the art will be able to conceive of other embodiments of the present invention without inventive effort, which would fall within the scope of the present invention.

Claims (6)

1. A high-voltage integrated circuit is characterized by comprising a Schmitt circuit, a filter, a level conversion circuit, a double-pulse generator, a single DMOS driving circuit and an output circuit; the input end of the Schmitt circuit is electrically connected with an input signal, the output end of the Schmitt circuit is electrically connected with the input end of the filter, the output end of the filter is electrically connected with the input end of the level switching circuit, the output end of the level switching circuit is electrically connected with the input end of the double-pulse generator, the output end of the double-pulse generator is electrically connected with the input end of the single DMOS driving circuit, and the output end of the single DMOS driving circuit is electrically connected with the output circuit; the single DMOS driving circuit is used for combining and dividing the two paths of pulse signals from the double-pulse generator.
2. The high voltage integrated circuit of claim 1, wherein the single DMOS driver circuit includes an or gate, a first DMOS transistor Q1, a not gate, a divide-by-two circuit, and a resistor R1; the input end of the or gate is electrically connected with the output end of the double-pulse generator, the output end of the or gate is electrically connected with the gate of the first DMOS tube Q1, the source of the first DMOS tube Q1 is grounded, the drain of the first DMOS tube Q1 is electrically connected with the input end of the not gate and one end of the resistor R1, the other end of the resistor R1 is electrically connected with the output circuit, the output end of the not gate is electrically connected with the input end of the divide-by-two circuit, and the output end of the divide-by-two circuit is electrically connected with the input end of the output circuit.
3. The high-voltage integrated circuit according to claim 2, further comprising an electrostatic discharge circuit, wherein one end of the electrostatic discharge circuit is electrically connected to the input terminal of the not gate, and the other end of the electrostatic discharge circuit is grounded.
4. The high-voltage integrated circuit according to claim 3, wherein the electrostatic discharge circuit comprises a zener diode D1, the negative terminal of the zener diode D1 is electrically connected to the input terminal of the NOT gate, and the positive terminal of the zener diode D1 is grounded.
5. The high-voltage integrated circuit according to claim 3, wherein the electrostatic discharge circuit comprises a MOS transistor Q4, a drain of the MOS transistor Q4 is electrically connected with the input terminal of the NOT gate, and a source and a gate of the MOS transistor Q4 are grounded.
6. The high-voltage integrated circuit as claimed in claim 2, wherein the output circuit comprises a MOS transistor Q2, a MOS transistor Q3, a resistor R2 and a resistor R3; the grid electrode of the MOS tube Q2 and the grid electrode of the MOS tube Q3 are both electrically connected with the output end of the two-frequency dividing circuit, and the drain electrode of the MOS tube Q2 is electrically connected with the other end of the resistor R1 and serves as a module output end VB; the source electrode of the MOS transistor Q2 is electrically connected with one end of a resistor R2, and the other end of the resistor R2 is electrically connected with one end of a resistor R3 and serves as a module output end HO; the drain of the MOS transistor Q3 is electrically connected to the other end of the resistor R3, and the source of the MOS transistor Q3 is used as the output terminal VS.
CN202210250667.1A 2022-03-15 2022-03-15 High-voltage integrated circuit Pending CN114614805A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210250667.1A CN114614805A (en) 2022-03-15 2022-03-15 High-voltage integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210250667.1A CN114614805A (en) 2022-03-15 2022-03-15 High-voltage integrated circuit

Publications (1)

Publication Number Publication Date
CN114614805A true CN114614805A (en) 2022-06-10

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210250667.1A Pending CN114614805A (en) 2022-03-15 2022-03-15 High-voltage integrated circuit

Country Status (1)

Country Link
CN (1) CN114614805A (en)

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