CN114613316B - Driving circuit of display panel and display device - Google Patents
Driving circuit of display panel and display device Download PDFInfo
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- CN114613316B CN114613316B CN202210141764.7A CN202210141764A CN114613316B CN 114613316 B CN114613316 B CN 114613316B CN 202210141764 A CN202210141764 A CN 202210141764A CN 114613316 B CN114613316 B CN 114613316B
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- 102100036285 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Human genes 0.000 description 1
- 101000875403 Homo sapiens 25-hydroxyvitamin D-1 alpha hydroxylase, mitochondrial Proteins 0.000 description 1
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- 101100102583 Schizosaccharomyces pombe (strain 972 / ATCC 24843) vgl1 gene Proteins 0.000 description 1
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- 230000009286 beneficial effect Effects 0.000 description 1
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Dc-Dc Converters (AREA)
Abstract
The application discloses a driving circuit of a display panel and display equipment, wherein the driving circuit comprises a power supply module and a boosting module connected with the power supply module, the power supply module is used for outputting a first logic voltage, a first negative reference voltage and a first positive reference voltage, the driving circuit comprises a power supply time sequence control circuit, the power supply time sequence control circuit is connected between the power supply module and the boosting module, and the power supply time sequence control circuit is used for receiving the first logic voltage, the first negative reference voltage and the first positive reference voltage and sequentially outputting a second logic voltage, a second negative reference voltage and the second positive reference voltage to the boosting module. Based on the above manner, the reliability of the driving circuit can be improved.
Description
Technical Field
The present application relates to the field of display technologies, and in particular, to a driving circuit of a display panel and a display device.
Background
In the prior art, a power module and a boost module are generally disposed in a driving circuit of a display panel, where the power module is configured to output a logic voltage, a negative reference voltage and a positive reference voltage to the boost module, so that the boost module performs corresponding boost processing based on the received voltage.
The prior art has the defects that when the power supply chip generates the logic voltage, the negative reference voltage and the positive reference voltage, the logic voltage and the positive reference voltage are synchronously generated and output to the boost module after the power supply voltage is received, the negative reference voltage can be generated and output to the boost module, and when the boost module does not receive the negative reference voltage and receives the logic voltage and the positive reference voltage, the boost module can trigger an overcurrent protection mechanism to enable the whole driving circuit to not normally operate, so that the reliability of the driving circuit is reduced.
Disclosure of Invention
The application mainly solves the technical problem of improving the reliability of the driving circuit.
In order to solve the technical problems, the first technical scheme adopted by the application is as follows: the driving circuit of the display panel comprises a power supply module and a boosting module connected with the power supply module, wherein the power supply module is used for outputting a first logic voltage, a first negative reference voltage and a first positive reference voltage, the driving circuit comprises a power supply time sequence control circuit, the power supply time sequence control circuit is connected between the power supply module and the boosting module, and the power supply time sequence control circuit is used for receiving the first logic voltage, the first negative reference voltage and the first positive reference voltage and sequentially outputting a second logic voltage, a second negative reference voltage and the second positive reference voltage to the boosting module.
The power supply time sequence control circuit comprises a first time sequence circuit, a second time sequence circuit and a third time sequence circuit; the first timing circuit is used for outputting a second logic voltage to the boosting module when the first logic voltage reaches a preset logic voltage difference threshold value; the second time sequence circuit is used for outputting a second negative reference voltage to the boosting module after the boosting module receives the first logic voltage; the third timing circuit is used for outputting a second positive reference voltage to the boosting module after the boosting module receives the first negative reference voltage.
The input end of the first timing circuit is connected with the power supply module, and the output end of the first timing circuit is connected with the boosting module; the input end of the second time sequence circuit is connected with the power supply module, the output end of the second time sequence circuit is connected with the boosting module, and the driving end of the second time sequence circuit is connected with the output end of the first time sequence circuit; the input end of the third time sequence circuit is connected with the power supply module, the output end of the third time sequence circuit is connected with the boosting module, and the driving end of the third time sequence circuit is connected with the output end of the second time sequence circuit.
Wherein the first timing circuit includes: one end of the first switching tube is connected with the logic voltage output end of the power supply module, and the other end of the first switching tube is connected with the logic voltage input end of the boosting module; one end of the first resistor is connected with one end of the first switching tube, and the other end of the first resistor is connected with the driving end of the first switching tube; one end of the second resistor is connected with the driving end of the first switch tube, and the other end of the second resistor is grounded.
Wherein the second sequential circuit includes: one end of the second switching tube is connected with the negative reference voltage output end of the power supply module, and the other end of the second switching tube is connected with the negative reference voltage input end of the boosting module; one end of the third resistor is connected with one end of the second switching tube, and the other end of the third resistor is connected with the driving end of the second switching tube; and one end of the fourth resistor is connected with the driving end of the second switching tube, and the other end of the fourth resistor is connected with the logic voltage input end of the boosting module.
Wherein the third sequential circuit includes: one end of the third switching tube is connected with the positive reference voltage output end of the power supply module, and the other end of the third switching tube is connected with the positive reference voltage input end of the boosting module; one end of the fifth resistor is connected with one end of the third switching tube, and the other end of the fifth resistor is connected with the driving end of the third switching tube; and one end of the sixth resistor is connected with the driving end of the third switching tube, and the other end of the sixth resistor is connected with the negative reference voltage input end of the boosting module.
The first switching tube is a PMOS tube, one end of the first switching tube is a source electrode, and the driving end of the first switching tube is a grid electrode; the second switching tube is an NMOS tube, one end of the second switching tube is a source electrode, and the driving end of the second switching tube is a grid electrode; the third switching tube is a PMOS tube, one end of the third switching tube is a source electrode, and the driving end of the third switching tube is a grid electrode; when the gate-source voltage difference of the first switching tube reaches a first voltage difference threshold, one end of the first switching tube is conducted with the other end, wherein the gate-source voltage difference of the first switching tube is a product obtained by multiplying a first logic voltage by a first resistance ratio, and the first resistance ratio is a quotient obtained by dividing the resistance value of the first resistor by the sum of the resistance value of the first resistor and the resistance value of the second resistor; when the gate-source voltage difference of the second switching tube reaches a second voltage difference threshold value, one end of the second switching tube is conducted with the other end, wherein the gate-source voltage difference of the second switching tube is a product obtained by multiplying a first voltage difference by a second resistance ratio, the first voltage difference is a difference value between a second logic voltage and a first negative reference voltage, and the second resistance ratio is a quotient obtained by dividing a resistance value of a third resistor by a sum of a resistance value of the third resistor and a resistance value of a fourth resistor; when the gate-source voltage difference of the third switching tube reaches a third voltage difference threshold, one end of the third switching tube is conducted with the other end, wherein the gate-source voltage difference of the third switching tube is a product obtained by multiplying a second voltage difference by a third resistance ratio, the second voltage difference is a difference value between a first positive reference voltage and a second negative reference voltage, and the third resistance ratio is a quotient obtained by dividing a resistance value of a fifth resistor by a sum of the resistance value of the fifth resistor and the resistance value of a sixth resistor.
The power supply module comprises a voltage reducing circuit, a negative pressure circuit and a pressurizing circuit; the voltage-reducing circuit receives the power supply voltage and outputs a first logic voltage based on the power supply voltage, the voltage-reducing circuit receives the power supply voltage and outputs a first negative reference voltage based on the power supply voltage, and the voltage-increasing circuit receives the power supply voltage and outputs a first positive reference voltage based on the power supply voltage.
The boosting module comprises a logic circuit and a voltage boosting circuit, and the logic circuit is connected with the voltage boosting circuit; the logic circuit receives a second logic voltage, and the voltage boosting circuit receives a second negative reference voltage and a second positive reference voltage respectively.
In order to solve the technical problems, a second technical scheme adopted by the application is as follows: a display device includes a display panel, a processor, and a driving circuit of the display panel.
The application has the beneficial effects that: compared with the prior art, the application is characterized in that the power supply time sequence control circuit is arranged between the power supply module and the boosting module, the power supply time sequence control circuit is used for receiving the first logic voltage, the first negative reference voltage and the first positive reference voltage, and sequentially outputting the second logic voltage, the second negative reference voltage and the second positive reference voltage to the boosting module based on the received voltages, so that the boosting module can sequentially receive the logic voltage, the negative reference voltage and the positive reference voltage, and the phenomenon that the whole driving circuit cannot normally operate due to the false triggering of an overcurrent protection mechanism of the boosting module is avoided, and the reliability of the driving circuit is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a first embodiment of a driving circuit of a display panel of the present application;
fig. 2 is a schematic structural diagram of a second embodiment of a driving circuit of the display panel of the present application;
FIG. 3 is a schematic diagram of a driving circuit of a display panel according to a third embodiment of the present application;
FIG. 4 is a schematic diagram of voltage waveforms in an application scenario of the present application;
Fig. 5 is a schematic structural view of a fourth embodiment of a driving circuit of the display panel of the present application;
Fig. 6 is a schematic structural view of an embodiment of the display device of the present application.
The reference numerals are: a power supply module 11; a step-down circuit 111; a negative pressure circuit 112; a pressurization circuit 113; a boost module 12; a logic circuit 121; a voltage boost circuit 122; a power supply timing control circuit 13; a first timing circuit 131; a first switching tube 1311; a first resistor 1312; a second resistor 1313; a second timing circuit 132; a second switching tube 1321; a third resistor 1322; a fourth resistor 1323; a third timing circuit 133; a third switching tube 1331; a fifth resistor 1332; a sixth resistor 1333; a display device 60; a driving circuit 61; a processor 62; and a display panel 63.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to fall within the scope of the present application.
The terms "first" and "second" in the present application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
The present application firstly proposes a driving circuit of a display panel, as shown in fig. 1, fig. 1 is a schematic structural diagram of a first embodiment of the driving circuit of the display panel of the present application, the driving circuit includes: the power supply device comprises a power supply module 11, a boosting module 12 connected with the power supply module 11 and a power supply time sequence control circuit 13 connected between the power supply module 11 and the boosting module 12, wherein the power supply module 11 is connected with the boosting module 12 through the power supply time sequence control circuit 13.
The power supply module 11 is configured to output a first logic voltage, a first negative reference voltage, and a first positive reference voltage, and the power supply timing control circuit 13 is configured to receive the first logic voltage, the first negative reference voltage, and the first positive reference voltage output by the power supply module 11, and sequentially output a second logic voltage, a second negative reference voltage, and a second positive reference voltage to the boost module 12.
It should be noted that, when the boost module 12 can sequentially receive the corresponding voltages according to the order of the second logic voltage, the second negative reference voltage and the second positive reference voltage, the boost module 12 will not trigger the overcurrent protection mechanism of itself by mistake due to receiving the second positive reference voltage in advance, so as to avoid the phenomenon that the drive circuit of the whole display panel is turned off due to the false triggering of the overcurrent protection mechanism in the normal driving process of the boost module 12.
Specifically, as shown in fig. 1, the power timing control circuit 13 may sequentially output the received first logic voltage (VDD 1 shown in fig. 1), the first negative reference voltage (VGL 1 shown in fig. 1), and the first positive reference voltage (VGH 1 shown in fig. 1) output by the power module 11, and sequentially output the second logic voltage (VDD 2 shown in fig. 1), the second negative reference voltage (VGL 2 shown in fig. 1), and the second positive reference voltage (VGH 2 shown in fig. 1) to the boosting module 12.
Compared with the prior art, the application is characterized in that the power supply time sequence control circuit is arranged between the power supply module and the boosting module, the power supply time sequence control circuit is used for receiving the first logic voltage, the first negative reference voltage and the first positive reference voltage, and sequentially outputting the second logic voltage, the second negative reference voltage and the second positive reference voltage to the boosting module based on the received voltages, so that the boosting module can sequentially receive the logic voltage, the negative reference voltage and the positive reference voltage, and the phenomenon that the whole driving circuit cannot normally operate due to the false triggering of an overcurrent protection mechanism of the boosting module is avoided, and the reliability of the driving circuit is improved.
The present application also provides a driving circuit of a display panel, as shown in fig. 2, fig. 2 is a schematic structural diagram of a second embodiment of the driving circuit of the display panel of the present application, where the driving circuit includes: the power supply device comprises a power supply module 11, a boosting module 12 connected with the power supply module 11 and a power supply time sequence control circuit 13 connected between the power supply module 11 and the boosting module 12, wherein the power supply module 11 is connected with the boosting module 12 through the power supply time sequence control circuit 13.
The power supply module 11 is configured to output a first logic voltage, a first negative reference voltage, and a first positive reference voltage, and the power supply timing control circuit 13 is configured to receive the first logic voltage, the first negative reference voltage, and the first positive reference voltage output by the power supply module 11, and sequentially output a second logic voltage, a second negative reference voltage, and a second positive reference voltage to the boost module 12.
The power supply timing control circuit 13 includes a first timing circuit 131, a second timing circuit 132, and a third timing circuit 133.
The first timing circuit 131 is configured to output a second logic voltage to the boosting module when the first logic voltage reaches a preset logic voltage difference threshold. The second timing circuit 132 is configured to output the first negative reference voltage to the boost module 12 after the boost module receives the second logic voltage. The third timing circuit 133 is configured to output the first positive reference voltage to the boost module after the boost module 12 receives the second negative reference voltage.
Specifically, as shown in fig. 2, the logic voltage output terminal a of the power module 11 is configured to output a first logic voltage, the negative reference voltage output terminal B of the power module 11 is configured to output a first negative reference voltage, the positive reference voltage output terminal C of the power module 11 is configured to output a first positive reference voltage, the logic voltage input terminal D of the boost module 12 is configured to receive a second logic voltage, the negative reference voltage input terminal E of the boost module 12 is configured to receive a second negative reference voltage, and the positive reference voltage input terminal F of the boost module 12 is configured to receive a second positive reference voltage.
Alternatively, as shown in fig. 2, an input end of the first timing circuit 131 is connected to the power module 11, and an output end of the first timing circuit 131 is connected to the boost module 12.
The input end of the second timing circuit 132 is connected to the power module 11, the output end of the second timing circuit is connected to the boost module 12, and the driving end of the second timing circuit 132 is connected to the output end of the first timing circuit 131.
The input end of the third timing circuit 133 is connected to the power module 11, the output end of the third timing circuit 133 is connected to the boost module 12, and the driving end of the third timing circuit 133 is connected to the output end of the second timing circuit 132.
Specifically, as shown in fig. 2, the input end of the first timing circuit 131 is connected to the logic voltage output end a of the power module 11, and the output end of the first timing circuit 131 is connected to the logic voltage input end D of the boost module 12.
The input end of the second timing circuit 132 is connected to the negative reference voltage output end B of the power module 11, the output end of the second timing circuit 132 is connected to the negative reference voltage input end E of the boost module 12, and the driving end G of the second timing circuit 132 is connected to the output end of the first timing circuit 131 or the logic voltage input end D of the boost module 12.
The input end of the third timing circuit 133 is connected to the positive reference voltage output end C of the power module 11, the output end of the third timing circuit 133 is connected to the positive reference voltage input end F of the boost module 12, and the driving end H of the third timing circuit 133 is connected to the output end of the second timing circuit 132 or the negative reference input end E of the boost module 12.
Compared with the prior art, the application is characterized in that the power supply time sequence control circuit is arranged between the power supply module and the boosting module, the power supply time sequence control circuit is used for receiving the first logic voltage, the first negative reference voltage and the first positive reference voltage, and sequentially outputting the second logic voltage, the second negative reference voltage and the second positive reference voltage to the boosting module based on the received voltages, so that the boosting module can sequentially receive the logic voltage, the negative reference voltage and the positive reference voltage, and the phenomenon that the whole driving circuit cannot normally operate due to the false triggering of an overcurrent protection mechanism of the boosting module is avoided, and the reliability of the driving circuit is improved.
The present application also provides a driving circuit of a display panel, as shown in fig. 3, fig. 3 is a schematic structural diagram of a third embodiment of the driving circuit of the display panel of the present application, where the driving circuit includes: the power supply device comprises a power supply module 11, a boosting module 12 connected with the power supply module 11 and a power supply time sequence control circuit 13 connected between the power supply module 11 and the boosting module 12, wherein the power supply module 11 is connected with the boosting module 12 through the power supply time sequence control circuit 13.
The power supply module 11 is configured to output a first logic voltage, a first negative reference voltage, and a first positive reference voltage, and the power supply timing control circuit 13 is configured to receive the first logic voltage, the first negative reference voltage, and the first positive reference voltage output by the power supply module 11, and sequentially output a second logic voltage, a second negative reference voltage, and a second positive reference voltage to the boost module 12.
The power supply timing control circuit 13 includes a first timing circuit 131, a second timing circuit 132, and a third timing circuit 133.
The first timing circuit 131 is configured to output a second logic voltage to the boosting module when the first logic voltage reaches a preset logic voltage difference threshold. The second timing circuit 132 is configured to output the first negative reference voltage to the boost module 12 after the boost module receives the second logic voltage. The third timing circuit 133 is configured to output the first positive reference voltage to the boost module after the boost module 12 receives the second negative reference voltage.
The first timing circuit 131 includes: a first switching tube 1311, a first resistor 1312, and a second resistor 1313.
One end of the first switch tube 1311 is connected with the logic voltage output end A of the power module 11, the other end of the first switch tube 1311 is connected with the logic voltage input end D of the boosting module 12, one end of the first resistor 1312 is connected with one end of the first switch tube 1311, the other end of the first resistor 1312 is connected with the driving end of the first switch tube 1311, one end of the second resistor 1313 is connected with the driving end of the first switch tube 1311, and the other end of the second resistor 1313 is grounded.
Specifically, as shown in fig. 3, the first switching tube 1311 is a PMOS tube, one end (the end connected to the logic voltage output terminal a of the power module 11) of the first switching tube 1311 is a source, and the driving end of the first switching tube 1311 is a gate.
The gate-source voltage difference of the first switching transistor 1311 is a product obtained by multiplying a first logic voltage by a first resistance ratio, and the first resistance 1312 ratio is a quotient obtained by dividing a resistance value of the first resistance 1312 by a sum of a resistance value of the first resistance 1312 and a resistance value of the second resistance 1313. When the gate-source voltage difference of the first switch tube 1311 reaches the first voltage difference threshold, the first switch tube 1311 is turned on, that is, one end of the first switch tube 1311 is turned on with the other end, so that the logic voltage input terminal D of the boost module 12 receives the second logic voltage corresponding to the first logic voltage output by the logic voltage output terminal a of the power module 11.
Optionally, as shown in fig. 3, the second timing circuit 132 includes: a second switching tube 1321, a third resistor 1322 and a fourth resistor 1323.
One end of the second switching tube 1321 is connected with the negative reference voltage output end B of the power module 11, the other end of the second switching tube 1321 is connected with the negative reference voltage input end E of the boosting module 12, one end of the third resistor 1322 is connected with one end of the second switching tube 1321, the other end of the third resistor 1322 is connected with the driving end of the second switching tube 1321, one end of the fourth resistor 1323 is connected with the driving end of the second switching tube 1321, and the other end of the fourth resistor 1323 is connected with the logic voltage input end D of the boosting module 12.
Specifically, as shown in fig. 3, the second switching tube 1321 is an NMOS tube, one end of the second switching tube 1321 (the end connected to the negative reference voltage output end B of the power module 11) is a source, and the driving end of the second switching tube 1321 is a gate.
The gate-source voltage difference of the second switching transistor 1321 is a product obtained by multiplying a first voltage difference by a second resistance ratio, the first voltage difference being a difference between the second logic voltage and the first negative reference voltage, and the second resistance ratio being a quotient obtained by dividing a resistance value of the third resistor 1322 by a sum of a resistance value of the third resistor 1322 and a resistance value of the fourth resistor 1323. When the gate-source voltage difference of the second switching tube 1321 reaches the second voltage difference threshold, the second switching tube 1321 is turned on, that is, one end of the second switching tube 1321 is turned on with the other end, so that the negative reference voltage input terminal E of the boost module 12 receives the second negative reference voltage corresponding to the first negative reference voltage output by the negative reference voltage output terminal B of the power module 11.
Further, the third timing circuit 133 includes: a third switching tube 1331, a fifth resistor 1332, and a sixth resistor 1333.
One end of the third switch tube 1331 is connected with the positive reference voltage output end C of the power supply module, the other end of the third switch tube 1331 is connected with the positive reference voltage input end F of the boosting module, one end of the fifth resistor 1332 is connected with one end of the third switch tube 1331, the other end of the fifth resistor 1332 is connected with the driving end of the third switch tube 1331, one end of the sixth resistor 1333 is connected with the driving end of the third switch tube 1331, and the other end of the sixth resistor 1333 is connected with the negative reference voltage input end E of the boosting module.
Specifically, as shown in fig. 3, the third switching tube 1331 is a PMOS tube, one end of the third switching tube 1331 is a source electrode, and the driving end of the third switching tube 1331 is a gate electrode.
The gate-source voltage difference of the third switching tube 1331 is a product obtained by multiplying a second voltage difference by a third resistance ratio, the second voltage difference is a difference between the first positive reference voltage and the second negative reference voltage, and the third resistance ratio is a quotient obtained by dividing a resistance value of the fifth resistor 1332 by a sum of a resistance value of the fifth resistor 1332 and a resistance value of the sixth resistor 1333. When the gate-source voltage difference of the third switching tube 1331 reaches the third voltage difference threshold, one end of the third switching tube 1331 is turned on with the other end, that is, one end of the third switching tube 1331 is turned on with the other end, so that the positive reference voltage input end F of the boost module 12 receives the second positive reference voltage corresponding to the first positive reference voltage output by the positive reference voltage output end C of the power module 11.
It should be noted that, based on the above manner, the time difference between the second logic voltage received by the boost module 12 and the power voltage received by the power module 11 may be adjusted by adjusting the magnitude of the first resistance ratio, the time difference between the second negative reference voltage received by the boost module 12 and the second logic voltage received by the boost module 12 may be adjusted by adjusting the magnitude of the second resistance ratio, and the time difference between the second positive reference voltage received by the boost module 12 and the second negative reference voltage received by the boost module 12 may be adjusted by adjusting the magnitude of the third resistance ratio.
For example, as shown in fig. 4, fig. 4 is a schematic diagram of voltage waveforms in an application scenario of the present application, the power supply voltage shown in fig. 4 is a power supply voltage of the power supply module 11, and the second logic voltage, the second negative reference voltage and the second positive reference voltage shown in fig. 4 are waveforms of voltages received by the boost module 12.
As shown in fig. 4, based on the above manner, the boost module 12 may sequentially receive the second logic voltage, the second negative reference voltage, and the second positive reference voltage, where the time difference T1 between the boost module 12 and the power module 11 receiving the power voltage may be adjusted by adjusting the magnitude of the first resistance ratio, the time difference T2 between the boost module 12 and the boost module 12 receiving the second logic voltage may be adjusted by adjusting the magnitude of the second resistance ratio, and the time difference T3 between the boost module 12 and the boost module 12 receiving the second positive reference voltage may be adjusted by adjusting the magnitude of the third resistance ratio, so as to achieve more precise control.
Compared with the prior art, the application is characterized in that the power supply time sequence control circuit is arranged between the power supply module and the boosting module, the power supply time sequence control circuit is used for receiving the first logic voltage, the first negative reference voltage and the first positive reference voltage, and sequentially outputting the second logic voltage, the second negative reference voltage and the second positive reference voltage to the boosting module based on the received voltages, so that the boosting module can sequentially receive the logic voltage, the negative reference voltage and the positive reference voltage, and the phenomenon that the whole driving circuit cannot normally operate due to the false triggering of an overcurrent protection mechanism of the boosting module is avoided, and the reliability of the driving circuit is improved.
The present application also provides a driving circuit of a display panel, as shown in fig. 5, fig. 5 is a schematic structural diagram of a fourth embodiment of the driving circuit of the display panel of the present application, the driving circuit includes: the power supply device comprises a power supply module 11, a boosting module 12 connected with the power supply module 11 and a power supply time sequence control circuit 13 connected between the power supply module 11 and the boosting module 12, wherein the power supply module 11 is connected with the boosting module 12 through the power supply time sequence control circuit 13.
The power supply module 11 is configured to output a first logic voltage, a first negative reference voltage, and a first positive reference voltage, and the power supply timing control circuit 13 is configured to receive the first logic voltage, the first negative reference voltage, and the first positive reference voltage output by the power supply module 11, and sequentially output a second logic voltage, a second negative reference voltage, and a second positive reference voltage to the boost module 12.
The power supply module 11 includes a voltage step-down circuit 111, a negative voltage circuit 112, and a voltage step-up circuit 113.
The step-down circuit 111 receives a power supply voltage (e.g., VIN in fig. 5) and outputs a first logic voltage (e.g., VDD1 in fig. 5) based on the power supply voltage, the negative voltage circuit 112 receives the power supply voltage and outputs a first negative reference voltage (e.g., VGL1 in fig. 5) based on the power supply voltage, and the pressurization circuit 113 receives the power supply voltage and outputs a first positive reference voltage (e.g., VGH1 in fig. 5) based on the power supply voltage.
Specifically, the first logic voltage may be obtained by performing a step-down process on the power supply voltage by using the step-down circuit 111, the first negative reference voltage may be obtained by performing a negative-pressure process on the power supply voltage by using the negative-pressure circuit 112, and the first positive reference voltage may be obtained by performing a pressurization process on the power supply voltage by using the pressurization circuit 113.
Optionally, the boost module 12 includes a logic circuit 121 and a voltage boost circuit 122, and the logic circuit 121 is connected to the voltage boost circuit 122.
The logic circuit 121 receives a second logic voltage (e.g., VDD2 in fig. 5), and the voltage boost circuit receives a second negative reference voltage (e.g., VGL2 in fig. 5) and a second positive reference voltage (e.g., VGH2 in fig. 5), respectively.
Specifically, the second logic voltage may be an operating voltage of the logic circuit 121, after receiving the second logic voltage, the logic circuit 121 may output a signal to be boosted to the voltage boosting circuit, and the voltage boosting circuit 122 may perform a step-down or step-up process on the signal to be boosted based on the received second negative reference voltage and the second positive reference voltage, so as to obtain a driving signal (e.g. VOUT in fig. 5) to be output by the driving circuit.
Compared with the prior art, the application is characterized in that the power supply time sequence control circuit is arranged between the power supply module and the boosting module, the power supply time sequence control circuit is used for receiving the first logic voltage, the first negative reference voltage and the first positive reference voltage, and sequentially outputting the second logic voltage, the second negative reference voltage and the second positive reference voltage to the boosting module based on the received voltages, so that the boosting module can sequentially receive the logic voltage, the negative reference voltage and the positive reference voltage, and the phenomenon that the whole driving circuit cannot normally operate due to the false triggering of an overcurrent protection mechanism of the boosting module is avoided, and the reliability of the driving circuit is improved.
The present application also provides a display device, as shown in fig. 6, fig. 6 is a schematic structural diagram of an embodiment of the display device of the present application, and the display device 60 includes a display panel 63, a processor 62, and a driving circuit 61 of any of the display panels described in the previous embodiments.
Specifically, the display device 60 may further include: a data driving chip (not shown).
The data driving chip is connected to the driving circuit 61 for driving the display operation of the display panel 63 based on the driving signal transmitted from the driving circuit 61.
The power module 11 in the driving circuit 61 may include a PWM (Pulse width modulation ) chip for outputting a logic signal (VDD), a high voltage signal (VGH) and a low voltage signal (VGL), but may be other types of power chips, which are not limited herein.
The processor 62 may be any type of device having computing or data processing capabilities, and is not limited herein.
The display panel 63 may include a plurality of pixel units arranged in an array, each pixel unit including at least one light emitting device, such as an LED (light-emitting diode).
The display panel 63 may be any one of a TN (TWISTED NEMATIC ) panel, an IPS (In-PLANE SWITCHING, in-plane switching) panel, a VA (VERTICAL ALIGNMENT, vertically aligned) panel, and other types of display panels, which are not limited herein.
Compared with the prior art, the application is characterized in that the power supply time sequence control circuit is arranged between the power supply module and the boosting module, the power supply time sequence control circuit is used for receiving the first logic voltage, the first negative reference voltage and the first positive reference voltage, and sequentially outputting the second logic voltage, the second negative reference voltage and the second positive reference voltage to the boosting module based on the received voltages, so that the boosting module can sequentially receive the logic voltage, the negative reference voltage and the positive reference voltage, and the phenomenon that the whole driving circuit cannot normally operate due to the false triggering of an overcurrent protection mechanism of the boosting module is avoided, and the reliability of the driving circuit is improved.
The foregoing description is only of embodiments of the present application, and is not intended to limit the scope of the application, and all equivalent structures or equivalent processes using the descriptions and the drawings of the present application or directly or indirectly applied to other related technical fields are included in the scope of the present application.
Claims (10)
1. The driving circuit of display panel includes power supply module and boosting module connected with the power supply module, the power supply module is used for outputting first logic voltage, first negative reference voltage and first positive reference voltage,
The driving circuit comprises a power supply time sequence control circuit, the power supply time sequence control circuit is connected between the power supply module and the boosting module, and the power supply time sequence control circuit is used for receiving the first logic voltage, the first negative reference voltage and the first positive reference voltage and sequentially outputting a second logic voltage, the second negative reference voltage and the second positive reference voltage to the boosting module.
2. The drive circuit according to claim 1, wherein the power supply timing control circuit includes a first timing circuit, a second timing circuit, and a third timing circuit;
the first timing circuit is used for outputting the second logic voltage to the boosting module when the first logic voltage reaches a preset logic voltage difference threshold;
The second time sequence circuit is used for outputting the second negative reference voltage to the boosting module after the boosting module receives the first logic voltage;
The third timing circuit is used for outputting the second positive reference voltage to the boosting module after the boosting module receives the first negative reference voltage.
3. The driving circuit according to claim 2, wherein,
The input end of the first timing circuit is connected with the power supply module, and the output end of the first timing circuit is connected with the boosting module;
The input end of the second time sequence circuit is connected with the power supply module, the output end of the second time sequence circuit is connected with the boosting module, and the driving end of the second time sequence circuit is connected with the output end of the first time sequence circuit;
the input end of the third time sequence circuit is connected with the power supply module, the output end of the third time sequence circuit is connected with the boosting module, and the driving end of the third time sequence circuit is connected with the output end of the second time sequence circuit.
4. A driving circuit according to claim 2 or 3, wherein the first timing circuit comprises:
One end of the first switching tube is connected with the logic voltage output end of the power supply module, and the other end of the first switching tube is connected with the logic voltage input end of the boosting module;
One end of the first resistor is connected with one end of the first switching tube, and the other end of the first resistor is connected with the driving end of the first switching tube;
and one end of the second resistor is connected with the driving end of the first switching tube, and the other end of the second resistor is grounded.
5. The drive circuit of claim 4, wherein the second timing circuit comprises:
One end of the second switching tube is connected with the negative reference voltage output end of the power supply module, and the other end of the second switching tube is connected with the negative reference voltage input end of the boosting module;
one end of the third resistor is connected with one end of the second switching tube, and the other end of the third resistor is connected with the driving end of the second switching tube;
and one end of the fourth resistor is connected with the driving end of the second switching tube, and the other end of the fourth resistor is connected with the logic voltage input end of the boosting module.
6. The drive circuit according to claim 5, wherein the third timing circuit includes:
one end of the third switching tube is connected with the positive reference voltage output end of the power supply module, and the other end of the third switching tube is connected with the positive reference voltage input end of the boosting module;
One end of the fifth resistor is connected with one end of the third switching tube, and the other end of the fifth resistor is connected with the driving end of the third switching tube;
and one end of the sixth resistor is connected with the driving end of the third switching tube, and the other end of the sixth resistor is connected with the negative reference voltage input end of the boosting module.
7. The driving circuit of claim 6, wherein the first switching tube is a PMOS tube, one end of the first switching tube is a source, and the driving end of the first switching tube is a gate; the second switching tube is an NMOS tube, one end of the second switching tube is a source electrode, and the driving end of the second switching tube is a grid electrode; the third switching tube is a PMOS tube, one end of the third switching tube is a source electrode, and the driving end of the third switching tube is a grid electrode;
When the gate-source voltage difference of the first switching tube reaches a first voltage difference threshold, one end of the first switching tube is conducted with the other end of the first switching tube, wherein the gate-source voltage difference of the first switching tube is a product obtained by multiplying the first logic voltage by a first resistance ratio, and the first resistance ratio is a quotient obtained by dividing the resistance value of the first resistor by the sum of the resistance value of the first resistor and the resistance value of the second resistor;
When the gate-source voltage difference of the second switching tube reaches a second voltage difference threshold, one end of the second switching tube is conducted with the other end, wherein the gate-source voltage difference of the second switching tube is a product obtained by multiplying a first voltage difference by a second resistance ratio, the first voltage difference is a difference value between the second logic voltage and the first negative reference voltage, and the second resistance ratio is a quotient obtained by dividing a resistance value of the third resistor by a sum of a resistance value of the third resistor and a resistance value of the fourth resistor;
When the gate-source voltage difference of the third switching tube reaches a third voltage difference threshold, one end of the third switching tube is conducted with the other end of the third switching tube, wherein the gate-source voltage difference of the third switching tube is a product obtained by multiplying a second voltage difference by a third resistance ratio, the second voltage difference is a difference value between the first positive reference voltage and the second negative reference voltage, and the third resistance ratio is a quotient obtained by dividing a resistance value of the fifth resistor by a sum of a resistance value of the fifth resistor and a resistance value of the sixth resistor.
8. A drive circuit according to any one of claims 1 to 3, wherein the power supply module includes a step-down circuit, a negative-pressure circuit, and a pressurizing circuit;
the step-down circuit receives a power supply voltage and outputs the first logic voltage based on the power supply voltage, the negative voltage circuit receives the power supply voltage and outputs the first negative reference voltage based on the power supply voltage, and the pressurizing circuit receives the power supply voltage and outputs the first positive reference voltage based on the power supply voltage.
9. The drive circuit of claim 8, wherein the boost module comprises a logic circuit and a voltage boost circuit, the logic circuit being connected to the voltage boost circuit;
The logic circuit receives the second logic voltage, and the voltage boosting circuit receives the second negative reference voltage and the second positive reference voltage, respectively.
10. A display device comprising a display panel, a processor and a drive circuit for the display panel according to any of claims 1-9.
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| KR101852065B1 (en) * | 2011-02-17 | 2018-06-07 | 삼성전자주식회사 | Power supply apparatus for latch-up free charge pump and method there-of |
| KR102151949B1 (en) * | 2013-12-30 | 2020-09-04 | 엘지디스플레이 주식회사 | Display device and driving method thereof |
| KR102122539B1 (en) * | 2013-12-31 | 2020-06-15 | 엘지디스플레이 주식회사 | Power supplying apparatus for liquid crystal display |
| CN208622409U (en) * | 2018-06-27 | 2019-03-19 | 深圳市韦德勋光电科技有限公司 | A kind of high-definition liquid crystal screen logic card |
| CN108922489B (en) * | 2018-08-31 | 2020-09-11 | 重庆惠科金渝光电科技有限公司 | Drive circuit and correction method of internal overcurrent set value thereof |
| CN210805176U (en) * | 2019-12-28 | 2020-06-19 | 深圳市诺威达科技有限公司 | Circuit time sequence identification system |
| KR102662910B1 (en) * | 2020-04-01 | 2024-05-08 | 삼성디스플레이 주식회사 | Power management circuit, method of generating a pixel power supplly voltage, and display device |
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| CN102376249A (en) * | 2010-08-20 | 2012-03-14 | 三星移动显示器株式会社 | Display apparatus and power supplying method performed by display apparatus |
| CN113948051A (en) * | 2021-10-28 | 2022-01-18 | 合肥鑫晟光电科技有限公司 | Display driving circuit, display driving method and display device |
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