CN114578884B

CN114578884B - Linear voltage regulator and system with same

Info

Publication number: CN114578884B
Application number: CN202210074625.7A
Authority: CN
Inventors: 阿诺德·J·德索萨; 希亚姆·索马亚居拉
Original assignee: Ningbo Aola Semiconductor Co ltd
Current assignee: Ningbo Aola Semiconductor Co ltd
Priority date: 2021-05-03
Filing date: 2022-01-21
Publication date: 2024-02-02
Anticipated expiration: 2042-01-21
Also published as: CN114578884A

Abstract

The present application provides a linear voltage regulator including a pass transistor, an error amplifier, a buffer, a load capacitor, and a pair of components coupled in series between an output node of the error amplifier and a regulated output voltage node. The buffer is coupled between the error amplifier and the pass transistor. The buffer is a unity voltage gain buffer having a wide bandwidth and providing a higher current drive for the control terminal of the pass transistor. A first component of the pair of components is provided to reduce loop gain as the output current increases to provide frequency compensation but to reduce the speed of the regulator response to output voltage transients. The second component of the pair of components is used to at least partially counteract operation of the first component during an output voltage transient, thereby enabling the voltage regulator to quickly respond to the transient.

Description

Linear voltage regulator and system with same

Priority statement

The present patent application cites and claims priority to pending provisional indian patent application filed on month 5 3 2021, application number 202141020190, entitled "LDO compensation", and priority to U.S. patent application filed on month 12 2021, application number 17/457,267, both of which are incorporated herein by reference in their entireties.

Technical Field

Embodiments of the present application relate generally to power supply circuits and, more particularly, to load current sensing for frequency compensation in linear regulators.

Background

Voltage regulators are well known in the relevant art as components or devices that produce a stable (regulated) output voltage at an output based on an input voltage received at an input. In general, an effort is made to maintain the output voltage at a fixed level (constant magnitude) regardless of the magnitude of the load current that may be drawn by a load powered by the output voltage or the magnitude of the input voltage.

Linear regulators use a transfer element operating in a linear region, the transfer element being located between an input terminal and an output terminal, and the resistance of the transfer element being adjusted to maintain the output voltage at a desired constant level. A negative feedback loop is typically employed to adjust the resistance of the pass element to maintain the output voltage at a constant level.

Linear regulators are characterized by their ability to respond to transient conditions in which the output voltage fluctuates from a desired constant magnitude. Such fluctuations are typically due to variations in one or more of the input voltage and the load current. The voltage regulator can be said to be in a transient state until the output voltage is corrected back to the desired constant magnitude by the feedback loop. The response of a voltage regulator under such transients may be referred to as a transient response, which is typically quantified in terms of the magnitude of the change from a desired constant magnitude and the time taken to return to the desired constant magnitude of the output voltage. The shorter the time used, the faster the transient response and vice versa.

Frequency compensation is a technique commonly used in linear voltage regulators. This technique is typically used to ensure stability of the output voltage (e.g., to prevent ringing) and also to prevent positive feedback that may occur in a negative feedback loop that is operating properly in a linear voltage regulator. One technique often used in frequency compensation is to reduce the loop gain (open loop gain). However, such a reduction in loop gain reduces the transient response of the linear regulator (i.e., resulting in a longer time for the output voltage to return to a desired constant magnitude), at least in some cases, thereby also substantially reducing other technical parameters such as load and linear regulation.

Disclosure of Invention

Aspects of the present application are directed to achieving fast transient response in linear regulators when employing reduced loop gain for frequency compensation.

Some embodiments of the present application provide a linear voltage regulator, including: a pass transistor having a first current terminal coupled to receive an input voltage and a second current terminal coupled to the regulated output node of the linear regulator and providing a regulated output voltage; an error amplifier coupled to receive a reference voltage from a first input and a feedback voltage from a second input, the feedback voltage derived from the regulated output voltage; the error amplifier is configured to generate an error signal at an output node of the error amplifier that is representative of a difference between the reference voltage and the feedback voltage; a buffer having an input coupled to the output node of the error amplifier and an output coupled to the control terminal of the pass transistor; a first component coupled between the output node of the error amplifier and the regulated output node for frequency compensation of the linear voltage regulator; and a second component coupled between the output node of the error amplifier and the first component, the second component for increasing an impedance provided by a combination of the first component and the second component between the output node of the error amplifier and the regulated output node during a voltage transient at the regulated output node.

In some embodiments, the first component is a first transistor and the second component is a second transistor; wherein: the control end of the first transistor is coupled to the output node of the error amplifier, the second current end of the first transistor is coupled to the regulated output node, the control end of the second transistor is coupled to the output end of the buffer, the first current end of the second transistor is coupled to the output node of the error amplifier, and the second current end of the second transistor is coupled to the first current end of the first transistor.

In some embodiments, the voltage transient is a negative voltage transient, wherein the second component is configured to increase the impedance for a duration of the negative voltage transient.

In some embodiments, the linear regulator further comprises a load capacitance coupled between the regulated output node of the linear regulator and a first constant reference potential, wherein: the combination of the capacitance of the load capacitance and the transconductance of the pass transistor creates a pole in an open loop transfer function of the linear voltage regulator, wherein a frequency position of the pole varies with a magnitude of a load current drawn from the regulated output node, the combination of the first transistor and the second transistor being operable to reduce a gain of the open loop transfer function based on the magnitude of the load current to provide the frequency compensation.

In some embodiments, the pass transistor is an N-type metal oxide semiconductor field effect transistor NMOS.

In some embodiments, wherein each of the error amplifier and the buffer is powered by a charge pump having limited current capability, wherein the voltage transient is a negative voltage transient during which the buffer is used to increase the current output from the buffer to rapidly charge the parasitic gate-source capacitance of the pass transistor to achieve rapid correction of the negative voltage transient.

In some embodiments, wherein the buffer comprises: a first transistor and a second transistor coupled in a current mirror configuration, a first current terminal of the first transistor being coupled to an output node of the error amplifier, a second current terminal of the first transistor being coupled to a control terminal of each of the first transistor and the second transistor, a first current terminal of the second transistor being coupled to a control terminal of the pass transistor, and a second current terminal of the second transistor being coupled to the regulated output node; a first current source having a first terminal coupled to the second current terminal of the first transistor and a second terminal coupled to the first constant reference potential; a second current source having a first terminal coupled to a second constant reference potential and a second terminal coupled to a control terminal of the pass transistor; a third transistor and a fourth transistor coupled as a differential pair, wherein a control terminal of the third transistor is coupled to the output node of the error amplifier, and the fourth transistor is coupled to the control terminal of the pass transistor; a third current source having a first terminal coupled to the second constant reference potential and a second terminal coupled to the first current terminal of each of the third transistor and the fourth transistor; a fifth transistor having a first current terminal and a control terminal, the first current terminal and the control terminal each coupled to a second current terminal of the third transistor, the second current terminal of the fifth transistor coupled to the first constant reference potential; a sixth transistor having a first current terminal and a control terminal, the first current terminal and the control terminal each coupled to a second current terminal of the fourth transistor, the second current terminal of the sixth transistor coupled to the first constant reference potential; a fourth current source having a first terminal coupled to the second current terminal of the fourth transistor and a second terminal coupled to the first constant reference potential; a seventh transistor coupled to the sixth transistor in a current mirror configuration, a control terminal of the seventh transistor coupled to the control terminal of the sixth transistor, a second current terminal of the seventh transistor coupled to the first constant reference potential; an eighth transistor having a second current terminal and a control terminal, the second current terminal and the control terminal each coupled to the first current terminal of the seventh transistor, the first current terminal of the eighth transistor coupled to the second constant reference potential; and a ninth transistor coupled to the eighth transistor in a current mirror configuration, a control terminal of the ninth transistor being coupled to the control terminal of the eighth transistor, a first current terminal of the ninth transistor being coupled to the second constant reference potential, and a second current terminal of the ninth transistor being coupled to the control terminal of the pass transistor.

In some embodiments, wherein the voltage at the output node of the error amplifier is equal to the voltage at the control terminal of the pass transistor without the voltage transient, and the ninth transistor is in an off state, wherein the voltage at the output node of the error amplifier exceeds the voltage at the control terminal of the pass transistor when there is a negative voltage transient, the ninth transistor is in an on state, and the parallel combination of the ninth transistor and the second current source provides increased current drive to the control terminal of the pass transistor.

Some embodiments of the present application further provide a system, including: a power end coupled to the power supply; and a power supply unit coupled to receive power from the power terminal, the power supply unit including a first linear voltage regulator coupled to receive the power and generate a first lower supply voltage; the first linear voltage stabilizer adopts any linear voltage stabilizer.

In some embodiments, the system further comprises: an antenna; a first diplexer coupled to the antenna; and a first transceiver, wherein the first lower supply voltage is used to power noise sensitive blocks in the first transceiver, the first transceiver comprising a transmitter portion and a receiver portion, each coupled to the first diplexer, the first transceiver sending communication signals to a wireless medium via the first diplexer and the antenna, the first transceiver also receiving communication signals from the wireless medium via the first diplexer and the antenna.

In some embodiments, the system is a base transceiver station, BTS, system further comprising: a combiner coupled to the antenna; a plurality of diplexers, each of the plurality of diplexers coupled to the combiner, the plurality of diplexers comprising the first diplexer; and a plurality of transceivers including the first transceiver, each of the plurality of transceivers including a transmitter portion and a receiver portion coupled at one end to a respective one of the plurality of diplexers and at another end to a Base Station Controller (BSC), wherein each of the plurality of transceivers is configured to transmit information signals received from the base station controller into the wireless medium via a respective one of the plurality of diplexers, the combiner, and the antenna, and to forward information signals received from the wireless medium to the base station controller via a respective one of the plurality of diplexers, the combiner, and the antenna; wherein the power supply unit includes: a plurality of DC-DC converters coupled to receive the power from the power terminals and generate respective power supply voltages, the plurality of DC-DC converters including a first DC-DC converter to generate a first power supply voltage, wherein the first power supply voltage is used to power noise-insensitive blocks in the first transceiver, wherein the first linear voltage regulator is coupled to receive the first power supply voltage from the first DC-DC converter to generate the first lower power supply voltage; and a plurality of linear regulators coupled to receive a supply voltage from a respective one of the DC-DC converters and to generate a respective lower supply voltage, wherein the plurality of linear regulators includes the first linear regulator. Wherein a supply voltage generated by one or more of the DC-DC converters is used to power noise insensitive blocks in the plurality of transceivers, and wherein a supply voltage generated by one or more of the linear regulators is used to power noise sensitive blocks in the plurality of transceivers, and wherein at least a second linear regulator of the plurality of linear regulators is implemented similarly to the first linear regulator.

Drawings

Example embodiments of the present application will be described with reference to the accompanying drawings, which are briefly described below.

Fig. 1 shows a detailed schematic of a prior art linear voltage regulator in which clamps are used to reduce loop gain at high load currents to ensure loop stability.

Fig. 2 shows a detailed schematic of a linear voltage regulator for providing fast transient response even when reduced loop gain techniques are employed in an embodiment of the present application.

Fig. 3 shows a circuit diagram of a unity gain buffer for providing an increased buffered switching current in case of transients in the regulated output voltage in an embodiment of the present application.

Fig. 4 is a block diagram of an example device/system incorporating a linear voltage regulator implemented in accordance with aspects of the present application.

In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.

Detailed Description

1. Summary of the invention

One aspect of the present application enables a linear regulator to provide a fast transient response even when a loop gain reduction element is used to provide frequency compensation. In one embodiment, a linear voltage regulator includes a pass transistor, an error amplifier, a buffer, a first component, and a second component. The pass transistor receives an input voltage at a first current terminal. The second current terminal of the pass transistor is connected to the regulated output node of the voltage regulator and provides a regulated output voltage. The error amplifier receives a reference voltage at a first input and a feedback voltage derived from the regulated output voltage at a second input. The error amplifier generates an error signal representing the difference between the reference voltage and the feedback voltage. The buffer has an input connected to the output node of the error amplifier and an output connected to the control terminal of the pass transistor. The first component is connected between the output node of the error amplifier and the regulated output node for frequency compensation. The second component is connected between the output node of the error amplifier and the first component, and is operative to increase an impedance provided by a combination of the first component and the second component between the output node of the error amplifier and the regulated output node when a voltage transient occurs at the regulated output node. Thereby achieving a fast transient response.

Several aspects of the present application are described below with reference to examples for illustration. One skilled in the relevant art will recognize, however, that the application may be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown in detail to avoid obscuring aspects of the application. Furthermore, the described features/aspects may be practiced in various combinations, although only some combinations are described herein for the sake of brevity.

2. Example apparatus

Fig. 1 shows a schematic diagram of an example device that may be modified in accordance with several aspects of the present application. Fig. 1 shows a conventional linear voltage regulator 100. As shown, the conventional linear voltage regulator 100 includes an error amplifier 110, a MOSFET clamp (Mclamp) 120, a buffer 130, a pass transistor (pass element) 140, and a voltage divider network including a resistor 160 and a resistor 170. Further, a load capacitor 150 and a load (current) 151 are also shown. Terminal 199 represents the ground terminal. The pass transistor 140 is an N-type MOSFET (metal oxide semiconductor field effect transistor or NMOS for short), although P-type transistors are also commonly employed. The NMOS 140 receives an Input voltage (Vin) 101 on the drain (D) terminal from a power supply (not shown). The source (S) terminal of the NMOS 140 is the Output terminal of the regulator, on which a regulated Output Voltage (VOUT) 145 is provided. The on-resistance of NMOS 140 is controlled by the voltage applied by error amplifier 110 (via buffer 130) at the gate (G) terminal of NMOS 140 and is adjustable so that VOUT145 is maintained at a desired level despite variations in load current 151 and/or VIN. VCP 102 represents a voltage generated inside the voltage regulator by a charge pump (not shown).

The voltage divider network formed by resistors 160 and 170 receives the output voltage VOUT and provides a portion of VOUT to the negative terminal (-) of error amplifier 110 as a feedback Voltage (VFB) 171.

Error amplifier 110 receives a reference Voltage (VREF) 111 at the positive terminal (+) that may be generated within voltage regulator 100 in a known manner. Error amplifier 110 generates an amplified value of the difference between VREF and VFB on path 113 to regulate the gate voltage of NMOS 150. Error amplifier 110 is powered by a power supply VCP (102) generated by a charge pump within voltage regulator 100, but not shown. If the output 113 of the error amplifier 210 is directly connected to the gate of the pass transistor 140, the node 113 will require charging and discharging of the relatively high parasitic gate-source capacitance of the pass transistor 140. This in turn requires a power supply that can provide a large current to the error amplifier 110. However, a charge pump that produces VCP (102) may not be able to provide such large currents for at least a long period of time. A current buffer (buffer 130) is used between the output of the error amplifier 110 and the gate of the pass transistor 140 to decouple the node 113 from the gate-source capacitance of the pass transistor 140.

Buffer 130 is powered by VCP102 and is a high bandwidth, unity voltage gain current buffer. Buffer 130 provides the same voltage on node 134 as on node 113. In particular, buffer 130 is intended to provide voltage 134 with a higher source or sink current to/from node 134. Accordingly, buffer 130 is able to quickly charge and discharge parasitic capacitance between the gate and source terminals of pass transistor 140 and change the gate voltage of pass transistor 140 faster than otherwise to allow for quick adjustment of the on-resistance of the pass transistor to bring VOUT back to its desired magnitude in the event of a load current change. Thus, the feedback loop formed by the voltage divider and the error amplifier quickly corrects for variations (transients) in the regulated output voltage VOUT caused by variations in the load current 151.

As is well known in the relevant art, frequency compensation is commonly used in negative feedback systems. As with other negative feedback systems, in linear regulators such as regulator 100, frequency compensation is employed to prevent the unexpected occurrence of positive feedback, which in turn may cause the regulated output voltage VOUT to oscillate or vary in any manner from a constant level that it should maintain. In addition to preventing positive feedback, frequency compensation may be employed in order to minimize or prevent overshoot and ringing of VOUT in response to disturbances (e.g., step changes in load current and/or VIN).

Frequency compensation may be achieved by modifying the gain and/or phase characteristics of the open loop transfer function of the voltage regulator. In short, in the open loop transfer function of the voltage regulator, sufficient gain and/or phase margin is ensured to prevent positive feedback from occurring and minimize ringing of VOUT in response to step disturbances. The open loop transfer function refers to the ratio of the feedback signal and the error signal, i.e. it is the product of the transfer functions of the circuit/block that forms the path from the output 131 of the error amplifier 110 to the input 171 of the error amplifier 110 that receives the feedback signal VFB (171 in fig. 1).

In order to provide good load regulation, the error amplifier 110 is designed to have a high gain. The voltage regulator 100 has two poles, one at the output node 113 of the error amplifier 110 and the other (the load pole) at the regulated output node VOUT. Since the Load capacitor (Cload) 150 is typically quite large (40 uF), both poles are at very low frequency under no-Load conditions and based on Cload, the Load pole can dominate. As load current 151 increases, the transconductance of pass transistor 140 increases and the load pole moves to a higher frequency based on the magnitude of load current 151. Therefore, the unit gain bandwidth (Unity gain bandwidth, abbreviated as UGB) of the voltage regulator 100 also increases, resulting in a decrease in the phase margin. Therefore, to ensure stability, at higher load currents, the loop gain (open loop gain) needs to be reduced in order to limit the UGB increase to acceptable frequencies. The decrease in loop gain typically reduces load and line regulation.

A technique for reducing loop gain is employed in the voltage regulator 100 according to which the drain and gate of the transistor (Mclamp 120) are shorted and placed between the node 113 and the node 145, as shown in fig. 1. That is, the drain and gate of transistor 120 are connected to node 113 and the source of transistor 120 is connected to VOUT 145. At zero load current or low load current, the voltage on node 113 is relatively small and thus Mclamp120 is turned off. Thus, the loop has a high gain at zero load current or low load current. However, as the load current increases, the voltage on node 113 increases and Mclamp120 turns on, the on-resistance of transistor 120 (1/Gm, where Gm represents the transconductance of transistor 120) decreases exponentially with respect to voltage 113. Accordingly, mclamp120 presents an impedance between node 113 and node 145 that decreases as the load current increases, thereby correspondingly decreasing the loop gain as the load current increases, thereby ensuring loop stability.

However, one disadvantage of using Mclamp 120 is: the presence of Mclamp 120 reduces the rate at which the voltage output 113 of error amplifier 110 rises (increases) with increasing load current to correct the corresponding drop in VOUT. In general, the greater the load current (with respect to time) increase, the longer the voltage 113 increases to be sufficient to fully correct for the drop in the output voltage VOUT. Thus, the transient response of the voltage regulator 100 slows down and load and line regulation specifications may generally decrease.

Aspects of the present application aim to overcome at least the above-mentioned drawbacks, achieving a fast transient response while still employing gain limitations using Mclamp 120 (or similar impedance).

3. Achieving fast transient response

Fig. 2 is a detailed schematic diagram illustrating a linear voltage regulator according to aspects of the present application. Fig. 2 shows a linear voltage regulator 200, the linear voltage regulator 200 comprising an error amplifier 210, a MOSFET clamp (Mclamp) 220, a buffer 230, a pass transistor (pass element) 240, a voltage divider network comprising a resistor 260 and a resistor 270, and a transistor 280. Further, a load capacitance 250 and a load (current) 251 are also shown. End 299 represents the ground. The pass transistor 240 is an N-type MOSFET (metal oxide semiconductor field effect transistor or NMOS for short), although P-type transistors may also be generally employed. In one embodiment, the voltage regulator 200 is implemented as a Low-dropout voltage regulator (LDO for short, low-dropout regulator).

Error amplifier 210, MOSFET clamp (Mclamp) 220, buffer 230, pass transistor (pass element) 240, voltage divider network including resistor 260 and resistor 270, load capacitor (Cload) 250 and Load 251 function similarly to the implementation of error amplifier 110, MOSFET clamp (Mclamp) 120, buffer 130, pass transistor (pass element) 140, voltage divider network including resistor 160 and resistor 170, load capacitor 150 and Load 151. For brevity, the description or operation thereof will not be repeated here.

The NMOS 240 receives an Input voltage 201 (Vin) from a power supply (not shown) on a drain (D). The source of the NMOS 240 is the Output of the regulator 200, at which a regulated Output voltage Vout (Vout) 245 is provided. The on-resistance of NMOS 240 is controlled by the voltage applied by error amplifier 210 (via buffer 230) on the gate (G) of NMOS 240 and is adjustable so that Vout245 is maintained at a desired level despite variations in load current 251 and/or Vin. Vcp 202 represents the voltage generated inside voltage regulator 200 by a charge pump (not shown). The operation of the voltage regulator 200 is similar to that of the prior art voltage regulator 100, except for the differences described below.

According to one aspect of the present application, another transistor 280 is connected in series with Mclamp 220. The source of transistor 280 is connected to the drain of transistor 220, the drain of transistor 280 is connected to node 213, and the gate of transistor 280 is connected to output 234 of buffer 230. The source of transistor 220 is connected to Vout 245 and the gate of transistor 220 is connected to node 213.

In operation, in the event of a negative transient in the output voltage Vout, the voltage on node 234 is relatively lower than the voltage on node 213 because the gate-source capacitance of pass transistor 240 requires time to charge. Thus, the transistor 280 is off or has a high on-resistance. Accordingly, the transistor 220 is also off or has a high on-resistance. Thus, the effective impedance between node 213 and node 245 (Vout) is very high, voltage 213 rises freely, and operates with buffer 230 to quickly restore Vout to the desired constant magnitude. Once steady state is reached, voltage 234 is equal to voltage 213 (buffer 230 is a unity voltage gain buffer) and transistor 280 is fully on. Thus, the series combination of transistors 220 and 280 returns to a low impedance state, the specific magnitude of the impedance being dependent on the load current 251. Thus, during a negative transient in Vout, the operation of transistor 280 serves to at least partially cancel the operation of transistor 220, thereby enabling the voltage regulator to quickly respond to the transient.

In case of a positive transient of the output voltage Vout, the voltage 213 needs to be reduced. However, this is not problematic because both transistor 220 and transistor 280 are diode-connected configurations, and voltage 213 may decrease as the current through both transistors decreases. Thus, degradation of the load and line conditioning parameters is also minimized.

The components 220 and 280 are shown as being implemented using transistors, but the components 220 and 280 may also be implemented generally by circuits or components that provide an impedance that varies as the load current 251 varies. Thus, transistor 220 may be generally considered a first component connected between output node 213 of error amplifier 210 and regulated output node 245 for frequency compensation of linear regulator 200. Transistor 280 may be generally considered a second component connected between output node 213 of error amplifier 210 and regulated output node 245, and when a voltage transient occurs at the regulated output node, transistor 280 is operated to increase the impedance provided by the combination of the first component and the second component between output node 213 of error amplifier 210 and regulated output node 245.

The operation of buffer 230 and its implementation in an embodiment are described next.

4. Buffer device

Buffer 230 is powered by Vcp (202), is configured as a unity voltage gain current buffer, and operates to provide a higher drive current to drive the gate of pass transistor 240. Since the charge pump that generates Vcp is only capable of providing low current (except for short durations when current can be increased), buffer 230 is designed to include an amplifier 235, which amplifier 235 operates during negative voltage transients to increase the source current 236 into node 234 to rapidly pull node 234 to higher voltages as needed. In short, in the event of a negative voltage transient in Vout (i.e., vout decreases from its steady state or present value), voltage 213 is greater than voltage 234, and amplifier 235 operates to increase source current 236 into node 234 until Vout is corrected, so voltage 213 and voltage 234 become equal. In the event of a positive voltage transient in Vout, transistor 233 provides a low impedance path to quickly pull down node 234 to correct Vout.

Fig. 3 is a circuit diagram of buffer 230 in an embodiment of the present application. The parallel combination of transistors 340 and 350, current sink (current sink) 370, and transistor 345 and current source 375 operate to provide higher current supply and current sinking capability to/from node 234 while providing high bandwidth unity voltage gain from node 213 to node 234. Transistor 340, transistor 350, and current well 370 correspond to transistor 232, transistor 233, and current well 231, respectively, of fig. 2. The remaining components of the buffer 230 of fig. 3 form the amplifier 235 and the controllable current source 236 of fig. 2. The parallel combination of transistor 345 and current source 375 corresponds to controllable current source 236 of fig. 2. Current source 360 provides a current equal to 2 x ib. Current source 365 provides a current equal to IB. The transistor size ratio of transistors 330 and 345 is 1:N. The particular values of IB and N are selected according to particular design requirements. The transistor size ratio of transistors 325 and 335 is 1:1. Transistors 310 and 320 form a differential pair.

In operation, when the voltages at nodes 213 and 234 are equal, a current of magnitude IB flows through transistors 310 and 315, and current I1 flowing through transistor 325 is equal to zero. Thus, no current flows through transistors 335, 330, and 345, and in the absence of a negative transient at Vout, the buffer source current is the current provided by current source 375. In the event of a negative transient at Vout, voltage 213 is greater than voltage 234 due to the relatively fast response of error amplifier 210 to the transients and the gate-source capacitance of pass transistor 240, and all of the current 2 x ib provided by current source 360 flows through transistor 320. Thus, the current I1 through transistor 325 is approximately equal to IB. Due to the current mirror configuration of transistors 325 and 335 and 330 and 345, current IB flows through transistors 335 and 330 and current N x IB flows through transistor 345. Thus, the source current into node 234 is equal to the sum of N x IB and the current provided by current source 375. Thus, buffer 230 provides a higher current drive to drive node 234 only during negative transients at Vout. In the event of a positive transient at Vout, transistor 350 provides a low impedance path for node 234 to discharge rapidly.

The linear voltage regulator 200 implemented as described above may be incorporated into a larger device or system as briefly described below.

5. Apparatus/system

Fig. 4 is a block diagram showing implementation details of a system incorporating linear voltage regulator 200 described in detail above in an embodiment of the present application. The system of fig. 4 may be deployed in a base transceiver station (Base transceiver station, simply BTS) of a cellular telephone system (eNodeB in LTE-long term evolution) and is referred to herein as BTS system 400. In general, the BTS system 400 facilitates wireless communication between User Equipment (UE), which may be a mobile station (e.g., a handset) or a fixed User equipment (e.g., a computer with an Internet connection). The BTS system 400 may be implemented according to technologies and standards such as global system for mobile communications (Global system for mobile communications, GSM for short), code division multiple access (Code division multiple access, CDMA for short), third generation mobile communication technology (3 rd generation, 3G for short), fourth generation mobile communication technology (4 th generation, 4G for short), long term evolution, fifth generation mobile communication technology (5 th generation, 5G for short), etc. BTS system 400 is shown to include transceivers 410A through 410N, diplexers 420A through 420N, combiner 430, antenna 440, battery pack 450, and power supply 460. The particular components/blocks of the BTS system 400 are shown by way of illustration only. However, as is well known in the relevant art, typically the BTS system 400 may include many more components/blocks, such as temperature sensors, maintenance and configuration blocks, and the like.

Each of the transceivers 410A-410N operates to transmit and receive communication signals to/from wireless user equipment via a corresponding diplexer 420A-420N, combiner 430, and antenna 440. Each transceiver includes a transmitter portion and a receiver portion. Accordingly, the transceiver 410A is shown to include a transmitter section including a transmit baseband block 411, a transmit Radio Frequency (RF) block 412, and a power amplifier 413, and a receiver section including a Low-noise amplifier (LNA) 416, a receive RF block 415, and a receive baseband block 414.

The transmit baseband block 411 receives information signals (e.g., representing voice, data) from a base station controller (Base station controller, simply BSC) via corresponding paths shown in bus 499 (which in turn receives communication signals from another user equipment (wireless or fixed) in the network downstream of the BSC), processes the signals according to corresponding techniques and protocols to perform modulation, channel coding, and other operations, and forwards the processed signals to the transmit RF block 412. The transmit RF block 412 may perform operations such as up-conversion to RF and forward the RF signal to the power amplifier 413. The power amplifier 413 amplifies the received RF signal and transmits the power amplified signal to a corresponding wireless user equipment through the duplexer 420A, the combiner 430, and the antenna 440.

LNA 416 receives RF signals from the wireless user device via duplexer 420A, combiner 430, and antenna 440, amplifies the RF signals, and forwards the amplified RF signals to receive RF block 415. The receive RF block 415 down-converts the RF signal to baseband frequency and forwards the baseband signal to the receive baseband block 414. The receive baseband block 414 may perform operations such as demodulation, error correction, etc. on the baseband signals to obtain information signals (e.g., data, voice) and forward the information signals to the BSC via corresponding paths in the bus 499.

Clock 417 generates one or more clocks required to enable operation of the digital units in transceiver 410. For example, transmit baseband block 411 and receive baseband block 414 may include one or more processors within them that require a clock to enable their operation.

The operation of the transmitter, receiver, and clock of the other transceiver of fig. 4 is similar to that described above with respect to transceiver 410A and includes corresponding transmitter and receiver blocks.

Each of the diplexers 420A-420N is capable of sending and receiving respective send and receive signals (i.e., bi-directional (duplex) communications) on a single path between the respective diplexer and combiner 430. Each of the diplexers 420A-420N may be implemented with two bandpass filters connected in parallel, with one filter providing a path between the respective transmitter and combiner 430 and the other filter providing a path between the combiner 430 and the respective receiver.

Combiner 430 combines signals from/to transceivers 410A through 410N to enable all signals to be transmitted and received using a single antenna 440.

The antenna 440 operates to receive information-bearing wireless signals from the wireless medium between the transceiver and the wireless user device and to transmit information-bearing wireless signals to the wireless medium.

The battery pack 450 houses batteries to provide power for the operation of the blocks/units in the BTS system 400.

The power supply 460 receives power (e.g., 12 volts) from the battery pack 450 and includes a plurality of DC-DC converters 461A through 461M, and a plurality of linear regulators (e.g., implemented as LDOs) 462A through 462L. The DC-DC converters 461A-461M generate various voltages (each DC-DC converter generates a corresponding voltage, e.g., 0.7V, 1.2V, 2.0V, 3.6V, etc.) for powering one or more blocks/components of the BTS system 400 described above. In particular, the voltage generated by the DC-DC converter may be used to power blocks and components of transceivers 410A-410N that are less susceptible to noise (e.g., transmit and receive baseband blocks). Thus, the supply voltage 491C is shown as being generated by the DC-DC converter 461A and provided to the (transmit and receive baseband blocks) of the transceiver 410. For clarity and conciseness, only one power connection directly from the DC-DC converter is shown in fig. 4. However, there are many more such power connections.

Each of the LDOs 462A-462L is connected to receive the output voltage of a corresponding DC-DC converter 461A-461M and to generate a corresponding lower voltage according to the needs of some components/blocks of the transceiver. The voltage generated by the LDO is used to power noise sensitive blocks and components in the transceivers 410A-410N, such as a transmit RF block (e.g., 412), a receive RF block (e.g., 415), an LNA (e.g., 416), and a clock (e.g., 417) included in the transceiver. For clarity and conciseness, only two power connections 491A and 491B (from LDO 462A and LDO 462L, respectively) are shown in FIG. 4. However, there are more power connections from the LDO to the corresponding blocks in the transceiver. LDOs may have better load and line regulation than DC-DC converters, and thus may provide cleaner supply voltages, while being lower in noise, as required by the noise sensitive blocks described above.

One or more of LDOs 462A-462-L are implemented as linear regulators 200 as described in detail above.

It is noted here that the linear voltage regulator 200 may also be used in other systems, such as separate transmitters and receivers, mobile phones, etc.

6. Conclusion(s)

Reference throughout this specification to "one embodiment" and "an embodiment" or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, appearances of the phrases "in one embodiment (" in one embodiment "and" in an embodiment ")" and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

Although in the illustrations of fig. 1, 2, 3, and 4, the ends/nodes are shown as having direct connections to (i.e., "connected to") various other ends, it should be understood that additional components (as appropriate for the particular environment) may also be present in the path, and thus the connections may be considered "electrically coupled" to the same connection ends.

It should be understood that the specific types of transistors (e.g., NMOS, PMOS, etc.) mentioned above are for illustration only. However, alternative embodiments using different configurations and transistors will be apparent to those skilled in the relevant arts from reading the disclosure provided herein. For example, the NMOS transistor may be replaced with a PMOS (P-type metal oxide semiconductor) transistor while exchanging connections to power and ground.

Therefore, in this application, the power supply terminal and the ground terminal are referred to as constant reference potential, the source (emitter) and the drain (collector) of the transistor (providing a current path when on, and an open path when off) are referred to as current terminals, and the gate (base) is referred to as a control terminal.

While various embodiments of the present application have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the present application should not be limited by any of the above-described embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A linear voltage regulator, comprising:

a pass transistor having a first current terminal coupled to receive an input voltage and a second current terminal coupled to the regulated output node of the linear regulator and providing a regulated output voltage;

an error amplifier coupled to receive a reference voltage from a first input and a feedback voltage from a second input, the feedback voltage derived from the regulated output voltage; the error amplifier is configured to generate an error signal at an output node of the error amplifier that is representative of a difference between the reference voltage and the feedback voltage;

a buffer having an input coupled to the output node of the error amplifier and an output coupled to the control terminal of the pass transistor;

a first component coupled between the output node of the error amplifier and the regulated output node for frequency compensation of the linear voltage regulator; and

a second component coupled between the output node of the error amplifier and the first component, the second component for increasing an impedance provided by a combination of the first component and the second component between the output node of the error amplifier and the regulated output node during a voltage transient at the regulated output node.

2. The linear voltage regulator of claim 1, wherein the first component is a first transistor and the second component is a second transistor; wherein:

the control terminal of the first transistor is coupled to the output node of the error amplifier, the second current terminal of the first transistor is coupled to the regulated output node, and

the control end of the second transistor is coupled to the output end of the buffer, the first current end of the second transistor is coupled to the output node of the error amplifier, and the second current end of the second transistor is coupled to the first current end of the first transistor.

3. The linear voltage regulator of claim 2, wherein the voltage transient is a negative voltage transient, wherein the second component is to increase the impedance for a duration of the negative voltage transient.

4. The linear regulator of claim 3, further comprising a load capacitance coupled between the regulated output node of the linear regulator and a first constant reference potential, wherein:

the combination of the capacitance of the load capacitor and the transconductance of the pass transistor creates a pole in an open loop transfer function of the linear voltage regulator, wherein the frequency position of the pole varies with the magnitude of the load current drawn from the regulated output node,

The combination of the first transistor and the second transistor is used to reduce the gain of the open loop transfer function based on the magnitude of the load current to provide the frequency compensation.

5. The linear voltage regulator according to claim 4, wherein the pass transistor is an N-type metal oxide semiconductor field effect transistor NMOS.

6. The linear voltage regulator of claim 1, wherein each of the error amplifier and the buffer is powered by a charge pump having limited current capability,

wherein the voltage transient is a negative voltage transient during which the snubber is used to increase the current output from the snubber to rapidly charge the parasitic gate-source capacitance of the pass transistor to achieve rapid correction of the negative voltage transient.

7. The linear voltage regulator of claim 6, wherein the buffer comprises:

a first transistor and a second transistor coupled in a current mirror configuration, a first current terminal of the first transistor being coupled to an output node of the error amplifier, a second current terminal of the first transistor being coupled to a control terminal of each of the first transistor and the second transistor, a first current terminal of the second transistor being coupled to a control terminal of the pass transistor, and a second current terminal of the second transistor being coupled to the regulated output node;

A first current source having a first terminal coupled to the second current terminal of the first transistor and a second terminal coupled to a first constant reference potential;

a second current source having a first terminal coupled to a second constant reference potential and a second terminal coupled to a control terminal of the pass transistor;

a third transistor and a fourth transistor coupled as a differential pair, wherein a control terminal of the third transistor is coupled to the output node of the error amplifier, and the fourth transistor is coupled to the control terminal of the pass transistor;

a third current source having a first terminal coupled to the second constant reference potential and a second terminal coupled to the first current terminal of each of the third transistor and the fourth transistor;

a fifth transistor having a first current terminal and a control terminal, the first current terminal and the control terminal each coupled to a second current terminal of the third transistor, the second current terminal of the fifth transistor coupled to the first constant reference potential;

a sixth transistor having a first current terminal and a control terminal, the first current terminal and the control terminal each coupled to a second current terminal of the fourth transistor, the second current terminal of the sixth transistor coupled to the first constant reference potential;

A fourth current source having a first terminal coupled to the second current terminal of the fourth transistor and a second terminal coupled to the first constant reference potential;

a seventh transistor coupled to the sixth transistor in a current mirror configuration, a control terminal of the seventh transistor coupled to the control terminal of the sixth transistor, a second current terminal of the seventh transistor coupled to the first constant reference potential;

an eighth transistor having a second current terminal and a control terminal, the second current terminal and the control terminal each coupled to the first current terminal of the seventh transistor, the first current terminal of the eighth transistor coupled to the second constant reference potential; and

a ninth transistor coupled to the eighth transistor in a current mirror configuration, a control terminal of the ninth transistor coupled to the control terminal of the eighth transistor, a first current terminal of the ninth transistor coupled to the second constant reference potential, and a second current terminal of the ninth transistor coupled to the control terminal of the pass transistor.

8. The linear voltage regulator of claim 7, wherein the voltage at the output node of the error amplifier is equal to the voltage at the control terminal of the pass transistor without the voltage transient, and the ninth transistor is in an off state,

Wherein when there is a negative voltage transient, the voltage at the output node of the error amplifier exceeds the voltage at the control terminal of the pass transistor, the ninth transistor is in a conductive state, and the parallel combination of the ninth transistor and the second current source provides increased current drive to the control terminal of the pass transistor.

9. A system, comprising:

a power end coupled to the power supply; and

a power supply unit coupled to receive power from the power terminal, the power supply unit including a first linear voltage regulator coupled to receive the power and generate a first lower supply voltage,

wherein the first linear voltage regulator comprises:

10. The system of claim 9, further comprising:

an antenna;

a first diplexer coupled to the antenna; and

a first transceiver, wherein the first lower supply voltage is used to power noise sensitive blocks in the first transceiver,

the first transceiver includes a transmitter portion and a receiver portion, each coupled to the first diplexer, the first transceiver transmitting communication signals to a wireless medium via the first diplexer and the antenna, the first transceiver also receiving communication signals from the wireless medium via the first diplexer and the antenna.

11. The system of claim 10, wherein the system is a base transceiver station, BTS, system further comprising:

a combiner coupled to the antenna;

a plurality of diplexers, each of the plurality of diplexers coupled to the combiner, the plurality of diplexers comprising the first diplexer; and

a plurality of transceivers including the first transceiver, each of the plurality of transceivers including a transmitter portion and a receiver portion coupled at one end to a respective one of the plurality of diplexers and at the other end to a base station controller BSC, wherein each of the plurality of transceivers is configured to transmit information signals received from the base station controller into the wireless medium via a respective one of the plurality of diplexers, the combiner and the antenna, and to forward information signals received from the wireless medium to the base station controller via a respective one of the plurality of diplexers, the combiner and the antenna;

wherein the power supply unit includes:

a plurality of DC-DC converters coupled to receive the power from the power terminals and generate respective power supply voltages, the plurality of DC-DC converters including a first DC-DC converter to generate a first power supply voltage, wherein the first power supply voltage is used to power noise-insensitive blocks in the first transceiver, wherein the first linear voltage regulator is coupled to receive the first power supply voltage from the first DC-DC converter to generate the first lower power supply voltage; and

A plurality of linear regulators coupled to receive a supply voltage from a respective one of the DC-DC converters and to generate a respective lower supply voltage, wherein the plurality of linear regulators includes the first linear regulator,

wherein a supply voltage generated by one or more of the DC-DC converters is used to power noise-insensitive blocks in the plurality of transceivers, and wherein a supply voltage generated by one or more of the linear regulators is used to power noise-sensitive blocks in the plurality of transceivers, an

Wherein at least a second linear voltage regulator of the plurality of linear voltage regulators is implemented similarly to the first linear voltage regulator.

12. The system of claim 11, wherein the first component is a first transistor and the second component is a second transistor, wherein:

13. The system of claim 12, wherein the voltage transient is a negative voltage transient, wherein the second component is to increase the impedance for a duration of the negative voltage transient.

14. The system of claim 13, wherein the linear regulator further comprises a load capacitance coupled between the regulated output node of the linear regulator and a first constant reference potential, wherein:

15. The system of claim 14, wherein the pass transistor is an N-type metal oxide semiconductor field effect transistor NMOS.

16. The system of claim 15, wherein each of the error amplifier and the buffer is powered by a charge pump having limited current capability,

17. The system of claim 16, wherein the buffer comprises:

a first current source having a first terminal coupled to the second current terminal of the first transistor and a second terminal coupled to the first constant reference potential;

18. The system of claim 17, wherein without the voltage transient, the voltage at the output node of the error amplifier is equal to the voltage at the control terminal of the pass transistor, and the ninth transistor is in an off state,