CN114578884A - Linear regulator and system having the same - Google Patents
Linear regulator and system having the same Download PDFInfo
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- CN114578884A CN114578884A CN202210074625.7A CN202210074625A CN114578884A CN 114578884 A CN114578884 A CN 114578884A CN 202210074625 A CN202210074625 A CN 202210074625A CN 114578884 A CN114578884 A CN 114578884A
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- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
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Abstract
A linear regulator includes a pass transistor, an error amplifier, a buffer, a load capacitor, and a pair of components coupled in series between an output node of the error amplifier and a regulated output voltage node. A buffer is coupled between the error amplifier and the pass transistor. The buffer is a unity voltage gain buffer that has a wide bandwidth and provides higher current drive to the control terminal of the pass transistor. A first component of a pair of components is provided to reduce the loop gain as the output current increases, thereby providing frequency compensation, but reducing the speed of response of the voltage regulator to output voltage transients. The second component of the pair of components is configured to at least partially cancel operation of the first component during the output voltage transient, thereby enabling the voltage regulator to respond quickly to the transient.
Description
Priority declaration
This patent application cites and claims priority from pending provisional indian patent application No. 202141020190 entitled "LDO compensation" filed on 3.5.2021 and U.S. patent application No. 17/457,267 filed on 2.12.2021, both of which are incorporated herein by reference in their entirety.
Technical Field
Embodiments of the present application relate generally to power supply circuits and, more particularly, to load current sensing for frequency compensation in linear regulators.
Background
As is well known in the related art, a voltage regulator refers to a component or device that generates a stable (regulated) output voltage at an output based on an input voltage received at an input. In general, the output voltage is strived to be maintained at a fixed level (constant magnitude) regardless of the magnitude of the load current or the magnitude of the input voltage that a load powered by the output voltage may draw.
Linear regulators use a pass element operating in the linear region, which is located between an input and an output, and adjust the resistance of the pass element to maintain the output voltage at a desired constant level. A negative feedback loop is typically employed to adjust the resistance of the pass element to maintain the output voltage at a constant level.
A characteristic of linear regulators is that they are able to respond to transient conditions in which the output voltage fluctuates from a desired constant magnitude. Such fluctuations are typically due to variations in one or more of the input voltage and the load current. It can be said that the voltage regulator is in a transient state until the output voltage is corrected back to the desired constant magnitude by the feedback loop. The response of a voltage regulator in such a transient state may be referred to as a transient response, which is typically quantified in terms of the amount of change from a desired constant magnitude and the time it takes to return to the desired constant magnitude of the output voltage. The shorter the time taken, the faster the transient response and vice versa.
Frequency compensation is a commonly used technique in linear regulators. This technique is commonly used to ensure the stability of the output voltage (e.g., to prevent ringing) and also to prevent positive feedback that may occur in the negative feedback loop of normal operation in a linear regulator. One technique often used in frequency compensation is to reduce the loop gain (open loop gain). However, at least in some cases, this reduced loop gain reduces the transient response of the linear regulator (i.e., results in the output voltage returning to a desired constant magnitude for a longer period of time), thereby also substantially reducing other technical parameters, such as load and linearity trim rates.
Disclosure of Invention
Aspects of the present application are directed to achieving fast transient response in a linear regulator when frequency compensation is performed with reduced loop gain.
Some embodiments of the present application provide a linear regulator, including: a pass transistor having a first current terminal coupled to receive an input voltage and a second current terminal coupled to a regulated output node of the linear regulator and providing a regulated output voltage; an error amplifier coupled to receive a reference voltage from a first input and a feedback voltage from a second input, the feedback voltage being derived from the regulated output voltage; the error amplifier is configured to generate an error signal at an output node of the error amplifier indicative of a difference between the reference voltage and the feedback voltage; a buffer having an input coupled to the output node of the error amplifier and an output coupled to the control terminal of the pass transistor; a first component coupled between an output node of the error amplifier and the regulated output node for frequency compensation of the linear regulator; and a second component coupled between the output node of the error amplifier and the first component, the second component for increasing an impedance provided by a combination of the first and second components between the output node of the error amplifier and the regulated output node during a voltage transient at the regulated output node.
In some embodiments, the first component is a first transistor and the second component is a second transistor; wherein: the control end of the first transistor is coupled to the output node of the error amplifier, the second current end of the first transistor is coupled to the regulated output node, the control end of the second transistor is coupled to the output end of the buffer, the first current end of the second transistor is coupled to the output node of the error amplifier, and the second current end of the second transistor is coupled to the first current end of the first transistor.
In some embodiments, the voltage transient is a negative voltage transient, wherein the second component is to increase the impedance for the duration of the negative voltage transient.
In some embodiments, the linear regulator further comprises a load capacitor coupled between the regulated output node of the linear regulator and a first constant reference potential, wherein: a combination of a capacitance of the load capacitance and a transconductance of the pass transistor generates a pole in an open loop transfer function of the linear regulator, wherein a frequency location of the pole varies with a magnitude of a load current drawn from the regulated output node, the combination of the first transistor and the second transistor to reduce a gain of the open loop transfer function based on the magnitude of the load current to provide the frequency compensation.
In some embodiments, the pass transistor is an N-type metal oxide semiconductor field effect transistor, NMOS.
In some embodiments, wherein each of the error amplifier and the buffer is powered by a charge pump with limited current capability, wherein the voltage transient is a negative voltage transient during which the buffer is used to increase the current output from the buffer to rapidly charge the parasitic gate-source capacitance of the pass transistor to enable rapid correction of the negative voltage transient.
In some embodiments, wherein the buffer comprises: a first transistor and a second transistor coupled in a current mirror configuration, a first current terminal of the first transistor being coupled to an output node of the error amplifier, a second current terminal of the first transistor being coupled to a control terminal of each of the first and second transistors, a first current terminal of the second transistor being coupled to a control terminal of the pass transistor, and a second current terminal of the second transistor being coupled to the regulated output node; a first current source having a first terminal coupled to the second current terminal of the first transistor and a second terminal coupled to the first constant reference potential; a second current source having a first terminal coupled to a second constant reference potential and a second terminal coupled to the control terminal of the pass transistor; a third transistor and a fourth transistor coupled as a differential pair, wherein a control terminal of the third transistor is coupled to an output node of the error amplifier, and the fourth transistor is coupled to a control terminal of the pass transistor; a third current source having a first terminal coupled to the second constant reference potential and a second terminal coupled to a first current terminal of each of the third and fourth transistors; a fifth transistor having a first current terminal and a control terminal, the first current terminal and the control terminal each coupled to a second current terminal of the third transistor, a second current terminal of the fifth transistor coupled to the first constant reference potential; a sixth transistor having a first current terminal and a control terminal, the first current terminal and the control terminal each coupled to a second current terminal of the fourth transistor, a second current terminal of the sixth transistor coupled to the first constant reference potential; a fourth current source having a first terminal coupled to the second current terminal of the fourth transistor and a second terminal coupled to the first constant reference potential; a seventh transistor coupled to the sixth transistor in a current mirror configuration, a control terminal of the seventh transistor being coupled to a control terminal of the sixth transistor, a second current terminal of the seventh transistor being coupled to the first constant reference potential; an eighth transistor having a second current terminal and a control terminal, the second current terminal and the control terminal each coupled to the first current terminal of the seventh transistor, the first current terminal of the eighth transistor coupled to the second constant reference potential; and a ninth transistor coupled to the eighth transistor in a current mirror configuration, a control terminal of the ninth transistor being coupled to a control terminal of the eighth transistor, a first current terminal of the ninth transistor being coupled to the second constant reference potential, and a second current terminal of the ninth transistor being coupled to a control terminal of the pass transistor.
In some embodiments, wherein in the absence of the voltage transient, the voltage at the output node of the error amplifier is equal to the voltage at the control terminal of the pass transistor and the ninth transistor is in an off state, wherein when there is a negative voltage transient, the voltage at the output node of the error amplifier exceeds the voltage at the control terminal of the pass transistor, the ninth transistor is in an on state, and the parallel combination of the ninth transistor and the second current source provides increased current drive to the control terminal of the pass transistor.
Some embodiments of the present application further provide a system, including: a power terminal coupled to a power source; and a power supply unit coupled to receive power from the power terminal, the power supply unit including a first linear regulator coupled to receive the power and generate a first lower supply voltage; the first linear regulator adopts any linear regulator.
In some embodiments, the system further comprises: an antenna; a first duplexer coupled to the antenna; and a first transceiver, wherein the first lower supply voltage is used to power a noise-sensitive block in the first transceiver, the first transceiver comprising a transmitter portion and a receiver portion, the transmitter portion and the receiver portion each coupled to the first duplexer, the first transceiver to transmit communication signals to a wireless medium via the first duplexer and the antenna, the first transceiver to also receive communication signals from the wireless medium via the first duplexer and the antenna.
In some embodiments, the system is a base transceiver station, BTS, system, the BTS system further comprising: a combiner coupled to the antennas; a plurality of duplexers, each of the plurality of duplexers coupled to the combiner, the plurality of duplexers including the first duplexer; and a plurality of transceivers, including the first transceiver, each of the plurality of transceivers including a transmitter portion and a receiver portion, coupled at one end to a respective one of the plurality of duplexers and coupled at another end to a Base Station Controller (BSC), wherein each of the plurality of transceivers is to transmit an information signal received from the base station controller into the wireless medium via a respective one of the plurality of duplexers, the combiner, and the antenna, and to forward an information signal received from the wireless medium to the base station controller via a respective one of the plurality of duplexers, the combiner, and the antenna; wherein the power supply unit includes: a plurality of DC-DC converters coupled to receive the power from the power terminal and generate respective supply voltages, the plurality of DC-DC converters including a first DC-DC converter to generate a first supply voltage, wherein the first supply voltage is used to power noise-insensitive blocks in the first transceiver, wherein the first linear regulator is coupled to receive the first supply voltage from the first DC-DC converter to generate the first lower supply voltage; and a plurality of linear regulators coupled to receive a supply voltage from a respective one of the DC-DC converters and to generate a respective lower supply voltage, wherein the plurality of linear regulators includes the first linear regulator. Wherein a supply voltage generated by one or more of the DC-DC converters is used to power noise insensitive blocks in the plurality of transceivers, and wherein a supply voltage generated by one or more of the linear voltage regulators is used to power noise sensitive blocks in the plurality of transceivers, and wherein at least a second of the plurality of linear voltage regulators is implemented in a manner similar to the first linear voltage regulator.
Drawings
Example embodiments of the present application will be described with reference to the accompanying drawings, which are briefly described below.
Fig. 1 shows a detailed schematic diagram of a prior art linear regulator, in which clamping is used to reduce the loop gain at high load currents to ensure loop stability.
Fig. 2 shows a detailed schematic diagram of a linear regulator for providing fast transient response in an embodiment of the present application, even when employing a reduced loop gain technique.
Fig. 3 shows a circuit diagram of a unity gain buffer in an embodiment of the present application for providing an increased buffered switching current in case of a transient in the regulated output voltage.
FIG. 4 is a block diagram of an example device/system incorporating a linear regulator implemented in accordance with several aspects of the present application.
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.
Detailed Description
1. Overview
One aspect of the present application enables a linear regulator to provide fast transient response even when a loop gain reduction element is used to provide frequency compensation. In one embodiment, a linear regulator includes a pass transistor, an error amplifier, a buffer, a first component, and a second component. The pass transistor receives an input voltage at a first current terminal. A second current terminal of the pass transistor is coupled to the regulated output node of the voltage regulator and provides a regulated output voltage. The error amplifier receives a reference voltage at a first input and a feedback voltage derived from the regulated output voltage at a second input. The error amplifier generates an error signal indicative of a difference between the reference voltage and the feedback voltage. The buffer has an input terminal connected to the output node of the error amplifier, and an output terminal connected to the control terminal of the pass transistor. The first component is connected between the output node of the error amplifier and the regulated output node for frequency compensation. The second component is connected between the output node of the error amplifier and the first component and is operative to increase an impedance provided by a combination of the first component and the second component between the output node of the error amplifier and the regulated output node in the presence of a voltage transient at the regulated output node. Thereby achieving a fast transient response.
Several aspects of the present application are described below with reference to examples for illustration. One skilled in the relevant art will recognize, however, that the application can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown in detail to avoid obscuring aspects of the application. Furthermore, the described features/aspects may be practiced in various combinations, although only some are described here for the sake of brevity.
2. Example apparatus
FIG. 1 shows a schematic diagram of an example device that may be improved in accordance with several aspects of the present application. Fig. 1 shows a conventional linear regulator 100. As shown, the conventional linear regulator 100 includes an error amplifier 110, a MOSFET clamp (Mclamp)120, a buffer 130, a pass transistor (pass element) 140, and a voltage divider network including a resistor 160 and a resistor 170. In addition, a load capacitance 150 and a load (current) 151 are shown. Terminal 199 represents ground terminal. The pass transistor 140 is an N-type MOSFET (metal oxide semiconductor field effect transistor or NMOS for short), although a P-type transistor is also commonly employed. The NMOS 140 receives an Input voltage (Vin) 101 at a drain (D) terminal from a power supply (not shown). The source (S) of the NMOS 140 is the Output of the regulator, and provides a regulated Output Voltage (VOUT) 145 at the Output. The on-resistance of NMOS 140 is controlled by the voltage applied by error amplifier 110 (via buffer 130) on the gate (G) terminal of NMOS 140 and is adjustable such that VOUT145 is maintained at a desired level despite variations in load current 151 and/or VIN. VCP102 represents the voltage generated internally in the regulator by a charge pump (not shown).
The voltage divider network formed by resistors 160 and 170 receives the output voltage VOUT and provides a portion of VOUT to the negative terminal (-) of the error amplifier 110 as the feedback Voltage (VFB) 171.
The buffer 130 is powered by the VCP102 and is a high bandwidth, unity voltage gain current buffer. Buffer 130 provides the same voltage on node 134 as on node 113. In particular, buffer 130 is intended to provide a voltage 134 having a higher source or sink current to/from node 134. Thus, the buffer 130 is able to quickly charge and discharge the parasitic capacitance between the gate and source terminals of the pass transistor 140 and change the gate voltage of the pass transistor 140 more quickly than would otherwise be possible to allow the on-resistance of the pass transistor to be quickly adjusted to restore VOUT to its desired magnitude in the event of a change in load current. Thus, the feedback loop formed by the voltage divider and the error amplifier quickly corrects for variations (transients) in the regulated output voltage VOUT caused by variations in the load current 151.
As is well known in the related art, frequency compensation is commonly used for negative feedback systems. As with other negative feedback systems, in linear regulators such as regulator 100, frequency compensation is employed to prevent the accidental occurrence of positive feedback, which in turn may cause the regulated output voltage VOUT to oscillate or change in any way from the constant level it should maintain. In addition to preventing positive feedback, frequency compensation may be employed in order to minimize or prevent overshoot and ringing of VOUT in response to disturbances (e.g., step changes in load current and/or VIN).
Frequency compensation may be achieved by modifying the gain and/or phase characteristics of the open-loop transfer function of the voltage regulator. In short, in the open-loop transfer function of the voltage regulator, sufficient gain and/or phase margin is ensured to prevent positive feedback from occurring and to minimize ringing of VOUT in response to step disturbances. The open loop transfer function refers to the ratio of the feedback signal and the error signal, i.e., it is the product of the transfer function of the circuit/block that forms the path from the output 131 of the error amplifier 110 to the input 171 of the error amplifier 110 that receives the feedback signal VFB (171 in fig. 1).
To provide good load regulation, the error amplifier 110 is designed to have a high gain. The regulator 100 has two poles, one at the output node 113 of the error amplifier 110 and the other (the load pole) at the regulated output node VOUT. Since the Load capacitor (Cload) 150 Load is typically quite large (-40 uF), under no-Load conditions, both poles are at very low frequencies and, based on Cload, the Load poles can dominate. As the load current 151 increases, the transconductance of the pass transistor 140 increases and the load pole moves to higher frequencies based on the magnitude of the load current 151. Therefore, Unity Gain Bandwidth (UGB) of the regulator 100 also increases, resulting in a decrease in the phase margin. Therefore, to ensure stability, at higher load currents, the loop gain (open loop gain) needs to be reduced in order to limit the UGB increase to acceptable frequencies. A reduction in loop gain typically reduces load and line regulation.
A technique for reducing the loop gain is employed in the voltage regulator 100, according to which the drain and gate of the transistor (Mclamp 120) are short-circuited and placed between the node 113 and the node 145, as shown in fig. 1. That is, the drain and gate of transistor 120 are connected to node 113, and the source of transistor 120 is connected to VOUT 145. At zero or low load current, the voltage on node 113 is relatively small and therefore Mclamp120 is off. Thus, the loop has a high gain at zero or low load current. However, as the load current increases, the voltage on node 113 increases and Mclamp120 turns on, the on-resistance of transistor 120 (1/Gm, where Gm represents the transconductance of transistor 120) decreases exponentially with respect to voltage 113. Therefore, Mclamp120 presents an impedance between node 113 and node 145 that decreases with increasing load current, thereby correspondingly decreasing loop gain with increasing load current, thereby ensuring loop stability.
However, one disadvantage of using Mclamp120 is that: the presence of Mclamp120 reduces the rate at which the voltage output 113 of error amplifier 110 rises (increases) with increasing load current to correct the corresponding drop in VOUT. In general, the greater the increase in load current (with respect to time), the longer it takes for voltage 113 to increase enough to completely correct the drop in output voltage VOUT. As a result, the transient response of the voltage regulator 100 becomes slow, and the load and line regulation specifications may typically be degraded.
Aspects of the present application are directed to overcoming at least the above disadvantages, while still employing gain limiting using Mclamp120 (or similar impedance), and achieving fast transient response.
3. Achieving fast transient response
Fig. 2 is a detailed schematic diagram illustrating a linear regulator according to aspects of the present application. Fig. 2 shows a linear regulator 200, the linear regulator 200 including an error amplifier 210, a MOSFET clamp (Mclamp for short) 220, a buffer 230, a pass transistor (pass element) 240, a voltage divider network including a resistor 260 and a resistor 270, and a transistor 280. In addition, a load capacitance 250 and a load (current) 251 are also shown. Terminal 299 represents ground. Pass transistor 240 is an N-type MOSFET (metal oxide semiconductor field effect transistor or NMOS for short), although a P-type transistor is also typically employed. In one embodiment, voltage regulator 200 is implemented as a Low-dropout regulator (LDO).
The NMOS 240 receives an Input voltage 201 (Vin) from a power supply (not shown) at a drain (D). The source of NMOS 240 is the Output terminal of regulator 200, at which a regulated Output voltage Vout (Vout) 245 is provided. The on-resistance of NMOS 240 is controlled by the voltage applied by error amplifier 210 (via buffer 230) on the gate (G) of NMOS 240 and is adjustable so that Vout245 is maintained at a desired level despite variations in load current 251 and/or Vin. Vcp 202 represents a voltage generated internally within voltage regulator 200 by a charge pump (not shown). The operation of regulator 200 is similar to the operation of conventional regulator 100, except for the following differences.
In accordance with one aspect of the present application, another transistor 280 is connected in series with McAmp 220. A source of transistor 280 is connected to the drain of transistor 220, a drain of transistor 280 is connected to node 213, and a gate of transistor 280 is connected to output 234 of buffer 230. The source of transistor 220 is connected to Vout245 and the gate of transistor 220 is connected to node 213.
In operation, in the event of a negative transient in the output voltage Vout, the voltage on node 234 is relatively lower than the voltage on node 213 because the gate-source capacitance of pass transistor 240 takes time to charge. Thus, the transistor 280 is off or has a high on-resistance. Accordingly, transistor 220 is also off or has a high on-resistance. Thus, the effective impedance between node 213 and node 245(Vout) is very high, voltage 213 is free to rise, and operates with buffer 230 to quickly restore Vout to the desired constant magnitude. Once steady state is reached, voltage 234 is equal to voltage 213 (buffer 230 is a unity voltage gain buffer) and transistor 280 is fully on. Thus, the series combination of transistors 220 and 280 returns to a low impedance state, the specific magnitude of which depends on load current 251. Thus, during a negative transient in Vout, the operation of transistor 280 serves to at least partially cancel the operation of transistor 220, thereby enabling the voltage regulator to quickly respond to the transient.
In the event of a positive transient in the output voltage Vout, the voltage 213 needs to be reduced. However, this is not a problem because both transistor 220 and transistor 280 are diode connected configurations, and voltage 213 can decrease as the current through both transistors decreases. Thus, the degradation of the load and line conditioning parameters is also minimized.
The components 220 and 280 are shown as being implemented using transistors, but the components 220 and 280 may generally be implemented by a circuit or component that provides an impedance that varies as the load current 251 varies. Thus, transistor 220 may generally be considered a first component connected between the output node 213 of the error amplifier 210 and the regulated output node 245 for frequency compensation of the linear regulator 200. Transistor 280 may be generally considered to be a second component connected between the output node 213 of the error amplifier 210 and the regulated output node 245, and when a voltage transient occurs at the regulated output node, transistor 280 is operated to increase the impedance provided by the combination of the first and second components between the output node 213 of the error amplifier 210 and the regulated output node 245.
The operation of buffer 230 and its implementation in an embodiment is described next.
4. Buffer device
Fig. 3 is a circuit diagram of the buffer 230 in the embodiment of the present application. The parallel combination of transistors 340 and 350, current sink 370, and transistor 345 and current source 375 operate to provide higher current sourcing and current sinking capability to/from node 234 while providing high bandwidth unit voltage gain from node 213 to node 234. Transistor 340, transistor 350, and current well 370 correspond to transistor 232, transistor 233, and current well 231, respectively, of fig. 2. The remaining components of the buffer 230 of fig. 3 form the amplifier 235 and the controllable current source 236 of fig. 2. The parallel combination of transistor 345 and current source 375 corresponds to controllable current source 236 of fig. 2. Current source 360 provides a current equal to 2 x IB. Current source 365 provides a current equal to IB. The transistor size ratio of transistors 330 and 345 is 1: N. The specific values of IB and N are selected according to specific design requirements. The transistor size ratio of transistors 325 and 335 is 1: 1. Transistors 310 and 320 form a differential pair.
In operation, when the voltages at nodes 213 and 234 are equal, a current of magnitude IB flows through transistors 310 and 315, and a current I1 flowing through transistor 325 equals zero. Thus, no current flows through transistors 335, 330, and 345, and the buffer source current is the current provided by current source 375 without a negative transient at Vout. In the event of a negative transient at Vout, voltage 213 is greater than voltage 234 and all current 2 IB provided by current source 360 flows through transistor 320 due to the relatively fast response of error amplifier 210 to the transient and the gate-source capacitance of pass transistor 240. Thus, the current I1 through transistor 325 is approximately equal to IB. Due to the current mirror configuration of transistors 325 and 335 and 330 and 345, current IB flows through transistors 335 and 330 and current N × IB flows through transistor 345. Thus, the source current into node 234 is equal to the sum of N IB and the current provided by current source 375. Thus, buffer 230 provides higher current drive to drive node 234 only during negative transients at Vout. In the event of a positive transient at Vout, transistor 350 provides a low impedance path for node 234 to discharge quickly.
The linear regulator 200 implemented as described above may be incorporated in a larger device or system as briefly described below.
5. Device/system
Fig. 4 is a block diagram showing implementation details of a system incorporating the linear regulator 200 described in detail above in an embodiment of the present application. The system of fig. 4 may be deployed in a Base Transceiver Station (BTS) of a cellular telephone system (eNodeB in LTE-long term evolution), and is referred to herein as a BTS system 400. In general, the BTS system 400 facilitates wireless communication between User Equipment (UE), which may be a mobile station (e.g., a handset) or a fixed User equipment (e.g., a computer with an internet connection). The BTS system 400 may be implemented according to technologies and standards such as Global system for mobile communications (GSM), Code Division Multiple Access (CDMA), third generation mobile communication technology (3rd generation, 3G), fourth generation mobile communication technology (4th generation, 4G), long term evolution (lte), and fifth generation mobile communication technology (5th generation, 5G). BTS system 400 is shown to include transceivers 410A through 410N, duplexers 420A through 420N, combiner 430, antenna 440, battery pack 450, and power supply 460. The specific components/blocks of BTS system 400 are shown by way of illustration only. However, as is well known in the relevant art, typically the BTS system 400 may include more components/blocks, such as temperature sensors, maintenance and configuration blocks, and the like.
Each of the transceivers 410A through 410N operates to transmit and receive communication signals to/from wireless user devices via the corresponding duplexers 420A-420N, combiner 430, and antenna 440. Each transceiver includes a transmitter section and a receiver section. Thus, the transceiver 410A is shown to include a transmitter section including a transmit baseband block 411, a transmit Radio Frequency (RF) block 412, and a power amplifier 413, and a receiver section including a Low-noise amplifier (LNA) 416, a receive RF block 415, and a receive baseband block 414.
Transmit baseband block 411 receives information signals (e.g., representing voice, data) from a Base Station Controller (BSC), which in turn receives communication signals from another user equipment (wireless or fixed) in a network downstream of the BSC, via respective paths shown in bus 499, processes the signals according to respective techniques and protocols to perform modulation, channel coding, and other operations, and forwards the processed signals to transmit RF block 412. The transmit RF block 412 may perform operations such as up-conversion to RF and forward the RF signal to the power amplifier 413. The power amplifier 413 amplifies the received RF signal and transmits the power-amplified signal to a corresponding wireless user equipment through the duplexer 420A, the combiner 430 and the antenna 440.
The operation of the transmitter, receiver, and clock of the other transceivers of fig. 4 is similar to that described above with respect to transceiver 410A, and includes corresponding transmitter and receiver blocks.
Each of duplexers 420A through 420N is capable of transmitting and receiving respective transmit and receive signals (i.e., bi-directional (duplex) communication) over a single path between the respective duplexer and combiner 430. Each of duplexers 420A through 420N may be implemented with two bandpass filters connected in parallel, one filter providing a path between a corresponding transmitter and combiner 430, and the other filter providing a path between combiner 430 and a corresponding receiver.
The combiner 430 combines signals from/to the transceivers 410A to 410N to enable all signals to be transmitted and received using a single antenna 440.
The antenna 440 operates to receive information-bearing wireless signals from and transmit information-bearing wireless signals to the wireless medium between the transceiver and the wireless user equipment.
The battery pack 450 houses a battery that provides power for the operation of the blocks/units in the BTS system 400.
The power supply 460 receives power (e.g., 12 volts) from the battery pack 450 and includes a plurality of DC-DC converters 461A-461M, and a plurality of linear regulators (e.g., implemented as LDOs) 462A-462L. The DC-DC converters 461A-461M generate various voltages (each generating a respective voltage, e.g., 0.7V, 1.2V, 2.0V, 3.6V, etc.) for powering one or more blocks/components of the BTS system 400 described above. In particular, the voltage generated by the DC-DC converter may be used to power less noise sensitive blocks and components (e.g., transmit and receive baseband blocks) in the transceivers 410A through 410N. Thus, the supply voltage 491C is shown as being generated by the DC-DC converter 461A and provided to (the transmit and receive baseband blocks) of the transceiver 410. For clarity and simplicity, only one power connection directly from the DC-DC converter is shown in fig. 4. However, there will be many more such power connections.
Each of the LDOs 462A-462L is connected to receive the output voltage of a corresponding DC-DC converter 461A-461M and generate a corresponding lower voltage as required by some components/blocks of the transceiver. The voltage generated by the LDO is used to power noise sensitive blocks and components in the transceivers 410A through 410N, such as the transmit RF block (e.g., 412), the receive RF block (e.g., 415), the LNA (e.g., 416), and the clock (e.g., 417) included in the transceiver. For clarity and simplicity, only two power connections 491A and 491B (from LDO 462A and LDO 462L, respectively) are shown in fig. 4. However, there are more power connections from the LDO to the corresponding block in the transceiver. Compared to a DC-DC converter, an LDO may have better load and line regulation and thus may provide a cleaner supply voltage while being less noisy, as required by the noise sensitive blocks described above.
One or more of LDOs 462A-462-L are implemented as linear regulator 200 as described in detail above.
It is noted here that the linear regulator 200 may also be used in other systems, such as separate transmitters and receivers, mobile phones, etc.
6. Conclusion
Reference throughout this specification to "one embodiment" or "an embodiment" or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, appearances of the phrases "in one embodiment" and "in an embodiment" or similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.
Although in the illustrations of fig. 1, 2, 3 and 4, the terminals/nodes are shown as having direct connections to (i.e., "connected to") various other terminals, it should be understood that additional components (as appropriate for the particular environment) may also be present in the path, and thus the connections may be considered as being "electrically coupled" to the same connection terminals.
It should be understood that the particular types of transistors (e.g., NMOS, PMOS, etc.) mentioned above are for illustration only. However, alternative embodiments using different configurations and transistors will be apparent to those skilled in the relevant art from reading the disclosure provided herein. For example, the NMOS transistor may be replaced with a PMOS (P-type metal oxide semiconductor) transistor while the connections to the power supply and the ground terminal are interchanged.
Therefore, in the present application, the power supply terminal and the ground terminal are referred to as constant reference potentials, the source (emitter) and the drain (collector) of the transistor (which provide a current path when on and an open circuit path when off) are referred to as current terminals, and the gate (base) is referred to as a control terminal.
While various embodiments of the present application have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the present application should not be limited by any of the above-described embodiments, but should be defined only in accordance with the following claims appended hereto and their equivalents.
Claims (18)
1. A linear regulator, comprising:
a pass transistor having a first current terminal coupled to receive an input voltage and a second current terminal coupled to a regulated output node of the linear regulator and providing a regulated output voltage;
an error amplifier coupled to receive a reference voltage from a first input and a feedback voltage from a second input, the feedback voltage being derived from the regulated output voltage; the error amplifier is configured to generate an error signal at an output node of the error amplifier indicative of a difference between the reference voltage and the feedback voltage;
a buffer having an input coupled to the output node of the error amplifier and an output coupled to the control terminal of the pass transistor;
a first component coupled between an output node of the error amplifier and the regulated output node for frequency compensation of the linear regulator; and
a second component coupled between the output node of the error amplifier and the first component, the second component to increase an impedance provided by a combination of the first and second components between the output node of the error amplifier and the regulated output node during a voltage transient at the regulated output node.
2. The linear regulator of claim 1, wherein the first component is a first transistor and the second component is a second transistor; wherein:
a control terminal of the first transistor is coupled to the output node of the error amplifier, a second current terminal of the first transistor is coupled to the regulated output node, an
The control end of the second transistor is coupled to the output end of the buffer, the first current end of the second transistor is coupled to the output node of the error amplifier, and the second current end of the second transistor is coupled to the first current end of the first transistor.
3. The linear regulator of claim 2, wherein the voltage transient is a negative voltage transient, wherein the second component is to increase the impedance for the duration of the negative voltage transient.
4. The linear regulator of claim 3, further comprising a load capacitor coupled between the regulated output node of the linear regulator and a first constant reference potential, wherein:
the combination of the capacitance of the load capacitance and the transconductance of the pass transistor creates a pole in an open loop transfer function of the linear regulator, wherein a frequency location of the pole varies with a magnitude of a load current drawn from the regulated output node,
the combination of the first transistor and the second transistor is to reduce a gain of the open loop transfer function based on a magnitude of the load current to provide the frequency compensation.
5. The linear regulator of claim 4, the pass transistor being an N-type metal oxide semiconductor field effect transistor (NMOS).
6. The linear regulator according to claim 1, wherein each of the error amplifier and the buffer is powered by a charge pump having limited current capability,
wherein the voltage transient is a negative voltage transient during which the buffer is used to increase a current output from the buffer to rapidly charge a parasitic gate-source capacitance of the pass transistor to enable rapid correction of the negative voltage transient.
7. The linear regulator of claim 6, wherein the buffer comprises:
a first transistor and a second transistor coupled in a current mirror configuration, a first current terminal of the first transistor being coupled to an output node of the error amplifier, a second current terminal of the first transistor being coupled to a control terminal of each of the first and second transistors, a first current terminal of the second transistor being coupled to a control terminal of the pass transistor, and a second current terminal of the second transistor being coupled to the regulated output node;
a first current source having a first terminal coupled to the second current terminal of the first transistor and a second terminal coupled to the first constant reference potential;
a second current source having a first terminal coupled to a second constant reference potential and a second terminal coupled to the control terminal of the pass transistor;
a third transistor and a fourth transistor coupled as a differential pair, wherein a control terminal of the third transistor is coupled to an output node of the error amplifier, and the fourth transistor is coupled to a control terminal of the pass transistor;
a third current source having a first terminal coupled to the second constant reference potential and a second terminal coupled to a first current terminal of each of the third and fourth transistors;
a fifth transistor having a first current terminal and a control terminal, the first current terminal and the control terminal each coupled to a second current terminal of the third transistor, a second current terminal of the fifth transistor coupled to the first constant reference potential;
a sixth transistor having a first current terminal and a control terminal, the first current terminal and the control terminal each coupled to a second current terminal of the fourth transistor, a second current terminal of the sixth transistor coupled to the first constant reference potential;
a fourth current source having a first terminal coupled to the second current terminal of the fourth transistor and a second terminal coupled to the first constant reference potential;
a seventh transistor coupled to the sixth transistor in a current mirror configuration, a control terminal of the seventh transistor being coupled to a control terminal of the sixth transistor, a second current terminal of the seventh transistor being coupled to the first constant reference potential;
an eighth transistor having a second current terminal and a control terminal, the second current terminal and the control terminal each coupled to the first current terminal of the seventh transistor, the first current terminal of the eighth transistor coupled to the second constant reference potential; and
a ninth transistor coupled to the eighth transistor in a current mirror configuration, a control terminal of the ninth transistor being coupled to a control terminal of the eighth transistor, a first current terminal of the ninth transistor being coupled to the second constant reference potential, and a second current terminal of the ninth transistor being coupled to a control terminal of the pass transistor.
8. The linear regulator according to claim 7, wherein in the absence of the voltage transient, a voltage at an output node of the error amplifier is equal to a voltage at a control terminal of the pass transistor, and the ninth transistor is in an off state,
wherein when there is a negative voltage transient, the voltage at the output node of the error amplifier exceeds the voltage at the control terminal of the pass transistor, the ninth transistor is in a conductive state, and the parallel combination of the ninth transistor and the second current source provides increased current drive to the control terminal of the pass transistor.
9. A system, comprising:
a power terminal coupled to a power source; and
a power supply unit coupled to receive power from the power terminal, the power supply unit including a first linear regulator coupled to receive the power and generate a first lower supply voltage,
wherein the first linear regulator includes:
a pass transistor having a first current terminal coupled to receive an input voltage and a second current terminal coupled to a regulated output node of the linear regulator and providing a regulated output voltage;
an error amplifier coupled to receive a reference voltage from a first input and a feedback voltage from a second input, the feedback voltage being derived from the regulated output voltage; the error amplifier is configured to generate an error signal at an output node of the error amplifier indicative of a difference between the reference voltage and the feedback voltage;
a buffer having an input coupled to the output node of the error amplifier and an output coupled to the control terminal of the pass transistor;
a first component coupled between an output node of the error amplifier and the regulated output node for frequency compensation of the linear regulator; and
a second component coupled between the output node of the error amplifier and the first component, the second component to increase an impedance provided by a combination of the first and second components between the output node of the error amplifier and the regulated output node during a voltage transient at the regulated output node.
10. The system of claim 9, further comprising:
an antenna;
a first duplexer coupled to the antenna; and
a first transceiver, wherein the first lower supply voltage is used to power noise sensitive blocks in the first transceiver,
the first transceiver includes a transmitter portion and a receiver portion each coupled to the first duplexer, the first transceiver transmitting communication signals to a wireless medium via the first duplexer and the antenna, the first transceiver also receiving communication signals from the wireless medium via the first duplexer and the antenna.
11. The system of claim 10, wherein the system is a Base Transceiver Station (BTS) system, the BTS system further comprising:
a combiner coupled to the antennas;
a plurality of duplexers, each of the plurality of duplexers coupled to the combiner, the plurality of duplexers including the first duplexer; and
a plurality of transceivers, including the first transceiver, each of the plurality of transceivers including a transmitter section and a receiver section, coupled at one end to a respective one of the plurality of duplexers and coupled at another end to a base station controller, BSC, wherein each of the plurality of transceivers is to transmit an information signal received from the base station controller into the wireless medium via a respective one of the plurality of duplexers, the combiner, and the antenna, and to forward an information signal received from the wireless medium to the base station controller via a respective one of the plurality of duplexers, the combiner, and the antenna;
wherein the power supply unit includes:
a plurality of DC-DC converters coupled to receive the power from the power terminal and generate respective supply voltages, the plurality of DC-DC converters including a first DC-DC converter to generate a first supply voltage, wherein the first supply voltage is used to power noise-insensitive blocks in the first transceiver, wherein the first linear regulator is coupled to receive the first supply voltage from the first DC-DC converter to generate the first lower supply voltage; and
a plurality of linear voltage regulators coupled to receive a supply voltage from a respective one of the DC-DC converters and to generate a respective lower supply voltage, wherein the plurality of linear voltage regulators includes the first linear voltage regulator,
wherein a supply voltage generated by one or more of the DC-DC converters is used to power noise-insensitive blocks in the plurality of transceivers, and wherein a supply voltage generated by one or more of the linear voltage regulators is used to power noise-sensitive blocks in the plurality of transceivers, an
Wherein at least a second linear regulator of the plurality of linear regulators is implemented in a similar manner as the first linear regulator.
12. The system of claim 11, wherein the first component is a first transistor and the second component is a second transistor, wherein:
a control terminal of the first transistor is coupled to the output node of the error amplifier, a second current terminal of the first transistor is coupled to the regulated output node, an
The control end of the second transistor is coupled to the output end of the buffer, the first current end of the second transistor is coupled to the output node of the error amplifier, and the second current end of the second transistor is coupled to the first current end of the first transistor.
13. The system of claim 12, wherein the voltage transient is a negative voltage transient, wherein the second component is to increase the impedance for a duration of the negative voltage transient.
14. The system of claim 13, wherein the linear regulator further comprises a load capacitor coupled between the regulated output node of the linear regulator and a first constant reference potential, wherein:
the combination of the capacitance of the load capacitance and the transconductance of the pass transistor creates a pole in an open loop transfer function of the linear regulator, wherein a frequency location of the pole varies with a magnitude of a load current drawn from the regulated output node,
the combination of the first transistor and the second transistor is to reduce a gain of the open loop transfer function based on a magnitude of the load current to provide the frequency compensation.
15. The system of claim 14, wherein the pass transistor is an N-type metal oxide semiconductor field effect transistor (NMOS).
16. The system of claim 15, wherein each of the error amplifier and the buffer is powered by a charge pump having limited current capability,
wherein the voltage transient is a negative voltage transient during which the buffer is used to increase a current output from the buffer to rapidly charge a parasitic gate-source capacitance of the pass transistor to enable rapid correction of the negative voltage transient.
17. The system of claim 16, wherein the buffer comprises:
a first transistor and a second transistor coupled in a current mirror configuration, a first current terminal of the first transistor being coupled to an output node of the error amplifier, a second current terminal of the first transistor being coupled to a control terminal of each of the first and second transistors, a first current terminal of the second transistor being coupled to a control terminal of the pass transistor, and a second current terminal of the second transistor being coupled to the regulated output node;
a first current source having a first terminal coupled to the second current terminal of the first transistor and a second terminal coupled to the first constant reference potential;
a second current source having a first terminal coupled to a second constant reference potential and a second terminal coupled to the control terminal of the pass transistor;
a third transistor and a fourth transistor coupled as a differential pair, wherein a control terminal of the third transistor is coupled to an output node of the error amplifier, and the fourth transistor is coupled to a control terminal of the pass transistor;
a third current source having a first terminal coupled to the second constant reference potential and a second terminal coupled to a first current terminal of each of the third and fourth transistors;
a fifth transistor having a first current terminal and a control terminal, the first current terminal and the control terminal each coupled to a second current terminal of the third transistor, a second current terminal of the fifth transistor coupled to the first constant reference potential;
a sixth transistor having a first current terminal and a control terminal, the first current terminal and the control terminal each coupled to a second current terminal of the fourth transistor, a second current terminal of the sixth transistor coupled to the first constant reference potential;
a fourth current source having a first terminal coupled to the second current terminal of the fourth transistor and a second terminal coupled to the first constant reference potential;
a seventh transistor coupled to the sixth transistor in a current mirror configuration, a control terminal of the seventh transistor being coupled to a control terminal of the sixth transistor, a second current terminal of the seventh transistor being coupled to the first constant reference potential;
an eighth transistor having a second current terminal and a control terminal, the second current terminal and the control terminal each coupled to the first current terminal of the seventh transistor, the first current terminal of the eighth transistor coupled to the second constant reference potential; and
a ninth transistor coupled to the eighth transistor in a current mirror configuration, a control terminal of the ninth transistor being coupled to a control terminal of the eighth transistor, a first current terminal of the ninth transistor being coupled to the second constant reference potential, and a second current terminal of the ninth transistor being coupled to a control terminal of the pass transistor.
18. The system of claim 17, wherein in the absence of the voltage transient, a voltage at an output node of the error amplifier is equal to a voltage at a control terminal of the pass transistor and the ninth transistor is in an off state,
wherein when there is a negative voltage transient, the voltage at the output node of the error amplifier exceeds the voltage at the control terminal of the pass transistor, the ninth transistor is in a conductive state, and the parallel combination of the ninth transistor and the second current source provides increased current drive to the control terminal of the pass transistor.
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| IN202141020190 | 2021-05-03 | ||
| US17/457,267 US20220352818A1 (en) | 2021-05-03 | 2021-12-02 | Enabling fast transient response in a linear regulator when loop- gain reduction is employed for frequency compensation |
| US17/457,267 | 2021-12-02 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114942341A (en) * | 2022-07-27 | 2022-08-26 | 苏州联讯仪器有限公司 | Digital source table control method, system, device and storage medium |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040164789A1 (en) * | 2002-12-23 | 2004-08-26 | The Hong Kong University Of Science And Technology | Low dropout regulator capable of on-chip implementation |
| US20070159146A1 (en) * | 2005-12-30 | 2007-07-12 | Stmicroelectronics Pvt. Ltd. | Low dropout regulator |
| CN101105696A (en) * | 2007-08-08 | 2008-01-16 | 中国航天时代电子公司第七七一研究所 | Voltage buffer circuit for linear potentiostat |
| CN101419479A (en) * | 2008-12-10 | 2009-04-29 | 武汉大学 | Low-voltage difference linear constant voltage regulator with novel structure |
| US7843180B1 (en) * | 2008-04-11 | 2010-11-30 | Lonestar Inventions, L.P. | Multi-stage linear voltage regulator with frequency compensation |
| CN101957628A (en) * | 2009-07-17 | 2011-01-26 | 上海沙丘微电子有限公司 | Self-adaption zero-frequency compensation circuit in low-voltage difference linear voltage regulator |
| CN103838286A (en) * | 2012-11-20 | 2014-06-04 | 杨洁 | Low dropout linear regulator with quick transient response and high stability |
| US20140312864A1 (en) * | 2013-04-18 | 2014-10-23 | Linear Technology Corporation | Light load stability circuitry for ldo regulator |
| US20150198960A1 (en) * | 2014-01-14 | 2015-07-16 | Broadcom Corporation | Low-power low-dropout voltage regulators with high power supply rejection and fast settling performance |
| CN206627849U (en) * | 2017-04-13 | 2017-11-10 | 成都信息工程大学 | The CMOS low pressure difference linear voltage regulators and electronic equipment of dynamic miller compensation |
| US9891644B1 (en) * | 2016-08-09 | 2018-02-13 | University Of Electronic Science And Technology Of China | Low-dropout regulator with dynamic pole tracking circuit for improved stability |
| CN108776500A (en) * | 2018-05-31 | 2018-11-09 | 河海大学常州校区 | It is a kind of based on frequency compensation and transient response improve circuit without capacitance LDO outside piece |
| CN110928358A (en) * | 2019-11-29 | 2020-03-27 | 芯原微电子(上海)股份有限公司 | Low dropout voltage regulating circuit |
-
2022
- 2022-01-21 CN CN202210074625.7A patent/CN114578884B/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040164789A1 (en) * | 2002-12-23 | 2004-08-26 | The Hong Kong University Of Science And Technology | Low dropout regulator capable of on-chip implementation |
| US20070159146A1 (en) * | 2005-12-30 | 2007-07-12 | Stmicroelectronics Pvt. Ltd. | Low dropout regulator |
| CN101105696A (en) * | 2007-08-08 | 2008-01-16 | 中国航天时代电子公司第七七一研究所 | Voltage buffer circuit for linear potentiostat |
| US7843180B1 (en) * | 2008-04-11 | 2010-11-30 | Lonestar Inventions, L.P. | Multi-stage linear voltage regulator with frequency compensation |
| CN101419479A (en) * | 2008-12-10 | 2009-04-29 | 武汉大学 | Low-voltage difference linear constant voltage regulator with novel structure |
| CN101957628A (en) * | 2009-07-17 | 2011-01-26 | 上海沙丘微电子有限公司 | Self-adaption zero-frequency compensation circuit in low-voltage difference linear voltage regulator |
| CN103838286A (en) * | 2012-11-20 | 2014-06-04 | 杨洁 | Low dropout linear regulator with quick transient response and high stability |
| US20140312864A1 (en) * | 2013-04-18 | 2014-10-23 | Linear Technology Corporation | Light load stability circuitry for ldo regulator |
| US20150198960A1 (en) * | 2014-01-14 | 2015-07-16 | Broadcom Corporation | Low-power low-dropout voltage regulators with high power supply rejection and fast settling performance |
| US9891644B1 (en) * | 2016-08-09 | 2018-02-13 | University Of Electronic Science And Technology Of China | Low-dropout regulator with dynamic pole tracking circuit for improved stability |
| CN206627849U (en) * | 2017-04-13 | 2017-11-10 | 成都信息工程大学 | The CMOS low pressure difference linear voltage regulators and electronic equipment of dynamic miller compensation |
| CN108776500A (en) * | 2018-05-31 | 2018-11-09 | 河海大学常州校区 | It is a kind of based on frequency compensation and transient response improve circuit without capacitance LDO outside piece |
| CN110928358A (en) * | 2019-11-29 | 2020-03-27 | 芯原微电子(上海)股份有限公司 | Low dropout voltage regulating circuit |
Non-Patent Citations (1)
| Title |
|---|
| 王欢;晋春;张贞凯;: "基于频率补偿和瞬态响应改善电路的低压差线性稳压器设计", 机电信息, no. 24 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114942341A (en) * | 2022-07-27 | 2022-08-26 | 苏州联讯仪器有限公司 | Digital source table control method, system, device and storage medium |
| CN114942341B (en) * | 2022-07-27 | 2022-11-01 | 苏州联讯仪器有限公司 | Digital source table control method, system, device and storage medium |
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|---|---|
| CN114578884B (en) | 2024-02-02 |
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