CN114556559A

CN114556559A - Receiving chip, distance measuring device and movable platform

Info

Publication number: CN114556559A
Application number: CN202080014594.5A
Authority: CN
Inventors: 郑国光; 洪小平; 王国才; 黄潇
Original assignee: SZ DJI Technology Co Ltd
Current assignee: SZ DJI Technology Co Ltd
Priority date: 2020-09-27
Filing date: 2020-09-27
Publication date: 2022-05-27
Also published as: WO2022061819A1

Abstract

A receiving chip, a ranging device and a movable platform are provided, wherein the receiving chip comprises: the avalanche photodiode chip (10), the avalanche photodiode chip (10) includes a plurality of back-illuminated avalanche photodiodes and a plurality of first connection bumps (110), the first connection bumps (110) are electrically connected with the back-illuminated avalanche photodiodes; the signal processing chip (20), the signal processing chip (20) includes a plurality of signal processing units and a plurality of second connection bumps (204), the second connection bumps (204) are electrically connected with the signal processing units; wherein the avalanche photodiodes corresponding up and down are connected with the signal processing unit via the first connection bumps (110) and the second connection bumps (204); the receiving chip is a high-integration and arrayed receiving chip, such as an APD chip including an area array, and has more stable performance and excellent reliability.

Description

Receiving chip, distance measuring device and movable platform

Description

Technical Field

The present application relates generally to the field of integrated circuits, and more particularly to a receiving chip, a ranging device, and a movable platform.

Background

The laser radar is a radar system that detects a characteristic quantity such as a position, a speed, and the like of an object by emitting a laser beam. The photosensitive sensor of the laser radar can convert the acquired optical pulse signal into an electric signal, and the time information corresponding to the electric signal is acquired based on the comparator, so that the distance information between the laser radar and the target object is obtained.

At present, mechanical rotary laser radars are mostly adopted in the technical scheme of the laser radars. It has the following disadvantages: reliability is low, in mechanical rotary lidar systems, a plurality of mechanical parts are introduced, in particular with movable parts. The production efficiency is low, the structure is complex, and each line needs to be respectively aligned, so that the difficulty of automatic assembly is caused. The cost is high, such as 64 line radars, which require 64 Laser diodes (Laser diodes) and 64 Avalanche Photodiodes (APDs), resulting in very high material cost. In addition, there is a high labor cost associated with complicated assembly.

The chip used in the mechanical rotary laser radar for receiving the optical pulse sequence reflected by the detection object is mostly a single-line APD, or a small-scale APD line array or APD surface array (generally within tens of channels, hardly exceeding hundreds of channels). The hardware scheme, mostly a test system composed of discrete APD devices and board-level hardware circuits, is not high in integration level, and once developed to a higher line number, is severely limited by technical difficulties and cost pressure, becomes a bottleneck difficult to solve, and is difficult to further evolve.

It is therefore desirable to provide a different chip for receiving a sequence of optical pulses reflected by a probe to overcome the above problems.

Disclosure of Invention

A first aspect of the present application provides a receiving chip, including:

an avalanche photodiode chip comprising a plurality of back-illuminated avalanche photodiodes and a plurality of first connection bumps electrically connected to the back-illuminated avalanche photodiodes;

the signal processing chip comprises a plurality of signal processing units and a plurality of second connecting bumps, and the second connecting bumps are electrically connected with the signal processing units;

the avalanche photodiodes corresponding to each other up and down are connected with the signal processing unit through the first connecting bumps and the second connecting bumps.

A second aspect of the present application provides a ranging apparatus, comprising:

an optical transmission circuit for emitting a sequence of optical pulses;

the receiving chip is configured to receive the optical pulse train emitted by the optical transmitting circuit and reflected by the detected object, and output a time signal based on the received optical pulse train;

and the arithmetic circuit is used for calculating the distance between the detected object and the distance measuring device according to the time signal.

A third aspect of the present application provides a movable platform comprising:

a movable platform body;

the distance measuring device is arranged on the movable platform body.

The application provides a receiving chip, range unit and movable platform. The receiving chip comprises an area array avalanche photodiode chip, and an existing Avalanche Photodiode (APD) manufacturing platform and technology can be utilized to produce the APD area array chip in a large-scale, low-cost and high-reliability manner so as to meet the requirement of the solid-state laser radar on the receiving end chip. And integrally packaging the avalanche photodiode chip and the signal processing chip together by using the first connecting bump and the second connecting bump through a chip interconnection technology in the receiving chip. The receiving chip is a high-integration and arrayed receiving chip, namely an area-arrayed APD receiving chip, and has more stable performance and excellent reliability.

The avalanche photodiode and the signal processing unit are connected with each other through the first connecting bump and the second connecting bump, the connection mode is more beneficial to miniaturization of the connection of the first connecting bump and the second connecting bump, for example, the diameter of the first connecting bump and the second connecting bump can be 50 micrometers and the pitch of the second connecting bump can be 100 micrometers, and the problems that the solder ball is seriously melted and overflowed integrally when being connected with a connecting pad at present, the pitch is difficult to be reduced (the minimum is 200 micrometers) and the connection is easy to be broken can be avoided.

The method for mutually connecting the first connecting bump and the second connecting bump in the application has higher reliability, the height of the first connecting bump and the height of the second connecting bump can be more than 100 mu m, the tensile strength is increased, and the reliability can be effectively improved.

Drawings

Fig. 1A-1C are schematic cross-sectional views illustrating avalanche photodiode chips in a receiver chip provided in various embodiments of the present application;

fig. 2 is a schematic cross-sectional view of the signal processing chip in the receiving chip provided in the present application;

fig. 3A-3D are schematic cross-sectional views of a receiving chip provided in various embodiments of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, exemplary embodiments according to the present application will be described in detail below with reference to the accompanying drawings. It should be understood that the described embodiments are only some embodiments of the present application and not all embodiments of the present application, and that the present application is not limited by the example embodiments described herein. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the application described in the application without inventive step, shall fall within the scope of protection of the application.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art, that the present application may be practiced without one or more of these specific details. In other instances, well-known features of the art have not been described in order to avoid obscuring the present application.

It is to be understood that the present application is capable of implementation in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In order to provide a thorough understanding of the present application, detailed steps and detailed structures will be provided in the following description in order to explain the technical solutions proposed in the present application. The following detailed description of the preferred embodiments of the present application, however, will suggest that the present application may have other embodiments in addition to these detailed descriptions.

In order to solve the foregoing problem, a first aspect of the present application provides a receiving chip including:

The avalanche photodiode and the signal processing unit are connected with each other through the first connecting bump and the second connecting bump, the connection mode is more beneficial to miniaturization of the connection of the first connecting bump and the second connecting bump, for example, the diameter of the first connecting bump and the diameter of the second connecting bump can be 50 micrometers, the pitch of 100 micrometers can be achieved, and the problems that the solder balls are seriously melted and overflowed integrally when being connected with a connecting pad at present, the pitch is difficult to be reduced (the minimum is 200 micrometers), and the solder balls are small and easy to be broken can be avoided.

The receiving chip is described in detail with reference to the accompanying drawings, wherein fig. 1A to 1C are schematic cross-sectional views of the avalanche photodiode chip in the receiving chip provided in various embodiments of the present application; fig. 2 is a schematic cross-sectional view of the signal processing chip in the receiving chip provided in the present application; fig. 3A-3D are schematic cross-sectional views of a receiving chip provided in various embodiments of the present application.

First, the avalanche photodiode chip, the signal processing chip, and the receiving chip will be described. As shown in fig. 1A to 1C, the avalanche photodiode chip 10 includes:

a heavily doped substrate 101, the substrate 101 comprising a first surface and a second surface disposed opposite to each other;

an epitaxial layer 102 disposed on the first surface;

a back-illuminated avalanche photodiode array disposed in the epitaxial layer;

a through silicon via 103, wherein the through silicon via 103 penetrates through the epitaxial layer and the substrate 101, and the side wall of the through silicon via 103 is vertical;

and a second wiring layer 104 disposed on the through silicon via 103.

Wherein the substrate 101 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others.

Wherein the substrate 101 is a heavily doped substrate with a doping concentration in the range of 5 x 10¹⁸/cm ³-5×10 ²⁰/cm ³。

The thickness of the substrate 101 in the avalanche photodiode chip 10 is in a range from 0.1 μm to 5 μm, for example, in an embodiment of the present application, the thickness of the thinned substrate 101 is in a range from 3 μm to 5 μm, in order to ensure that light enters from the first surface of the substrate 101 and is absorbed by an absorption layer in the back-illuminated avalanche photodiode.

The thickness of the substrate 101 is reduced to about 3-5 um, so that the minimum light absorbed by the substrate 101 can be ensured, and most of the light is absorbed by the absorption layer of the back-illuminated avalanche photodiode, so that the performance of the back-illuminated avalanche photodiode is improved.

Alternatively, in an embodiment of the present application, the doping impurities may be implanted by an ion implanter. Specifically, the energy for ion implantation on the surface of the substrate 101 is 5Kev-50 Kev; for example, in one embodiment, the impurities are implanted at an energy of about 10 keV.

Further, after the ion implantation, the substrate can be rapidly annealed to eliminate defects formed by the ion implantation. In one embodiment of the present application, the temperature of the rapid annealing is 800 ℃ to 1600 ℃; the time of the rapid annealing is 10s-300 s.

In an embodiment of the present application, the substrate 101 is selected from silicon.

The substrate 101 includes a first surface and a second surface that are oppositely disposed, where the first surface is a front surface and the second surface is a back surface.

An epitaxial layer 102 is formed on the first surface of the substrate 101, wherein the epitaxial layer 102 may be made of a semiconductor material, and in an embodiment of the present application, an epitaxial silicon wafer is used.

The epitaxial layer 102 has a thickness in the range of 20-40 μm to form an array of avalanche photodiodes in the epitaxial layer 102.

The epitaxial layer 102 includes a first surface and a second surface which are oppositely disposed, the second surface of the epitaxial layer is disposed on the substrate 101, and the first surface of the epitaxial layer is far away from the substrate 101. The first surface is a front surface, and the second surface is a back surface.

Optionally, the epitaxial layer 102 has a low doping type, which may be N-type or P-type, and usually the epitaxial layer 102 is P-type doped.

Wherein the doping concentration of the epitaxial layer 102 is less than or equal to 1 × 10¹⁵/cm ³。

In the present application, the epitaxial layer 102 is set to be of a low doping type, so that the consumption of photon-generated carriers generated in the APD can be reduced, the photon-generated carriers can rapidly reach an avalanche collecting region of the APD, the corresponding speed of the APD is increased, the problem of trailing of the APD is avoided, and the delay of a device is avoided.

A back-illuminated avalanche photodiode array is formed on the first surface of the epitaxial layer 102 (the front side of the epitaxial layer).

Wherein the back-illuminated avalanche photodiode array may comprise rows and/or columns of back-illuminated avalanche photodiodes.

Wherein the back-illuminated avalanche photodiode may comprise an arrangement of rows or columns to form a linear array of back-illuminated avalanche photodiodes. In addition, the back-illuminated avalanche photodiode can also include an arrangement of rows and columns to form an area array of back-illuminated avalanche photodiodes. The number of the back-illuminated avalanche photodiodes is not limited to a certain range of values and can be selected according to actual needs.

It should be noted that the array formed by the back-illuminated avalanche photodiode may be arranged in other forms besides the linear array and the planar array, and is not limited to the linear array and the planar array, and may also be arranged in an irregular manner, and the like, and may be set according to actual needs.

In one embodiment of the present application, a plurality of rows and columns of avalanche photodiodes are formed on the surface of the epitaxial layer 102. The forming method comprises the following steps: forming a photoresist mask layer on the first surface of the epitaxial layer 102, performing photolithography to expose a region to be subjected to ion implantation, and performing an ion implantation process to sequentially form each functional region of the avalanche photodiode from bottom to top on the first surface of the epitaxial layer 102, wherein each functional region of the avalanche photodiode comprises a buffer layer, a diffusion barrier layer, an avalanche multiplication layer, an absorption layer and a contact layer.

Further, an electric field control layer and a graded layer may be further formed between the avalanche multiplication layer and the absorption layer.

In an embodiment of the application, the avalanche photodiode comprises a p-InP buffer layer, a p-AlInAs diffusion barrier layer, a low-doped n-InP avalanche multiplication layer, an n-InP electric field control layer, an n-InGaAsP gradual change layer, an nInGaAs light absorption layer, a semi-insulating InP window layer and an InGaAs contact layer from bottom to top in sequence.

The doping concentration and thickness of each functional layer of the avalanche photodiode can be conventional doping concentration and thickness, and are not listed here.

A through-silicon-via 103 is formed in the epitaxial layer 102 and the substrate 101, the through-silicon-via 103 penetrating the epitaxial layer and being partially embedded in the substrate.

The side wall of the through silicon via is vertical so as to realize vertical connection between two electrodes of the back-illuminated avalanche photodiode in the avalanche photodiode chip, wherein the through silicon via leads out a high-voltage signal.

The side walls of the through silicon vias are vertical, the filling effect is better when the through silicon vias are prepared, wiring layers with better quality are easier to form above the through silicon vias with the vertical side walls, the area of a chip is saved, the through silicon vias are more compatible with a subsequent deposition process, subsequent processes are not limited completely, the compatibility of the process is improved, and the yield of the avalanche photodiode chip is further improved.

Optionally, the through-silicon via 103 is disposed in the epitaxial layer 102 and the edge region of the substrate 101, so as to isolate the high-voltage pin of the through-silicon via 103 from the output pins of the back-illuminated avalanche photodiode, and the voltage of the output pins of the back-illuminated avalanche photodiode is low, so that a relatively large voltage difference is formed, so as to prevent the distance between the through-silicon via and the back-illuminated avalanche photodiode from being too close, thereby avoiding coupling with the pins of the back-illuminated avalanche photodiode and reducing the risk of failure.

Wherein, 2 or more through silicon vias 103 are formed at the edges of the epitaxial layer 102 and the substrate 101 to prevent a large difference in high voltage between two sides of the avalanche photodiode chip.

In an embodiment of the present application, the through silicon vias 103 are symmetrically distributed around the epitaxial layer 102 and the substrate 101, for example, when the substrate 101 is circular, 2 through silicon vias 103 are formed at the edge of the substrate, and the through silicon vias 103 are oppositely disposed at the edge and located at two ends of the diameter in the substrate.

Wherein 2 or more through silicon vias 103 are formed at the edges of the epitaxial layer 102 and the substrate 101. In an embodiment of the present application, the through silicon vias 103 are symmetrically distributed around the epitaxial layer 102 and the substrate 101, for example, when the substrate 101 is circular, 2 through silicon vias are formed at the edge of the substrate, and the through silicon vias are oppositely disposed at the edge and respectively located at two ends of the diameter in the substrate.

The forming method of the through silicon via comprises the following steps:

step A1: patterning the epitaxial layer 102 and a part of the substrate 101 to form a through silicon via groove in the epitaxial layer 102 and the substrate 101;

step A2: the through-silicon via recess is at least partially filled with a first conductive material to form the through-silicon via 103.

In the step S32, a first conductive material is formed in the through silicon via groove 10 to at least partially fill the through silicon via groove 10, thereby forming the through silicon via 103.

The first conductive material may be tungsten, InGaAs (indium gallium arsenide), or a hollow copper tube. The first conductive material may completely fill the through silicon via groove 10, and the first conductive material may be disposed on a sidewall of the through silicon via groove 10, for example, in an embodiment of the present application, tungsten or InGaAs (indium gallium arsenide) is selected to completely fill the through silicon via groove 10, or a hollow copper tube is inserted into the through silicon via groove 10, so as to form the through silicon via 103.

Further, as shown in fig. 1B, an isolation structure 112 is formed between adjacent back-illuminated avalanche photodiodes to prevent signals between adjacent back-illuminated avalanche photodiodes from interfering with each other and/or forming a bridge, which may cause device failure.

Optionally, the shape of the top view of the isolation structure 112 is circular or elliptical, which is not listed here.

Wherein the isolation structure 112 may be formed after the formation of the through silicon via 103, or the isolation structure may also be formed at the same time as the formation of the through silicon via 103.

In an embodiment of the present application, the method of forming the isolation structure 112 specifically includes:

patterning the epitaxial layer 102 and a part of the substrate 101 to form an isolation groove; the isolation recess is at least partially filled with a second conductive material to form the isolation structure 112.

The first conductive material and the second conductive material may be the same or different, and may be selected according to actual requirements.

Optionally, the second conductive material may be tungsten paste, a hollow copper tube, or polysilicon.

Wherein the isolation structure 112 is filled with the second conductive material for optical isolation between adjacent ones of the back-illuminated avalanche photodiodes.

In another embodiment of the present application, the forming of the isolation structure 112 simultaneously with the forming of the through silicon via 103 specifically includes:

patterning the epitaxial layer 102 and a part of the substrate 101 to form the through silicon via groove 10, and simultaneously forming an isolation groove in the epitaxial layer; the isolation groove is filled with the first conductive material while the through-silicon via groove is filled with the first conductive material to form the isolation structure 112. The isolation structure 112 is formed at the same time of forming the through silicon via 103, so that the preparation process is simpler and the manufacturing cost is reduced.

Optionally, as shown in fig. 1C, before the first conductive material or the second conductive material is filled in the tsv recess 10, the method further includes a step of forming an insulating layer 113 on the sidewall of the tsv recess to increase the interference of the optical signal between the adjacent back-illuminated avalanche photodiodes, thereby improving the performance of the device.

The insulating layer 113 may be made of an oxide material, such as silicon dioxide.

When the isolation structure 112 includes the insulating layer 113 and the second conductive material, the isolation structure is not only used for performing optical isolation between adjacent back-illuminated avalanche photodiodes, but also used for further achieving electrical isolation between adjacent back-illuminated avalanche photodiodes.

A second wiring layer 104 is also formed on the through silicon via 103 to form an electrical connection with the back-illuminated avalanche photodiode to extract a signal of the back-illuminated avalanche photodiode.

The method for forming the second wiring layer 104 on the through silicon via 103 includes: step B1: a wiring material layer is formed on the epitaxial layer to completely cover the epitaxial layer 102 and the through silicon via 103, wherein the wiring material layer may be a metal material, such as, but not limited to, Al. In a specific embodiment of the present application, the wiring material layer may be formed by a deposition method.

Step B2: after the wiring material layer is formed, the wiring material layer is patterned to form a plurality of connection structures spaced apart from each other, thereby forming a second wiring layer 104 to electrically connect the through-silicon via 103 and the back-illuminated avalanche photodiode array, respectively.

A passivation layer 105 is also formed on the second wiring layer 104, and the passivation layer 105 covers the second wiring layer 104 and fills gaps between the second wiring layer 104.

A passivation layer opening is formed in the passivation layer 105 to expose the second wiring layer 104 for subsequent electrical connection to extract a signal of the back-illuminated avalanche photodiode.

Wherein the avalanche photodiode chip 10 further includes a support wafer 107, and the support wafer 107 is bonded to the second surface of the substrate 101. The support wafer 107 may be a wafer of transparent material to enable light to enter the back-illuminated avalanche photodiode through the support wafer 107. In an embodiment of the present application, the support wafer 107 may be a glass wafer.

The avalanche photodiode chip comprises a thinned substrate 101 in the preparation process, and when the avalanche photodiode chip is thinned, the substrate 101 is bonded with a transparent supporting wafer 107 through bonding (wafer bond) or resin (such as epoxy resin), so that the light transmittance is guaranteed, the strength of the whole chip is improved, the chip is prevented from being broken in the thinning process, and the yield is further improved.

The support wafer 107 and the substrate 101 may be bonded together by a resin adhesive.

The avalanche photodiode chip further includes a first connection bump 110 formed on the second wiring layer 104 to be electrically connected to the signal chip through the first connection bump 110.

The method of forming the first connection bump 110 includes:

step C1: forming a buffer material layer 108 on the passivation layer 105 and the second wiring layer 104 exposed by the opening to cover the passivation layer 105 while filling the opening;

step C2: then patterning the buffer material layer 108 to form an opening and expose the passivation layer opening and the second wiring layer 104 in the opening;

step C3: forming the first connection bump in the opening.

Optionally, the avalanche photodiode chip further includes a buffer material layer 108 on the passivation layer 105 and the second wiring layer 104 exposed by the opening to cover the passivation layer 105 while filling the opening.

Wherein an opening in the buffer material layer 108 exposes the passivation layer opening and the second wiring layer 104 in the opening, and the first connection bump 110 is formed in the opening.

The buffer material layer 108 may be a Polyimide (Polyimide) material, and the buffer material layer 108 may be formed by a spin coating method. The buffer material layer 108 may play a role in buffering during the subsequent formation of the first connection bump 110, so as to prevent damage to the second wiring layer 104 or the substrate 101.

A buffer material layer 108 is deposited between the connection bump 110 and the epitaxial layer 102, so as to buffer the stress on the connection bump 110 in a vibration or impact scene, thereby improving the reliability of interconnection between the connection bump 110 and the epitaxial layer 102.

An Under Bump Metal (UBM) layer 109 is further formed in the opening to cover the opening, and the first connection bump 110 is formed on the under bump metal layer 109.

The Under Bump Metal (UBM) 109 may include at least one of a copper (Cu) layer, a tin (Sn) layer, and a nickel (Ni) layer. In an embodiment of the present application, the Under Bump Metal (UBM) 109 is a copper (Cu) layer.

The first connection bump 110 includes a first copper pillar, wherein a projection of the first copper pillar on a horizontal plane may be a cylindrical structure of a circle, a square, a polygon, or the like.

A pad layer 111 is also formed on the upper surface of the first connection bump 110 for subsequent bonding between chips.

Wherein, the distance between the first connection bump 110 located at the edge region of the substrate 101 and the adjacent first connection bump 110 is greater than the distance between the adjacent first connection bumps 110 located at the center region of the substrate 101, so as to prevent the high voltage difference between the two sides from being great.

The solder joint layer is a material that can be melted and soldered, such as but not limited to a tin (Sn) layer, and the solder joint layer uniformly covers the first connection bump 110.

As shown in fig. 2, the signal processing chip 20 includes a plurality of signal processing units and a plurality of second connection bumps 204, and the second connection bumps 204 are electrically connected to the signal processing units.

The signal processing chip 20 includes a central region and an edge region, wherein an array of the second connection bumps 204 is formed in the central region, and a solder pad layer 206 is further formed on the upper surfaces of the second connection bumps 204 for bonding between subsequent chips. Connection pads are formed at the edge regions.

The manufacturing process of the signal processing chip 20 is based on the conventional CMOS process, the second connection bump 204 is formed only on a partial region of the signal processing chip 20, a connection pad, such as an aluminum pad, is arranged around the second connection bump 204, and no connection bump is provided, and the connection pad is used as an output/output lead during packaging and is led to a package pin through a lead bonding.

The Hybrid bond chip (Hybrid bond chip) in which the connection pads and the second connection bumps 204 are simultaneously located on the same signal processing chip 20 can realize that the central second connection bump 204 is interconnected with the first connection bump 110, and the connection pads around the periphery lead out output/output (I/O) to the package pins by wire bonding.

The avalanche photodiode chip is configured to receive the optical pulse sequence reflected by the detected object, and convert the received optical pulse sequence into a current signal;

the signal processing unit includes:

a trans-group amplifier for converting the current signal into a voltage signal;

a comparator for comparing the voltage signal with a preset voltage threshold;

and the time-to-digital converter is used for outputting a time signal according to the comparison result of the comparator.

In an embodiment of the present application, the signal processing unit is integrated with a plurality of circuits, and in an embodiment of the present application, for example, the signal processing unit is integrated with a transimpedance amplifier circuit (TIA circuit), a multi-stage operational amplifier OPA, a comparator, and a time-to-digital converter (circuit that converts time into a digital signal) or an analog-to-digital conversion circuit (ADC circuit), and a subsequent data processing circuit (DSP circuit). The TIA circuit is an analog front-stage circuit for converting APD photocurrent into voltage.

When the back-illuminated avalanche photodiodes convert optical signals into current signals, external high-voltage power supply is needed, and the APD can provide stable internal gain, improve the signal-to-noise ratio and output the current signals.

In the signal processing unit, the TIA circuit is electrically connected with the back-illuminated avalanche photodiode, converts a current signal of the APD into a voltage signal and provides conversion gain; and the multi-stage operational amplifier OPA is electrically connected with the TIA circuit and used for amplifying the signal output by the TIA circuit so as to meet the comparison amplitude requirement of the comparator. The comparator is electrically connected with the multi-stage operational amplifier OPA, wherein a comparison threshold is set in the comparator to trigger the analog signal, the analog signal is converted into a digital signal, and the signal is transmitted to the TDC circuit, and the TDC circuit is used for converting the digital signal into a time signal and calculating the distance. The signal processing unit can be further provided with a storage system for caching data, providing an input/output cache space for an interface and providing a space for internal calculation. For the plurality of signal processing units, one TDC circuit may be shared, that is, the number of signal processing units and the number of TDC circuits may not correspond to each other.

An interface can be further arranged in the signal processing unit to be used as a data input and output channel for outputting the measurement data.

In an embodiment of the present application, a first input terminal of the comparator is configured to receive an electrical signal input from the trans-group amplifier, that is, an electrical signal after an amplification operation, a second input terminal of the comparator is configured to receive a preset threshold, and an output terminal of the comparator is configured to output a result of the comparison operation, where the result of the comparison operation includes time information corresponding to the electrical signal. It will be appreciated that the predetermined threshold received at the second input of the comparator may be an electrical signal having a strength of the predetermined threshold. The result of the comparison operation may be a digital signal corresponding to the amplified electrical signal.

Optionally, the Time-to-Digital Converter (TDC) is electrically connected to an output end of the comparator, and is configured to extract Time information corresponding to the electrical signal according to a comparison operation result output by the comparator.

The signal processing chip 20 is described in detail below with reference to the accompanying drawings, and as shown in fig. 2, the signal processing chip 20 includes a substrate 201, and the substrate 201 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others.

Wherein, each circuit in the signal processing unit is formed in the substrate 201, and a first wiring layer 202 is formed on the surface of the substrate 201 to be electrically connected with each circuit in the signal processing unit so as to lead out the signal of each circuit in the signal processing unit.

The method for forming the first wiring layer 202 includes: a wiring material layer is formed on the substrate 201, wherein the wiring material layer may be a metal material, such as metal Al, but is not limited to Al. In a specific embodiment of the present application, the wiring material layer may be formed by a deposition method.

After the wiring material layer is formed, the wiring material layer is patterned to form a plurality of connection structures spaced apart from each other, thereby forming the first wiring layer 202.

A second passivation layer 203 is further formed on the first wiring layer 202, and the second passivation layer 203 covers the first wiring layer 202 and fills gaps between the first wiring layer 202.

A passivation layer opening is formed in the second passivation layer 203 and exposes the first wiring layer 202 for subsequent electrical connection, leading out signals of each circuit in the signal processing unit.

Optionally, the signal processing chip further includes a second buffer material layer 207 on the second passivation layer 203 and the first wiring layer 202 exposed by the opening, wherein the second buffer material layer 207 has an opening and exposes the passivation layer opening and the first wiring layer 202 in the opening, and the second connection bump 204 is formed in the opening.

The second buffer material layer 207 may be a Polyimide (Polyimide) material, and the second buffer material layer 207 may be formed by a spin coating method. The second buffer material layer 207 can play a role of buffering in the subsequent process of forming the second connection bump 204, so as to prevent damage to the first wiring layer 202 or the substrate 201.

A second Under Bump Metal (UBM) 205 is further formed in the opening to cover the opening, and the second connection bump 204 is formed on the second under bump metal 205.

The second Under Bump Metal (UBM) 205 may include at least one of a copper (Cu) layer, a tin (Sn) layer, and a nickel (Ni) layer. In an embodiment of the present application, the second Under Bump Metal (UBM) layer 205 is a copper (Cu) layer.

The second connecting bump 204 includes a second copper pillar, wherein a projection of the second copper pillar on a horizontal plane may be a cylindrical structure with a circular shape, a square shape, a polygonal shape, or the like.

A solder joint layer 206 is also formed on the upper surface of the second connection bump 204 for subsequent bonding between chips.

The distance between the second connecting bump 204 located at the edge region of the substrate 201 and the adjacent second connecting bump 204 is greater than the distance between the adjacent second connecting bumps 204 located at the central region of the substrate 201, so as to prevent the high voltage difference between the two sides from being great.

The method for integrating the avalanche photodiode chip 10 and the signal processing chip 20 in the receiving chip is described in detail with reference to fig. 3A to 3D.

In an example of the present application, as shown in fig. 3A, in this example, the first connection bump 110 in the avalanche photodiode chip 10 and the second connection bump 204 in the signal processing chip 20 are aligned and connected to each other up and down to integrate the avalanche photodiode chip 10 and the signal processing chip 20 as one body, while achieving electrical connection of the avalanche photodiodes corresponding up and down to the signal processing unit.

Specifically, in an embodiment of the present application, the pad layer 111 on the first connection bump 110 and the pad layer 206 on the second connection bump 204 connect the first connection bump 110 and the second connection bump 204 to each other by soldering.

Specifically, in an embodiment of the present application, the implementation flow of the packaging process of the receiving chip includes the following steps:

providing a wafer containing the avalanche photodiode chips 10, wherein the wafer comprises a plurality of rows and columns of avalanche photodiode chips 10, and then cutting the wafer to form single chips (single chips) containing avalanche photodiode arrays;

providing a wafer containing the signal processing chip 20, bonding a single chip of the diced avalanche photodiode array onto the wafer of the signal processing chip 20, specifically bonding the avalanche photodiode chip 10 and the signal processing chip 20 together by connecting the first connection bump 110 and the second connection bump 204 to each other up and down;

a cleaning step is then performed to clean the surface of the bonded device of various impurities to avoid damage to the avalanche photodiode array or the signal processing chip 20.

After the cleaning step is performed, underfill is filled between the avalanche photodiode chip 10 and the signal processing chip 10, and the underfill is cured to seal the gap.

The bonded device is then diced to yield a plurality of individual single chips containing the avalanche photodiode array and signal processing chip 20.

And finally packaging the cut single chip containing the avalanche photodiode array and the signal processing chip 20: in the packaging process, the second surface of the signal processing chip 20 is attached to the bottom plate of the package housing in the receiving chip, wherein a pin 302 is further disposed on the bottom plate, and the pin is electrically connected to the first wiring layer 202 in the signal processing chip 20, so as to lead out signals in the avalanche photodiode chip 10 and the signal processing chip 20; and sealing the top plate to form a closed accommodating space, wherein at least part of the top plate is a light-transmitting area.

The package housing in the receiving chip is explained in detail below. The receiving chip includes a substrate 301 and a cover 303 to form the receiving space around.

In an embodiment of the present application, the substrate 301 has a groove structure, and the cover 303 has a plate structure.

The base plate comprises a bottom plate positioned at the bottom and side plates positioned on the bottom plate, and the bottom plate and the side plates jointly enclose to form the groove structure.

The bottom plate can be various types of substrates such as a Printed Circuit Board (PCB) substrate, a ceramic substrate and the like, wherein the PCB is manufactured by different components and parts and various complex process technologies, the PCB has a single-layer structure, a double-layer structure and a multi-layer structure, and the manufacturing modes of different hierarchical structures are different.

Alternatively, the printed circuit board is primarily comprised of pads, vias, mounting holes, wires, components, connectors, fills, electrical boundaries, and the like.

Further, common board Layer structures of printed circuit boards include three types, namely a Single Layer board (Single Layer PCB), a Double Layer board (Double Layer PCB) and a Multi Layer board (Multi Layer PCB), and specific structures thereof are as follows:

(1) single-layer board: i.e. a circuit board with only one side copper-clad and the other side not copper-clad. Typically, the components are placed on the side that is not copper-clad, the copper-clad side being used primarily for wiring and soldering.

(2) Double-layer plate: i.e., a circuit board with both sides copper-clad, is commonly referred to as a Top Layer (Top Layer) on one side and a Bottom Layer (Bottom Layer) on the other side. The top layer is generally used as the surface for placing components, and the bottom layer is used as the surface for welding components.

(3) Multilayer board: that is, a circuit board including a plurality of working layers includes a plurality of intermediate layers in addition to a top layer and a bottom layer, and the intermediate layers can be used as a conductive layer, a signal layer, a power layer, a ground layer, etc. The layers are insulated from each other and the connections between the layers are usually made by vias.

The printed circuit board includes many types of working layers, such as a signal layer, a protective layer, a silk-screen layer, an internal layer, and so on, which are not described herein again.

In addition, the base plate may be a ceramic substrate in the present application, and the ceramic substrate refers to a copper foil directly bonded to alumina (Al) at a high temperature₂O ₃) Or a special process plate on the surface (single or double side) of an aluminum nitride (AlN) ceramic substrate. The manufactured ultrathin composite substrate has excellent electrical insulation performance, high heat conduction characteristic, excellent soft solderability and high adhesion strength, can be etched into various patterns like a PCB (printed circuit board), and has great current carrying capacity.

The bottom plate is further provided with a pin 302, and the pin is electrically connected with the first wiring layer 202 in the signal processing chip 20, so as to lead out signals in the avalanche photodiode chip 10 and the signal processing chip 20.

Specifically, as shown in fig. 3A to 3B and fig. 3D, in the packaging process, the second surface of the signal processing chip 20 is attached to the bottom plate.

Further, in an embodiment of the present application, a sealant is further formed in the accommodating space to cover and fix the receiving chip. The sealant can be a waterproof adhesive.

As shown in fig. 3A to 3D, at least a partial region of the top plate is a light-transmitting region.

The top plate may be made of a commonly used transparent material, such as glass, which must have high light transmittance.

Alternatively, the top plate may be a plate-shaped structure with all light transmission, and may also be a metal flat plate with a glass window.

Alternatively, the signal processing chip 20 is disposed on the substrate, and the connection pad on the edge of the signal processing chip 20 or the connection pad on the edge of the interposer 30 disposed between the avalanche photodiode chip 10 and the signal processing chip 20 is electrically connected to the pin 302 of the substrate.

In an embodiment of the present application, the material of the substrate 301 is an epoxy glass cloth laminate or a BT resin substrate material. The BT resin is a thermosetting resin formed by using Bismaleimide (BMI) and triazine as main resin components and adding an epoxy resin, a polyphenylene ether resin (PPE), an allyl compound, or the like as a modifying component, and is referred to as a BT resin.

Wherein the thermal expansion coefficient of the epoxy glass cloth laminated board or BT resin substrate material is 8 multiplied by 10^-6/℃～15×10 ^-6/℃。

Wherein the thermal expansion coefficient of the avalanche photodiode chip 10 and the signal processing chip 20 is 8 × 10^-6/℃。

A stress buffer layer 304 is further disposed between the bottom plate of the substrate 301 and the signal processing chip 20, as shown in fig. 3C, wherein the stress buffer layer 304 has a thermal expansion coefficient of 3 × 10^-6/℃～7×10 ^-6/℃。

The thermal expansion coefficient of the stress buffer layer 304 is between that of the bottom plate of the substrate 301 and that of the signal processing chip 20, and the stress buffer layer 304 has the characteristic of high mechanical strength, so that warpage caused by mismatching of the thermal expansion Coefficients (CTE) between the bottom plate of the substrate 301 and the signal processing chip 20 in the process of product application or reliable tests such as TCT (high-low temperature cycle) and other temperature changes can be avoided through the arrangement of the stress buffer layer 304, the warpage which is aggravated by air cold and heat shrinkage in the cavity package of the tube shell can be avoided, stress caused by the warpage to Bump (Bump) interconnecting the TIA/TDC chip and the APD array chip can be eliminated, Bump cracking can be eliminated, and the yield of the whole device can be improved.

Optionally, the stress buffer layer comprises glass, aluminum nitride ceramic, aluminum oxide ceramic, and copper molybdenum copper.

providing a wafer containing the signal processing chip 20, bonding the single chip of the diced avalanche photodiode array to the wafer of the signal processing chip 20, specifically bonding the avalanche photodiode chip 10 and the signal processing chip 20 together by the above-mentioned first connection bump 110 and the second connection bump 204 being connected to each other up and down;

The stress buffer layer 304 is bonded to the substrate by epoxy.

Bonding the cut single chip containing the avalanche photodiode array and the signal processing chip 20 to the stress buffer layer 304 integrally; the stress buffer layer 304 is attached to a bottom plate of a package housing in the receiving chip, and a pin 302 is further disposed on the bottom plate, and the pin is electrically connected to the first wiring layer 202 in the signal processing chip 20, so as to lead out signals in the avalanche photodiode chip 10 and the signal processing chip 20;

and finally, sealing through a top plate to form a closed accommodating space, wherein at least part of the top plate is a light-transmitting area.

Other integration methods of the avalanche photodiode chip 10 and the signal processing chip 20 in the present application are described below, it should be noted that the same parts of the following embodiment as those of the embodiment shown in fig. 3A are not repeated, and reference may be made to the embodiment shown in fig. 3A, and only the differences from the embodiment shown in fig. 3A will be described in detail below.

In an embodiment of the present application, in which the second connection bump is not provided in the signal processing chip 20, but a metal pad 207 is provided, as shown in fig. 3B, the metal pad 207 is formed on the first wiring layer 202 in the signal processing chip 20 to lead out the electrical signals of each circuit in the signal processing chip 20.

The metal pad 207 may be made of a metal material, for example, the metal pad 207 is made of metal gold, but is not limited to the material.

Optionally, a diffusion barrier layer is further disposed below the metal pad 207, and is used to prevent the metal pad 207 from diffusing downward, which affects each circuit in the signal processing chip 20. The diffusion barrier layer may be one or more layers, for example including one or more of a nickel (Ni) layer, a platinum layer.

In an embodiment of the present application, a nickel (Ni) layer is disposed under the metal pad 207.

In another embodiment of the present application, a platinum (pt) layer and a nickel (Ni) layer are sequentially disposed under the metal pad 207.

In the integration of the avalanche photodiode chip 10 and the signal processing chip 20, the first connection bump 110 in the avalanche photodiode chip 10 and the metal pad 207 in the signal processing chip 20 are aligned and connected to each other up and down to integrate the avalanche photodiode chip 10 and the signal processing chip 20 together, while achieving the electrical connection of the avalanche photodiode corresponding up and down to the signal processing unit.

Specifically, in this embodiment, the implementation flow of the packaging process of the receiving chip includes the following steps:

providing a wafer containing the signal processing chip 20, bonding the single chip of the cut avalanche photodiode array to the wafer of the signal processing chip 20, specifically bonding the avalanche photodiode chip 10 and the signal processing chip 20 together by the above-mentioned first connection bump 110 and the metal pad 207 being connected to each other up and down;

And finally packaging the cut single chip containing the avalanche photodiode array and the signal processing chip 20: in the packaging process, the signal processing chip 20 is attached to a bottom plate of a packaging shell in the receiving chip, wherein a pin 302 is further arranged on the bottom plate, and the pin is electrically connected with the first wiring layer 202 in the signal processing chip 20, so that signals in the avalanche photodiode chip 10 and the signal processing chip 20 are led out; and finally, sealing through a top plate to form a closed accommodating space, wherein at least part of the top plate is a light-transmitting area.

In another embodiment of the present application, as shown in fig. 3C, the receiving chip further includes an interposer 30 disposed between the avalanche photodiode chip 10 and the signal processing chip 20, the interposer 30 includes a first surface and a second surface disposed oppositely, the first surface of the interposer 30 is electrically connected to the avalanche photodiode chip, and the second surface of the interposer 30 is electrically connected to the signal processing chip.

The interposer 30 is a through silicon via interposer (TSV interposer), and specifically, the interposer 30 includes a through silicon via interconnection structure 306 penetrating through a first surface and a second surface of the interposer, wherein a conductive layer 305 is further disposed on the first surface and the second surface of the interposer 30, and the conductive layer is electrically connected to the through silicon via interconnection structure.

The interposer 30 may be made of silicon material or ceramic material, and the thickness thereof is 200-500 μm.

Wherein the first connection bump 110 and the second connection bump 204 are electrically connected to the conductive layer 305 of the first surface and the second surface of the interposer, respectively, so as to realize the electrical connection between the avalanche photodiode chip 10 and the signal processing chip 20.

The conductive layer 305 may be one or more of Ni, Pt, and Au. In an example of the present application, a conductive layer of Ni-Pt-Au or a conductive layer of Ni-Au is sequentially formed on the upper and lower surfaces of the through silicon via interconnection structure 306 from inside to outside.

Further, the interposer 30 is further provided with a connection pad for leading out a signal in the avalanche photodiode chip 10 to a package pin of the receiving chip.

The first surface and the second surface of the interposer 30 are both flat structures to perform double-sided Flip chip (Flip chip) bonding with the avalanche photodiode chip 10 and the signal processing chip 20, respectively, and the interposer 30 maintains a flat surface to prevent the first connection bump 110 and the second connection bump 204 from interfering during double-sided packaging.

Further, in the present application, the integration of the avalanche photodiode chip 10 and the signal processing chip 20 through the interposer 30 can realize the decoupling of the high voltage signal on the avalanche photodiode chip 10 and the signal processing chip 20, the high voltage signal on the avalanche photodiode chip 10 is led from the interposer 30 to the connection pad on the interposer 30 through the conductive layer routing and led out the package pin through the bonding wire (wire bond), and does not need to pass through the signal processing chip 20, and the signal processing chip 20 does not need to consider extra customized high voltage design rules to avoid the interference and breakdown risk of HV (high voltage) signals to normal signals through the connection mode signal processing chip 20.

Alternatively, the material for manufacturing the interposer 30 includes, but is not limited to, silicon or ceramic.

Further, an underfill is disposed between the avalanche photodiode chip 10 and the signal processing chip 10 to fill and seal a gap between the avalanche photodiode chip 10 and the signal processing chip 10, thereby playing a role in protection.

When the avalanche photodiode chip 10 and the signal processing chip 10 are connected by the interposer 30, underfill is disposed between the avalanche photodiode chip 10 and the interposer 30 and between the signal processing chip 10 and the interposer 30 to seal gaps between the interposer 30 and the first connection bumps 110 and the second connection bumps 204.

The underfill may be selected from a common insulating glue or a bonding glue, which is not listed here.

providing a wafer containing the avalanche photodiode chips 10, wherein the wafer comprises a plurality of rows and columns of avalanche photodiode chips 10, and then cutting the wafer to form single chips (single chips) containing avalanche photodiode arrays; similarly, the wafer following the signal processing chip 20 is cut into single chips of the signal processing chip 20.

The avalanche photodiode chip 10 is electrically connected to the interposer 30, and specifically, the avalanche photodiode chip 10 is soldered to the conductive layer 305 on the first surface of the interposer 30.

And filling underfill between the avalanche photodiode chip 10 and the interposer 30, and curing the underfill to seal the gap.

The interposer 30 is turned over so that the second surface faces upward, and then the second surface of the interposer 30 and the signal processing chip 20 are bonded together, for example, the second connection bumps 204 of the signal processing chip 20 are soldered to the conductive layer 305 on the second surface of the interposer 30.

And filling underfill between the signal processing chip 20 and the interposer 30, and curing the underfill to seal the gap.

Packaging the structure of the avalanche photodiode chip 10, the adapter plate 30 and the signal processing chip 20 which are bonded into a whole: in the packaging process, the second surface of the signal processing chip 20 is attached to the bottom plate of the package housing in the receiving chip, wherein a pin 302 is further disposed on the bottom plate, and the pin is electrically connected to the first wiring layer 202 in the signal processing chip 20, so as to lead out signals in the avalanche photodiode chip 10 and the signal processing chip 20; and finally, sealing through a top plate to form a closed accommodating space, wherein at least part of the top plate is a light-transmitting area.

The second aspect of this application still provides a range unit, and the receiving chip that this application each embodiment provided can be applied to range unit, and this range unit can be electronic equipment such as laser radar, laser rangefinder. In one embodiment, the ranging device is used to sense external environmental information, such as distance information, orientation information, reflected intensity information, velocity information, etc. of environmental targets. In one implementation, the ranging device may detect the distance of the probe to the ranging device by measuring the Time of Flight (TOF), which is the Time-of-Flight Time, of light traveling between the ranging device and the probe. Alternatively, the distance measuring device may detect the distance from the probe to the distance measuring device by other techniques, such as a distance measuring method based on phase shift (phase shift) measurement or a distance measuring method based on frequency shift (frequency shift) measurement, which is not limited herein.

For ease of understanding, the following describes the operation flow of ranging by the ranging apparatus as an example.

The ranging device may include a transmitting circuit, a receiving chip, and an arithmetic circuit. Wherein, the receiving chip comprises the avalanche photodiode chip and the signal processing chip.

In the signal processing chip, for the signal processing unit, each signal processing unit may be separately provided with a transimpedance amplifier circuit (TIA circuit), wherein the time-to-digital converter (TDC) may be separately provided, and a plurality of TIA circuits may share one time-to-digital converter (TDC), and during sharing, the time-to-digital converter (TDC) may be switched to different channels to receive and process signals of the TIA circuits.

The arithmetic circuit may be provided separately or one arithmetic circuit may be shared by a plurality of signal processing units.

The transmit circuit may transmit a sequence of light pulses (e.g., a sequence of laser pulses). The receiving chip can receive the optical pulse sequence emitted by the optical transmitting circuit and reflected by the detected object, and output a time signal based on the received optical pulse sequence. The arithmetic circuitry may determine a distance between the ranging device and the detected object based on the time signal.

Optionally, the distance measuring apparatus may further include a control circuit, and the control circuit may implement control of other circuits, for example, may control an operating time of each circuit and/or perform parameter setting on each circuit, and the like.

The distance and the direction detected by the distance measuring device can be used for remote sensing, obstacle avoidance, mapping, modeling, navigation and the like. In one embodiment, the distance measuring device of the embodiment of the present invention may be applied to the movable platform.

Based on the above, the invention also provides a movable platform, wherein the distance measuring device can be applied to the movable platform, and the distance measuring device can be arranged on the movable platform body of the movable platform.

In certain embodiments, the movable platform comprises at least one of an unmanned aerial vehicle, an automobile, a remote control car, a robot, a camera. When the distance measuring device is applied to the unmanned aerial vehicle, the movable platform body is a fuselage of the unmanned aerial vehicle. When the distance measuring device is applied to an automobile, the movable platform body is the automobile body of the automobile. The vehicle may be an autonomous vehicle or a semi-autonomous vehicle, without limitation. When the distance measuring device is applied to the remote control car, the movable platform body is the car body of the remote control car. When the distance measuring device is applied to a robot, the movable platform body is the body of the robot. When the distance measuring device is applied to a camera, the movable platform body is a camera body.

In some embodiments, the movable platform may further include a power system for driving the movable platform body to move. For example, when the movable platform is a vehicle, the power system may be an engine inside the vehicle, which is not listed here.

Although the example embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the above-described example embodiments are merely illustrative and are not intended to limit the scope of the present application thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present application. All such changes and modifications are intended to be included within the scope of the present application as claimed in the appended claims.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the technical solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described device embodiments are merely illustrative, and for example, the division of the units is only one logical functional division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another device, or some features may be omitted, or not executed.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Similarly, it should be appreciated that in the description of exemplary embodiments of the present application, various features of the present application are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the application and aiding in the understanding of one or more of the various inventive aspects. However, the method of the present application should not be construed to reflect the intent: this application is intended to cover such departures from the present disclosure as come within known or customary practice in the art to which this invention pertains. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this application.

It will be understood by those skilled in the art that all of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where such features are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the application and form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.

The various component embodiments of the present application may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art will appreciate that a microprocessor or Digital Signal Processor (DSP) may be used in practice to implement some or all of the functionality of some of the modules according to embodiments of the present application. The present application may also be embodied as apparatus programs (e.g., computer programs and computer program products) for performing a portion or all of the methods described herein. Such programs implementing the present application may be stored on a computer readable medium or may be in the form of one or more signals. Such a signal may be downloaded from an internet website or provided on a carrier signal or in any other form.

It should be noted that the above-mentioned embodiments illustrate rather than limit the application, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The application may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.

The above description is only for the specific embodiments of the present application or the description thereof, and the protection scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope disclosed in the present application, and shall be covered by the protection scope of the present application. The protection scope of the present application shall be subject to the protection scope of the claims.

Claims

A receiving chip, comprising:

an avalanche photodiode chip comprising a plurality of back-illuminated avalanche photodiodes and a plurality of first connection bumps electrically connected to the back-illuminated avalanche photodiodes;

the signal processing chip comprises a plurality of signal processing units and a plurality of second connecting bumps, and the second connecting bumps are electrically connected with the signal processing units;

the avalanche photodiodes corresponding to each other up and down are connected with the signal processing unit through the first connecting bumps and the second connecting bumps.
The receiving chip of claim 1, wherein the first connection bump comprises a first copper pillar;

the second connection bump includes a second copper pillar.
The receiving chip according to claim 2, wherein a solder pad layer is formed on the first connection bump and/or the second connection bump.
The receiving chip of claim 1, wherein the receiving chip further comprises an interposer disposed between the avalanche photodiode chip and the signal processing chip and electrically connected to the avalanche photodiode chip and the signal processing chip, respectively.
The receiving chip of claim 4, wherein the interposer comprises through-silicon via interconnection structures penetrating through upper and lower surfaces of the interposer and conductive layers located on the upper and lower surfaces of the interposer and electrically connected to the through-silicon via interconnection structures;

the first connecting bump and the second connecting bump are electrically connected with the conductive layers on the upper surface and the lower surface of the adapter plate respectively.
The receiving chip of claim 5, wherein the sidewalls of the through silicon via interconnect structure are vertical.
The receiving chip as claimed in claim 4, wherein the edge of the interposer is further formed with connection pads.
The receiving chip according to claim 4, wherein the interposer is made of a material including silicon or ceramic.
The receiving chip according to claim 1, wherein a first wiring layer is further formed on the signal processing chip and disposed between the second connection bump and the signal processing unit.
The receiving chip according to claim 1, wherein the edge of the signal processing chip is further formed with a connection pad.
The receiving chip as claimed in claim 1, wherein an underfill is further disposed in the gap between the avalanche photodiode chip and the signal processing chip.
The receiving chip according to any of the preceding claims 1 to 11, wherein the receiving chip further comprises a substrate and a lid, wherein the lid is disposed on the substrate, and a space for accommodating the avalanche photodiode chip and the signal processing chip is disposed between the substrate and the lid.
The receiving chip as claimed in claim 12, wherein the signal processing chip is disposed on the substrate, and the connection pad of the edge of the signal processing chip or the connection pad of the edge of the interposer disposed between the avalanche photodiode chip and the signal processing chip is electrically connected to the lead of the substrate.
The receiving chip as recited in claim 12, wherein the substrate has a groove structure and the cover has a plate structure.
The receiving chip according to claim 12, wherein at least a portion of the cover is an optically transparent region.
The receiving chip according to claim 12, wherein the material of the cover body comprises metal, resin, or ceramic; and/or

The substrate comprises a printed circuit board substrate or a ceramic substrate.
The receiving chip of claim 12, wherein the substrate is made of epoxy glass cloth laminate or BT resin substrate material.
The receiving chip according to claim 17, wherein a stress buffer layer is disposed on the substrate, and the signal processing chip is disposed on the stress buffer layer.
The receiver chip of claim 18, wherein the stress buffer layer has a thermal expansion coefficient of 3 x 10^-6/℃～7×10 ^-6/℃。
The receiving chip of claim 18, wherein the stress buffer layer comprises glass, aluminum nitride ceramic, aluminum oxide ceramic, and copper molybdenum copper.
The receiving chip according to any of the preceding claims, wherein the avalanche photodiode chip comprises:

a heavily doped substrate comprising a first surface and a second surface disposed opposite one another;

an epitaxial layer disposed on the first surface;

a back-illuminated avalanche photodiode array disposed in the epitaxial layer;

the silicon through hole penetrates through the epitaxial layer and the substrate, and the side wall of the silicon through hole is vertical;

and the wiring layer is arranged on the silicon through hole.
The receiving chip of claim 21, the avalanche photodiode chip further comprising:

and the connecting bump is arranged on the wiring layer.
The receiving chip as recited in claim 22, wherein a distance between the connection bump located at the edge region of the substrate and an adjacent connection bump is greater than a distance between the adjacent connection bumps located at the center region of the substrate.
The receiving chip of claim 21, wherein the back-illuminated avalanche photodiode array comprises a plurality of back-illuminated avalanche photodiodes, and wherein an isolation structure is formed between adjacent back-illuminated avalanche photodiodes.
The receiving chip of claim 24, wherein the isolation structure comprises an isolation recess and a conductive material in the isolation recess.
The receiving chip of claim 25, the isolation structure further comprising an insulating layer on a surface of the isolation groove, the conductive material being formed on the insulating layer.
The receiver chip of claim 21, wherein the wiring layer has a passivation layer formed thereon with an opening exposing a portion of the wiring layer.
The receiving chip of claim 21, wherein a support wafer is attached to the second surface, the support wafer being bonded to the second surface.
The receiving chip of claim 28, wherein the support wafer comprises a glass wafer.
The receiver chip according to claim 21, wherein a buffer layer having an opening is formed on the wiring layer, the opening exposing a portion of the wiring layer;

the connection bump is formed on the wiring layer exposed from the opening.
The receiving chip as recited in claim 30, wherein an under bump metallurgy layer is further disposed between the wiring layer and the connection bump.
The receiving chip of claim 21, wherein the connection bump comprises a copper pillar.
The receiver chip of claim 21, wherein a pad layer is formed on the connection bump.
A ranging apparatus, comprising:

an optical transmission circuit for emitting a sequence of optical pulses;

the receiving chip of one of claims 1 to 33, configured to receive an optical pulse train emitted by the optical transmitting circuit and reflected by an object to be detected, and output a time signal based on the received optical pulse train;

and the arithmetic circuit is used for calculating the distance between the detected object and the distance measuring device according to the time signal.
A movable platform, comprising:

a movable platform body;

a ranging device as claimed in claim 34 wherein the ranging device is provided on the moveable platform body.
The movable platform of claim 35, wherein the movable platform comprises a drone, an autonomous automobile, or a robot.