CN202231013U - Silicone-free through hole low cost image sensor packaging structure - Google Patents
Silicone-free through hole low cost image sensor packaging structure Download PDFInfo
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- CN202231013U CN202231013U CN2011203711810U CN201120371181U CN202231013U CN 202231013 U CN202231013 U CN 202231013U CN 2011203711810 U CN2011203711810 U CN 2011203711810U CN 201120371181 U CN201120371181 U CN 201120371181U CN 202231013 U CN202231013 U CN 202231013U
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Abstract
The utility model relates to a silicone-free through hole low cost image sensor packaging structure, comprising a chip body(1) of which the upper surface is equipped with an isolation layer(5). A transparent cover plate (6) is arranged on the isolation layer, a silicon groove (8) is formed on the chip body, and an insulating layer(9) is selectivity arranged on the lower surface of the chip body, the side wall of the silicon groove (8) and the lower surface of a chip interior passivation layer(2); through holes(10) are formed on the chip interior passivation layer(2) and a chip interior metal layer(3), a metal circuit layer(11) is selectively formed on the surface of the insulating layer(9) and in the through holes(10), a circuit protection layer(12) is selectively arranged on the insulating layer(9) and the metal circuit layer(11), and a solder ball (13) is arranged at the position of the metal circuit layer(11) extending out the circuit protection layer(12). The utility model provides the silicone-free through hole low cost image sensor packaging structure having the characteristics of simple structure, good interconnection reliability, simple process and low cost.
Description
Technical field
The utility model relates to a kind of wafer level image sensor package structure.Belong to the semiconductor packaging field.
Background technology
Imageing sensor is to convert external optical signals to the signal of telecommunication, and institute's signal of telecommunication that obtains is through handling the semiconductor device that can finally form images.The wafer level image sensor package is novel image sensor package mode, closes encapsulation and compares than conventional wire is strong, has that package dimension is little, a photosensitive area advantage such as pollution not when low price and downstream assembling, is receiving increasing concern.Because the chip electrode of imageing sensor or chip internal metal level and photosensitive area all are positioned at chip front side; So wafer-level packaging just need give over to photosensitive window with chip front side; And the chip internal metal level is redistributed chip back from chip front side, to realize with extraneous interconnected.
Realize that this positive back side is shifted and to pass through silicon through hole (Through Silicon Via) interconnected method.The silicon through hole is interconnected promptly to utilize diameter that the method for dry etching forms silicon through hole, silicon through hole on the silicon body of chip back about 100um, and the degree of depth is about 100um.Comprise that to exposing silicon the silicon in body and the hole carries out the insulating processing then, and need leave interconnected window in the bottom, hole so that follow-up filling metal contacts with the formation of chip internal metal level.Then need in the hole, fill metal, and redistribution metallic circuit layer.This wafer level image sensor package mode is interconnected owing to having introduced the silicon through hole, makes encapsulating structure complicated; And that is that all right is ripe for silicon through hole interconnection technique; Often, cause this type to utilize the interconnected wafer level image sensor package of carrying out of silicon through hole to have the low problem of big, the interconnected reliability of technology difficulty because imperfect and metal filled unreal the causing of bad, the interconnected window that insulate in the hole lost efficacy or reliability is bad.Simultaneously, the interconnected process complexity of silicon through hole also causes adopting this technological wafer level image sensor package price comparison expensive.
Summary of the invention
The purpose of the utility model is to overcome the deficiency of current wafer level image sensor package mode, provide have simple in structure, interconnected good reliability, technology simply, the low-cost image sensor package structure of the no silicon through hole of characteristics cheaply.
The purpose of the utility model is achieved in that the low-cost image sensor package structure of a kind of no silicon through hole; Comprise the chip body that is provided with chip internal passivation layer, chip internal metal level and photosensitive area; Upper surface at the chip body is provided with separator, and separator does not cover or be covered in the chip photosensitive area; Euphotic cover plate is set on separator, when separator is not covered in the chip photosensitive area, forms cavity between euphotic cover plate, separator and the chip body; On the chip body, form silicon trench, and directly stop at the lower surface of chip internal passivation layer bottom the silicon trench, make chip internal passivation layer lower surface expose out; Lower surface at chip body lower surface, silicon trench sidewall and the chip internal passivation layer that exposes optionally is provided with insulating barrier; On chip internal passivation layer and chip internal metal level, form through hole, and through hole stops at separator inside; In surface of insulating layer and through hole, optionally form the metallic circuit layer; On insulating barrier and metallic circuit layer, the route protection layer is set optionally; The place of exposing the route protection layer at the metallic circuit layer is provided with soldered ball.
The utility model does not have the low-cost image sensor package structure of silicon through hole, and said insulating barrier is at the reserved window at the interconnected place of needs, and the reserved window size is greater than follow-up through hole size.
The utility model does not have the low-cost image sensor package structure of silicon through hole, and when said separator covered photosensitive area, separator was selected light transmissive material for use.
The beneficial effect of the utility model is:
(1), realizes that through the method that forms filling wiring in insulating barrier, through hole and the hole chip signal of telecommunication transfers to chip back from chip front side then through forming silicon trench and stopping at the surface of chip internal passivation layer; Compare with the silicon through hole is interconnected, structure is simple relatively; And because the channel bottom size that forms is big and the chip internal passivation layer thickness is thinner, the filling wiring technology difficulty reduces in follow-up through hole and the hole, has avoided owing to the metal filled unreal bad problem of reliability that causes in the silicon through hole.
(2) insulating barrier forms through the method for photoetching, insulating barrier attaching surface relatively flat, and technology is fairly simple; And insulating barrier is at the reserved window at the interconnected place of needs, and the reserved window size is greater than follow-up through hole size, and this can reduce the stress of the formation because insulating barrier and chip internal passivation layer thermal coefficient of expansion (CTE) do not match.
(3) owing to avoid adopting silicon through hole interconnection technique, packaging technology is simplified, and packaging cost reduces.
Description of drawings
Fig. 1 does not have the tangent plane sketch map of the low-cost image sensor package structure of silicon through hole for the utility model, and diagram separator 5 is not covered in photosensitive area 4, thereby forms cavity 7.
Fig. 2 does not have the tangent plane sketch map of the low-cost image sensor package structure of silicon through hole for the utility model, and separator 5 is covered in photosensitive area 4 in the diagram.Preferably, euphotic cover plate is an optical glass.
Fig. 3 does not have the low-cost image sensor package structure of silicon through hole interconnect portion tangent plane sketch map for the utility model.
Reference numeral among the figure:
Embodiment
Referring to Fig. 1 and Fig. 3, Fig. 1 does not have the tangent plane sketch map of the low-cost image sensor package structure of silicon through hole (band cavity type) for the utility model.Fig. 3 does not have the low-cost image sensor package structure of silicon through hole interconnect portion tangent plane sketch map for the utility model.Can find out by Fig. 1 and Fig. 3; The utility model does not have the low-cost image sensor package structure of silicon through hole; Comprise the chip body 1 that is provided with chip internal passivation layer 2, chip internal metal level 3 and photosensitive area 4; Chip internal passivation layer, chip internal metal level and photosensitive area all are structures that image sensor chip itself has, and do not belong to the encapsulation category that the utility model patent relates to.Upper surface at chip body 1 is provided with separator 5, and separator 5 does not cover chip photosensitive area 4.Euphotic cover plate 6 is set on separator 5.Form cavity 7 between euphotic cover plate 6, separator 5 and the chip body 1.On chip body 1, form silicon trench 8, and silicon trench 8 bottoms directly stop at the lower surface of chip internal passivation layer 2, make chip internal passivation layer 2 lower surfaces expose out.Depend on that this body structure of chip, chip internal passivation layer thickness are usually less than 5 μ m.Lower surface at chip body 1 lower surface, silicon trench 8 sidewalls and the chip internal passivation layer 2 that exposes optionally is provided with insulating barrier 9.On chip internal passivation layer 2 and chip internal metal level 3, form through hole 10, and through hole 10 stops at separator 5 inside.Because the chip internal passivation layer of imageing sensor and chip internal metal level be multilayer normally, thus preferably in this encapsulating structure through hole run through inner passivation layer of multilayer chiop and chip internal metal level.In insulating barrier 9 surfaces and through hole 10, optionally form metallic circuit layer 11, thereby the electric signal of chip is redistributed chip back from the chip internal metal level.On insulating barrier 9 and metallic circuit layer 11, route protection layer 12 is set optionally.The place of exposing route protection layer 12 at metallic circuit layer 11 is provided with soldered ball 13.
Said insulating barrier 9 is at the reserved window at the interconnected place of needs, and the reserved window size is greater than follow-up through hole size, to reduce because insulating barrier and chip internal passivation layer thermal coefficient of expansion (CTE) do not match the stress of formation.
Fig. 2 does not have the tangent plane sketch map of the low-cost image sensor package structure of silicon through hole (not with cavity type) for the utility model.Than Fig. 1, the difference of Fig. 2 is that separator 5 is covered in photosensitive area 4, thereby does not form cavity 7.When separator 5 covered photosensitive area 4, separator 5 was selected light transmissive material for use.
Claims (3)
1. low-cost image sensor package structure of no silicon through hole; Comprise the chip body (1) that is provided with chip internal passivation layer (2), chip internal metal level (3) and photosensitive area (4); It is characterized in that: the upper surface at chip body (1) is provided with separator (5), and separator (5) does not cover or be covered in chip photosensitive area (4); Euphotic cover plate (6) is set on separator (5), when separator (5) is not covered in chip photosensitive area (4), forms cavity (7) between euphotic cover plate (6), separator (5) and the chip body (1); Go up formation silicon trench (8) at chip body (1), and directly stop at the lower surface of chip internal passivation layer (2) bottom the silicon trench (8), make chip internal passivation layer (2) lower surface expose out; Lower surface at chip body (1) lower surface, silicon trench (8) sidewall and the chip internal passivation layer (2) that exposes optionally is provided with insulating barrier (9); Go up formation through hole (10) at chip internal passivation layer (2) and chip internal metal level (3), and through hole (10) stops at separator (5) inside; In insulating barrier (9) surface and through hole (10), optionally form metallic circuit layer (11); On insulating barrier (9) and metallic circuit layer (11), route protection layer (12) is set optionally; The place of exposing route protection layer (12) at metallic circuit layer (11) is provided with soldered ball (13).
2. the low-cost image sensor package structure of a kind of no silicon through hole according to claim 1, it is characterized in that: said insulating barrier (9) is at the reserved window at the interconnected place of needs, and the reserved window size is greater than follow-up through hole size.
3. the low-cost image sensor package structure of a kind of no silicon through hole according to claim 1, it is characterized in that: when said separator (5) covered photosensitive area (4), separator (5) was selected light transmissive material for use.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011203711810U CN202231013U (en) | 2011-10-08 | 2011-10-08 | Silicone-free through hole low cost image sensor packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011203711810U CN202231013U (en) | 2011-10-08 | 2011-10-08 | Silicone-free through hole low cost image sensor packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202231013U true CN202231013U (en) | 2012-05-23 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011203711810U Expired - Lifetime CN202231013U (en) | 2011-10-08 | 2011-10-08 | Silicone-free through hole low cost image sensor packaging structure |
Country Status (1)
| Country | Link |
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| CN (1) | CN202231013U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102339843A (en) * | 2011-10-08 | 2012-02-01 | 江阴长电先进封装有限公司 | TSV (Through Silicon Via)-free high-reliability image sensor encapsulation structure |
| CN104409422A (en) * | 2014-11-23 | 2015-03-11 | 北京工业大学 | Low-thickness and low-cost chip size package with cavity |
-
2011
- 2011-10-08 CN CN2011203711810U patent/CN202231013U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102339843A (en) * | 2011-10-08 | 2012-02-01 | 江阴长电先进封装有限公司 | TSV (Through Silicon Via)-free high-reliability image sensor encapsulation structure |
| CN104409422A (en) * | 2014-11-23 | 2015-03-11 | 北京工业大学 | Low-thickness and low-cost chip size package with cavity |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20120523 |