CN114554729A - Manufacturing method of circuit board and circuit board - Google Patents
Manufacturing method of circuit board and circuit board Download PDFInfo
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- CN114554729A CN114554729A CN202011354807.7A CN202011354807A CN114554729A CN 114554729 A CN114554729 A CN 114554729A CN 202011354807 A CN202011354807 A CN 202011354807A CN 114554729 A CN114554729 A CN 114554729A
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- bump
- dielectric layer
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 111
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 47
- 229910052802 copper Inorganic materials 0.000 claims abstract description 47
- 239000010949 copper Substances 0.000 claims abstract description 47
- 238000003466 welding Methods 0.000 claims abstract description 29
- 238000003825 pressing Methods 0.000 claims abstract description 11
- 230000004907 flux Effects 0.000 claims abstract description 8
- 229910000679 solder Inorganic materials 0.000 claims description 39
- 238000000034 method Methods 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 155
- 229920000106 Liquid crystal polymer Polymers 0.000 description 6
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 6
- 239000004642 Polyimide Substances 0.000 description 5
- 230000000149 penetrating effect Effects 0.000 description 5
- 229920001721 polyimide Polymers 0.000 description 5
- 239000012790 adhesive layer Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000004810 polytetrafluoroethylene Substances 0.000 description 4
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 230000002349 favourable effect Effects 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- -1 Polytetrafluoroethylene Polymers 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 230000008093 supporting effect Effects 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000009194 climbing Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
A manufacturing method of a circuit board comprises the following steps: providing a first circuit substrate, wherein the first circuit substrate comprises a first copper layer, a first dielectric layer and a convex welding pad which are overlapped along a first direction, the convex welding pad comprises a first convex block and a second convex block, the second convex block is arranged on the surface of the first convex block, which deviates from the first dielectric layer, and the width of the first convex block is larger than that of the second convex block along a second direction which is vertical to the first direction; connecting the electronic element on the convex welding pad through the welding flux; providing a first film, the first film having a first opening; providing a second circuit substrate which comprises a second dielectric layer and a second copper layer; sequentially stacking and pressing a first circuit substrate, a first film and a second circuit substrate which are connected with electronic elements along a first direction, wherein the electronic elements are accommodated in the first opening, and the first copper layer and the second copper layer are arranged away from the electronic elements; and respectively manufacturing the first copper layer and the second copper layer to form a first outer layer circuit layer and a second outer layer circuit layer. The application also provides a circuit board.
Description
Technical Field
The present disclosure relates to the field of circuit boards, and particularly to a method for manufacturing a circuit board and a circuit board.
Background
With the increasing demand of people for various electronic products such as computers, consumer electronics, communications, and the like, the functions of the electronic products are diversified, and the packaging structures in the electronic products are more and more concentrated, for example, a plurality of electronic components are embedded in a multilayer circuit board to shorten the connection path between the electronic components and reduce the signal transmission loss.
In the process of embedding the electronic component, solder paste is usually used to electrically connect the electronic component with the bonding pad on the circuit layer, and then the adhesive layer and the circuit layer are laminated through a layer-adding step, wherein the space around the electronic component is filled with the adhesive layer, so as to embed the electronic component in the circuit board.
However, in the pressing process, due to the limitation of the fluidity of the adhesive layer, gaps formed between the electronic component and the circuit layer, between the solder paste and the electronic component, and the like are not easily soaked and filled by the adhesive layer, so that air bubbles are formed, the electronic component is in poor contact with the circuit layer, and the quality of the circuit board is affected.
Disclosure of Invention
In view of the above, it is desirable to provide a method for manufacturing a circuit board that prevents bubbles from being generated around the periphery of the electronic component.
In addition, it is also necessary to provide a circuit board manufactured by the above manufacturing method.
A manufacturing method of a circuit board comprises the following steps:
providing a first circuit substrate, which comprises a first copper layer, a first dielectric layer and at least two convex welding pads, wherein the first copper layer, the first dielectric layer and the at least two convex welding pads are stacked along a first direction, the convex welding pads comprise a first lug and a second lug, the first lug is connected with the first dielectric layer, the second lug is arranged on the surface of the first lug, which deviates from the first dielectric layer, and the width of the first lug is greater than that of the second lug along a second direction perpendicular to the first direction;
connecting an electronic element on the convex welding pad through welding flux;
providing a first film, the first film having a first opening;
providing a second circuit substrate which comprises a second dielectric layer and a second copper layer positioned on one surface of the second dielectric layer;
the first circuit substrate, the first film and the second circuit substrate which are connected with the electronic element are sequentially stacked along the first direction and are pressed, wherein the electronic element is contained in the first opening, and the first copper layer and the second copper layer are arranged to be deviated from the electronic element; and
and respectively manufacturing the first copper layer and the second copper layer to form a first outer layer circuit layer and a second outer layer circuit layer so as to form the circuit board.
Further, the step of forming the first wiring substrate includes:
providing a double-sided copper-clad plate, wherein the double-sided copper-clad plate comprises a first dielectric layer and first copper layers positioned on two opposite surfaces of the first dielectric layer;
etching one of the first copper layers to form a circuit layer, wherein the circuit layer comprises the first bump; and
and forming the second bump on the first bump to obtain the first circuit substrate with the convex pad.
Further, along the first direction, a thickness of the second bump ranges from 10 μm to 30 μm; a width of the second bump in the second direction ranges greater than or equal to 50 μm; the distance from the side edge of the second bump to the side edge of the first bump is greater than or equal to 50 μm toward the other side of the convex pad.
Further, before the first circuit board, the first prepreg, and the second circuit board are stacked, the method further includes the steps of:
providing a third circuit substrate, wherein the third circuit substrate comprises an inner-layer dielectric layer and inner-layer circuit layers which are positioned on two opposite surfaces of the inner-layer dielectric layer and are electrically connected with each other, and the third circuit substrate comprises a second opening which penetrates through the inner-layer dielectric layer and the inner-layer circuit layers; and
providing a second film;
when the step of establishing first circuit substrate, first film and second circuit substrate superposes, still include:
and laminating the third circuit substrate and the second circuit substrate between the first film and the second circuit substrate, wherein the first opening and the second opening are communicated to form an accommodating space, and the electronic element is positioned in the accommodating space.
Furthermore, the first circuit substrate further comprises a slot, and the slot is located between two adjacent convex welding pads and penetrates through the first copper layer and the first dielectric layer; after the pressing step, the first film fills the slot.
A circuit board comprises a first circuit substrate, a welding flux, an electronic element, a first film and a second circuit substrate, wherein the first circuit substrate comprises a first outer layer circuit layer, a first dielectric layer and at least two convex welding pads which are overlapped along a first direction, the convex welding pads comprise first convex blocks and second convex blocks, the first convex blocks are connected with the first dielectric layer, the second convex blocks are arranged on the surfaces, deviating from the first dielectric layer, of the first convex blocks, and the width of the first convex blocks is larger than that of the second convex blocks along a second direction perpendicular to the first direction; the solder is positioned on the surface of the first bump, which is deviated from the first medium layer, and covers the second bump; the electronic component is positioned on one side of the solder, which is far away from the first circuit substrate, and is connected with the solder; the first film is positioned on one side of the first circuit substrate, which is far away from the first outer layer circuit layer, and surrounds the periphery of the electronic element; the second circuit substrate comprises a second dielectric layer and a second outer layer circuit layer, the second circuit substrate is located on the surface of the first film and covers the electronic element, and the second outer layer circuit layer is located on the surface, away from the electronic element, of the second dielectric layer.
Further, along the first direction, a thickness of the second bump ranges from 10 μm to 30 μm; a width of the second bump in the second direction ranges greater than or equal to 50 μm; the distance from the side edge of the second bump to the side edge of the first bump is greater than or equal to 50 μm toward the other side of the convex pad.
Further, the electronic component includes a pin, the pin being connected with the solder; the distance from the pin to the second bump along the first direction is 5-20 μm; facing to one side of the other convex pad along the second direction, wherein the distance from the side edge of the pin to the side edge of the first bump is-30 μm-30 μm; and the distance from the side edge of the pin to the side edge of the first bump is 0-150 μm away from the other convex pad.
Further, the circuit board further includes:
the third circuit substrate comprises an inner-layer dielectric layer and inner-layer circuit layers which are positioned on two opposite surfaces of the inner-layer dielectric layer and are electrically connected with each other, and the third circuit substrate is positioned between the first film and the second circuit substrate and surrounds the periphery of the electronic element; and
and a second prepreg positioned between the third circuit substrate and the second circuit substrate and covering the electronic component.
Further, the circuit board further comprises a solder mask layer, the solder mask layer is located between the first outer layer circuit layer and the second outer layer circuit layer, the first circuit substrate deviates from the surface of the electronic element, the slot is located between two adjacent convex welding pads, and the slot is filled with the first rubber sheet.
According to the manufacturing method of the circuit board, the convex welding pad is arranged on the first circuit substrate, in the process of connecting the electronic element through the welding flux, the welding flux climbs along the convex welding pad due to the wick effect to form the smooth side wall, in the process of subsequently laminating the first film, the first film can flow conveniently to fill the gaps at the periphery of the electronic element, bubbles are effectively avoided, and the yield of the circuit board is improved.
Drawings
Fig. 1A is a schematic cross-sectional view of a first circuit substrate according to an embodiment of the present disclosure.
Fig. 1B is a schematic cross-sectional view of a first circuit substrate according to another embodiment of the present disclosure.
Fig. 1C is a schematic cross-sectional view of a first circuit substrate according to still another embodiment of the present disclosure.
Fig. 2 is a schematic cross-sectional view of a double-sided copper-clad plate provided in an embodiment of the present application.
Fig. 3 is a cross-sectional view of the first copper layer of fig. 2 after forming a second bump thereon.
Fig. 4 is a schematic cross-sectional view of the second bump shown in fig. 3 covered with a dry film.
FIG. 5 is a cross-sectional view of the first circuit substrate with the bump pads formed after removing a portion of the first copper layer.
Fig. 6 is a schematic cross-sectional view of the convex pad shown in fig. 5 after a gold plating layer is formed on the surface.
Fig. 7 is a schematic cross-sectional view of the electronic component connected to the surface of the convex pad shown in fig. 1 by solder.
Fig. 8 is a schematic cross-sectional view of a first circuit substrate, a first prepreg, a third circuit substrate, a second prepreg, and a second circuit substrate to which an electronic component is connected according to an embodiment of the present application.
Fig. 9 is a schematic cross-sectional view of the first circuit substrate, the first prepreg, the third circuit substrate, the second prepreg, and the second circuit substrate connected with the electronic component shown in fig. 8 after being laminated.
Fig. 10 is a schematic cross-sectional view of the first copper layer and the second copper layer shown in fig. 9 after forming a first outer wiring layer and a second outer wiring layer, respectively.
Fig. 11 is a cross-sectional view of the first outer circuit layer and the second outer circuit layer shown in fig. 10 after solder masks are formed on the surfaces.
Description of the main elements
The following detailed description will further illustrate the present application in conjunction with the above-described figures.
Detailed Description
In order that the above objects, features and advantages of the present application can be more clearly understood, a detailed description of the present application will be given below with reference to the accompanying drawings and detailed description. In addition, the embodiments and features of the embodiments of the present application may be combined with each other without conflict. In the following description, numerous specific details are set forth to provide a thorough understanding of the present application, and the described embodiments are merely a subset of the embodiments of the present application, rather than all embodiments. All other embodiments obtained by a person of ordinary skill in the art without any inventive work based on the embodiments in the present application are within the scope of protection of the present application.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes all and any combination of one or more of the associated listed items.
In various embodiments of the present application, for convenience in description and not limitation, the term "coupled" as used in the specification and claims of the present application is not limited to physical or mechanical connections, either direct or indirect. "upper", "lower", "above", "below", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships are changed accordingly.
Referring to fig. 1A to 11, an embodiment of the present application provides a method for manufacturing a circuit board 100, including the following steps S1-S9:
step S1: referring to fig. 1A, a first circuit substrate 10 is provided, where the first circuit substrate 10 includes a first copper layer 11, a first dielectric layer 13, and a convex pad 15 sequentially stacked along a first direction L1, where the first copper layer 11 and the convex pad 15 are located on two opposite surfaces of the first dielectric layer 13.
The material of the first dielectric layer 13 may be one selected from Polyimide (PI), Liquid Crystal Polymer (LCP), Modified Polyimide (MPI), Epoxy Glass Cloth (FR 4/FR5), and the like.
The number of the convex pads 15 is at least two, each convex pad 15 includes a first bump 152 and a second bump 154, the first bump 152 is connected to the first dielectric layer 13, the second bump 154 is disposed on a surface of the first bump 152 facing away from the first dielectric layer 13, and a projection of the second bump 154 along the first direction L1 is located in a projection area of the first bump 152 along the first direction L1. A circuit layer (not shown) is further disposed on a surface of the convex pad 15, and the first bump 152 is a portion of the circuit layer.
A direction perpendicular to the first direction L1 and extending along the first circuit substrate 10 is defined as a second direction L2. The second direction L2 may be a direction along the length of the circuit board or a direction along the width of the circuit board, and in the present embodiment, the second direction L2 is a direction along the length of the circuit board.
Wherein, along the second direction L2, the width of the first bump 152 is greater than the width of the second bump 154.
Further, referring to fig. 1A again, the first circuit substrate 10 further includes a slot 18 penetrating the first circuit substrate 10 along the first direction L1, the slot 18 is located between two adjacent convex pads 15, and the slot 18 is configured to form an exhaust channel in a subsequent pressing process, which is favorable for exhausting gas.
Further, in other embodiments, the second protrusion 154 may also be a convex structure, i.e. have at least one boss (see fig. 1B), or a trapezoid (see fig. 1C).
In some embodiments, the step of forming the first circuit substrate 10 may include steps S11-S13:
step S11: referring to fig. 2, a double-sided copper-clad plate 16 is provided, wherein the double-sided copper-clad plate 16 includes the first dielectric layer 13 and the first copper layers 11 located on two opposite surfaces of the first dielectric layer 13.
Step S12: referring to fig. 3, the dry film 19 is covered on the surface of the first copper layer 11, the dry film 19 on the surface of one of the first copper layers 11 is exposed and developed to form a gap matching with the second bump 154, and the second bump 154 connected to the first copper layer 11 is formed in the gap.
Step S13: referring to fig. 4, a dry film 19 is covered again, and the dry film 19 covers the second bump 154.
Step S14: referring to fig. 5, exposing and developing to remove a portion of the first copper layer 11 located at the periphery of the second bump 154, forming the first bump 152 by the remaining portion of the first copper layer 11, forming the convex pad 15 by the first bump 152 and the second bump 154 together, and removing the remaining dry film 19 to obtain the first circuit substrate 10 having the convex pad 15.
Further, the step of forming the first circuit substrate 10 may further include a step of forming a slot 18 penetrating the first circuit substrate 10, and the step of forming the slot 18 may be by laser drilling or mechanical drilling.
Further, referring to fig. 6, the convex pad 15 may be subjected to a surface treatment, for example, a gold plating layer 17 is formed on the surface of the convex pad 15 to prevent the convex pad 15 from being oxidized.
Step S2: referring to fig. 7, an electronic component 30 is connected to the convex pad 15 by solder 20.
The electronic component 30 has pins 32 for electrical connection. The solder 20 is a metal paste, such as a solder paste, a silver paste, or the like, which plays a role of electrical conduction.
Specifically, an electronic component 30 is placed on the convex pad 15, the pins 32 are disposed corresponding to the second bumps 154, a liquid solder 20 is injected between the second bumps 154 and the pins 32, and then a reflow process is performed to solidify the solder 20. Due to the supporting effect of the first bump 152, the solder 20 can be prevented from overflowing to the first dielectric layer 13 between the adjacent convex pads 15, so that a narrow gap is prevented from being formed between the adjacent two convex pads 15 and the electronic component 30 by the solder 20, and the film is prevented from being difficult to fill to form bubbles in the subsequent support; in addition, during the reflow process, the solder 20 climbs towards the high temperature place due to the wicking effect, and the thermal conductivity of the lead 32 is greater than that of the convex pad 15, so that the temperature of the lead 32 rises rapidly, so that the solder 20 climbs towards the lead 32 along the second bump 154, and the solder 20 climbs and solidifies to form a smooth sidewall.
After the electronic component 30 is connected to the first circuit board 10, the slot 18 is located below the electronic component 30 and is communicated with an area below the electronic component 30.
Further, along the first direction L1, the thickness of the second bump 154 is a, where a is in a range of 10 μm ≦ a ≦ 30 μm, and the solder 20 may have a sufficient space to climb up during the reflow process; along the second direction L2, the width of the second bump 154 is b, and the range of b is more than or equal to 50 μm; facing one side of the other convex pad 15, the distance from the side of the second bump 154 to the side of the first bump 152 is c, the range of c is greater than or equal to 50 μm, and enough supporting space for the first bump 152 is reserved, so that the solder can be prevented from forming an inverted L shape or a semi-concave shape after climbing up, and the solder 20 can be prevented from overflowing from the first bump 152 to the space between two adjacent convex pads 15 to form a narrow gap.
After solidification, the solder 20 is located on the surface of the first bump 152 facing away from the first dielectric layer 13 and covers the second bump 154. Wherein, along the first direction L1, the distance from the lead 32 to the second bump 154 is d, and the range of d is 5 μm ≦ d ≦ 20 μm, so as to ensure that there is enough solder 20 connection between the electronic component 30 and the second bump 154 to ensure conductivity; facing to the other side of the convex pad 15 along the second direction L2, a distance e from the side of the pin 32 to the side of the first bump 152 is set, and the range of e is-30 μm ≦ e ≦ 30 μm, that is, the side of the pin 32 may protrude from the first bump 152, or may be located above the first bump 152, where the distance between the side of the pin 32 and the side of the first bump 152 is too large, so that a gap is easily formed on the side of the electronic component 30 facing to the first circuit board 10, which is not favorable for exhausting gas; the distance from the side of the pin 32 to the side of the first bump 152 is greater than or equal to f, where f is greater than or equal to 0 and less than or equal to 150 μm, so as to reserve enough space for mounting the electronic component 30.
In step S3, please refer to fig. 8, a first film 40 is provided, wherein the first film 40 has a first opening 42.
The material of the first film 40 may be one of insulating materials such as epoxy resin, Polytetrafluoroethylene (PTFE) and industrial Liquid Crystal Polymer (LCP), and the first film 40 and the pressing process have certain fluidity, and the first film 40 plays a role in insulation and adhesion.
The first opening 42 penetrates the first film 40 in a direction.
Step S4: referring to fig. 8 again, a third circuit substrate 50 is provided, in which the third circuit substrate 50 includes an inner dielectric layer 52 and inner circuit layers 54 disposed on opposite surfaces of the inner dielectric layer 52 and electrically connected to each other, and the third circuit substrate 50 includes a second opening 56 penetrating through the inner dielectric layer 52 and the inner circuit layers 54.
In the subsequent process, the first film 40 and the third circuit board 50 are stacked, and the first opening 42 and the second opening 56 are communicated to form a receiving space (not shown) for receiving the electronic component 30. It can be understood that the accommodating space formed by the first opening 42 communicating with the second opening 56 is adapted to the size of the electronic component 30.
Further, in some embodiments, the number of the circuit layers of the third circuit substrate 50 is not limited to two layers, and may be a plurality of circuit layers electrically connected to each other.
Step S5: referring again to fig. 8, a second film 60 is provided.
The material of the second film 60 may be one of insulating materials such as epoxy resin, Polytetrafluoroethylene (PTFE) and industrial Liquid Crystal Polymer (LCP), the second film 60 and the pressing process have certain fluidity, and the second film 60 plays a role in insulation and adhesion.
In some embodiments, the third circuit substrate 50 and the second prepreg 60 may be omitted, wherein the size of the first opening 42 of the first prepreg 40 is adapted to the size of the electronic component 30.
Step S6: referring to fig. 8 again, a second circuit substrate 70 is provided, wherein the second circuit substrate 70 includes a second dielectric layer 72 and a second copper layer 74, and the second copper layer 74 is disposed on a surface of the second dielectric layer 72.
In this embodiment, the second circuit substrate 70 is a single-sided copper-clad plate.
The material of the second dielectric layer 72 may be one selected from polyimide, liquid crystal high molecular polymer, modified polyimide, epoxy resin glass fiber cloth, and the like.
Step S7: referring to fig. 9, the first circuit board 10, the first film 40, the third circuit board 50, the second film 60 and the third circuit board 50 connected with the electronic component 30 are sequentially stacked and pressed, wherein the electronic component 30 is located in the accommodating space formed by the first opening 42 and the second opening 56, and the first copper layer 11 and the second copper layer 74 are respectively located on one side away from the electronic component 30.
Specifically, the first prepreg 40 connects the first circuit board 10 and the third circuit board 50, and the second prepreg 60 connects the third circuit board 50 and the second circuit board 70, wherein both the first copper layer 11 and the second copper layer 74 are outermost layers.
The first film 40 and the second film 60 are semi-cured films, and in the pressing process, the first film 40 and the second film 60 flow and are filled in gaps between the electronic component 30 and the first circuit board 10 and the third circuit board 50, wherein the gaps include a gap between the solder 20 and the electronic component 30, a gap between the electronic component 30 and the first circuit board 10, and a gap between the solder 20 and the first circuit board 10. It can be understood that by the provision of the convex pads 15, smooth sidewalls are formed after the solder 20 is solidified, which facilitates the sufficient flow of the first and second prepregs 40 and fills the gap during the bonding process, thereby preventing the generation of bubbles.
Further, after the first circuit board 10, the first prepreg 40, the third circuit board 50, the second prepreg 60 and the third circuit board 50 connected with the electronic component 30 are stacked, the slot 18 of the first circuit board 10 is communicated with the accommodating space formed by the first opening 42 and the second opening 56, so that in the pressing process, the air below the electronic component 30 can be discharged through the slot 18, and the first prepreg 40 and the second prepreg 60 can also flow to the slot 18 and fill the slot 18, thereby further solving the problem of air bubble residue.
Step S8: referring to fig. 10, the first copper layer 11 and the second copper layer 74 are respectively formed to form a first outer circuit layer 112 and a second outer circuit layer 742 connected to the inner circuit layer 54.
The step of forming the first outer layer circuit layer 112 and the second outer layer circuit layer 742 may be formed by etching, or may be formed by electroplating after etching.
Before the steps of forming the first outer-layer circuit layer 112 and the second outer-layer circuit layer 742, a conductive hole (not shown) penetrating through the first dielectric layer 13 and the first prepreg 40 and a conductive hole penetrating through the second dielectric layer 72 and the second prepreg 60 are formed, so that the conductive hole is filled with a conductive body 80 to electrically connect the first circuit substrate 10, the second circuit substrate 70 and the third circuit substrate 50.
In some embodiments, the step of forming the first and second copper layers 11 and 74 into the first and second outer circuit layers 112 and 742, respectively, may be performed before the step of pressing (i.e., step S8).
Step S9: referring to fig. 11, a solder mask 90 is covered on the first outer circuit layer 112 and the second outer circuit layer 742 to form the circuit board 100.
Referring to fig. 11 again, the present application further provides a circuit board 100 manufactured by the above manufacturing method, where the circuit board 100 includes a first circuit substrate 10, a first film 40, a third circuit substrate 50, a second film 60, a second circuit substrate 70 stacked in sequence along a first direction L1, and an electronic component 30 embedded between the first circuit substrate 10 and the second circuit substrate 70, where the first circuit substrate 10, the third circuit substrate 50, and the second circuit substrate 70 are electrically connected to each other, the first circuit substrate 10 includes a convex pad 15, and the electronic component 30 is connected to the first circuit substrate 10 through the convex pad and a solder 20 disposed on the convex pad 15.
The first circuit substrate 10 includes a first dielectric layer 13, a first outer circuit layer 112 and a convex pad 15, wherein the first outer circuit layer 112 and the convex pad 15 are located on two opposite surfaces of the first dielectric layer 13, the first outer circuit layer 112 is located on a surface of the first dielectric layer 13 facing away from the electronic component 30, and the first outer circuit layer 112 is electrically connected to the third circuit substrate 50.
The number of the convex pads 15 is at least two, each convex pad 15 includes a first bump 152 and a second bump 154, the first bump 152 is connected to the first dielectric layer 13, the second bump 154 is disposed on a surface of the first bump 152 facing away from the first dielectric layer 13, and the width of the first bump 152 is greater than the width of the second bump 154 along the second direction L2. The solder 20 is located on the surface of the first bump 152 facing away from the first dielectric layer 13 and covers the second bump 154.
Referring to fig. 7 again, along the first direction L1, the thickness of the second bump 154 is a, and a is in the range of 10 μm ≦ 30 μm; along the second direction L2, the width of the second bump 154 is b, and the range of b is more than or equal to 50 μm; the distance from the side of the second bump 154 to the side of the first bump 152 is c, which is in the range of c ≧ 50 μm, toward the side of the other one of the male pads 15. In the first direction L1, the distance from the lead 32 to the second bump 154 is d, and the range of d is 5 μm ≦ d ≦ 20 μm, so as to ensure that there is sufficient solder 20 connection between the electronic component 30 and the second bump 154 to ensure conductivity; facing to the other side of the convex pad 15 along the second direction L2, a distance e from the side of the pin 32 to the side of the first bump 152 is set, and the range of e is-30 μm ≦ e ≦ 30 μm, that is, the side of the pin 32 may protrude from the first bump 152, or may be located above the first bump 152, where the distance between the side of the pin 32 and the side of the first bump 152 is too large, so that a gap is easily formed on the side of the electronic component 30 facing to the first circuit board 10, which is not favorable for discharging bubbles; the distance from the side of the pin 32 to the side of the first bump 152 is f, where f is in the range of 0 ≦ f ≦ 150 μm, so as to reserve enough space for mounting the electronic component 30.
The solder 20 may be a solder paste, a silver paste, or the like.
The first film 40 is located on a side of the first circuit substrate 10 facing away from the first outer circuit layer 112 and surrounds the periphery of the electronic component 30, and it is understood that the first film 40 also fills gaps around the leads 32 of the electronic component 30.
Further, the first circuit substrate 10 further includes a slot 18, the slot 18 is located between two adjacent convex pads 15 and located below the electronic component 30, and the first adhesive sheet 40 fills the slot 18.
The third circuit substrate 50 includes an inner dielectric layer 52 and inner circuit layers 54 located on two opposite surfaces of the inner dielectric layer 52 and electrically connected to each other. In some embodiments, the number of the circuit layers of the third circuit substrate 50 is not limited to two layers, and may be a plurality of circuit layers electrically connected to each other.
The second film 60 is positioned on the surface of the first film 40 and covers the electronic component 30.
The second circuit substrate 70 includes a second dielectric layer 72 and a second outer circuit layer 742, the second outer circuit layer 742 is located on a surface of the second dielectric layer 72 facing away from the electronic component 30, and the second outer circuit layer 742 is electrically connected to the third circuit substrate 50.
In some embodiments, the third circuit board 50 and the second prepreg 60 may be omitted, and the thickness of the first prepreg 40 along the first direction L1 is adapted to the thickness of the electronic component 30.
The circuit board 100 further includes a solder mask 90 disposed on the first outer circuit layer 112 and the second outer circuit layer 742.
According to the manufacturing method of the circuit board 100, the convex welding pads 15 are arranged on the first circuit substrate 10, in the process of connecting the electronic element 30 through the welding flux 20, the welding flux 20 climbs along the convex welding pads 15 due to the wick effect to form a smooth side wall, and in the subsequent process of laminating the first film 40, the first film 40 can flow conveniently to fill the gaps at the periphery of the electronic element 30, so that bubbles are effectively avoided, and the yield of the circuit board 100 is improved.
Although the present application has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the spirit and scope of the present application.
Claims (10)
1. The manufacturing method of the circuit board is characterized by comprising the following steps:
providing a first circuit substrate, which comprises a first copper layer, a first dielectric layer and at least two convex welding pads, wherein the first copper layer, the first dielectric layer and the at least two convex welding pads are stacked along a first direction, the convex welding pads comprise a first lug and a second lug, the first lug is connected with the first dielectric layer, the second lug is arranged on the surface of the first lug, which deviates from the first dielectric layer, and the width of the first lug is greater than that of the second lug along a second direction perpendicular to the first direction;
connecting an electronic element on the convex welding pad through welding flux;
providing a first film, the first film having a first opening;
providing a second circuit substrate which comprises a second dielectric layer and a second copper layer positioned on one surface of the second dielectric layer;
sequentially stacking and connecting the first circuit substrate with the electronic element, the first film and the second circuit substrate along the first direction, and pressing, wherein the electronic element is accommodated in the first opening, and the first copper layer and the second copper layer are arranged away from the electronic element; and
and respectively manufacturing the first copper layer and the second copper layer to form a first outer layer circuit layer and a second outer layer circuit layer so as to form the circuit board.
2. The method of manufacturing a circuit board according to claim 1, wherein the step of forming the first circuit substrate includes:
providing a double-sided copper-clad plate, which comprises a first dielectric layer and first copper layers positioned on two opposite surfaces of the first dielectric layer;
etching one of the first copper layers to form a circuit layer, wherein the circuit layer comprises the first bump; and
and forming the second bump on the first bump to obtain the first circuit substrate with the convex pad.
3. The method for manufacturing a circuit board according to claim 1, wherein the thickness of the second bump along the first direction is in a range of 10 μm to 30 μm; a width of the second bump in the second direction ranges greater than or equal to 50 μm; the distance from the side edge of the second bump to the side edge of the first bump is greater than or equal to 50 μm toward the other side of the convex pad.
4. The method for manufacturing a circuit board according to claim 1, further comprising, before stacking the first circuit substrate, the first prepreg, and the second circuit substrate, the steps of:
providing a third circuit substrate, wherein the third circuit substrate comprises an inner-layer dielectric layer and inner-layer circuit layers which are positioned on two opposite surfaces of the inner-layer dielectric layer and are electrically connected with each other, and the third circuit substrate comprises a second opening which penetrates through the inner-layer dielectric layer and the inner-layer circuit layers; and
providing a second film;
when the step of establishing first circuit substrate, first film and second circuit substrate superposes, still include:
and laminating the third circuit substrate and the second circuit substrate between the first film and the second circuit substrate, wherein the first opening and the second opening are communicated to form an accommodating space, and the electronic element is positioned in the accommodating space.
5. The method of claim 1, wherein the first circuit substrate further comprises a slot, the slot is located between two adjacent convex pads and penetrates through the first copper layer and the first dielectric layer; after the pressing step, the first film fills the slot.
6. A circuit board, comprising:
the first circuit substrate comprises a first outer layer circuit layer, a first medium layer and at least two convex welding pads which are overlapped along a first direction, wherein each convex welding pad comprises a first lug and a second lug, the first lug is connected with the first medium layer, the second lug is arranged on the surface of the first lug, which deviates from the first medium layer, and the width of the first lug is greater than that of the second lug along a second direction which is perpendicular to the first direction;
the solder is positioned on the surface of the first bump, which is deviated from the first medium layer, and covers the second bump;
the electronic component is positioned on one side of the solder, which is far away from the first circuit substrate, and is connected with the solder;
the first film is positioned on one side of the first circuit substrate, which is far away from the first outer layer circuit layer, and surrounds the periphery of the electronic element; and
and the second circuit substrate comprises a second dielectric layer and a second outer layer circuit layer, the second circuit substrate is positioned on the surface of the first film and covers the electronic element, and the second outer layer circuit layer is positioned on the surface of the second dielectric layer, which deviates from the electronic element.
7. The circuit board of claim 6, wherein the second bump has a thickness in a range of 10 μ ι η -30 μ ι η along the first direction; a width of the second bump in the second direction ranges greater than or equal to 50 μm; the distance from the side edge of the second bump to the side edge of the first bump is greater than or equal to 50 μm toward the other side of the convex pad.
8. The circuit board of claim 7, wherein the electronic component comprises a pin, the pin being connected to the solder; the distance from the pin to the second bump is 5-20 μm along the first direction; facing to one side of the other convex pad along the second direction, wherein the distance from the side edge of the pin to the side edge of the first bump is-30 μm-30 μm; and the distance from the side edge of the pin to the side edge of the first bump is 0-150 μm at the side edge opposite to the other convex pad.
9. The circuit board of claim 6, further comprising:
the third circuit substrate comprises an inner-layer dielectric layer and inner-layer circuit layers which are positioned on two opposite surfaces of the inner-layer dielectric layer and are electrically connected with each other, and the third circuit substrate is positioned between the first film and the second circuit substrate and surrounds the periphery of the electronic element; and
and a second prepreg positioned between the third circuit substrate and the second circuit substrate and covering the electronic component.
10. The circuit board of claim 6, wherein the first circuit substrate further comprises a slot between two adjacent convex pads, and the first prepreg fills the slot.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011354807.7A CN114554729A (en) | 2020-11-27 | 2020-11-27 | Manufacturing method of circuit board and circuit board |
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| CN202011354807.7A CN114554729A (en) | 2020-11-27 | 2020-11-27 | Manufacturing method of circuit board and circuit board |
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