CN114553212A - Low-voltage-to-high-voltage level shift circuit with high-voltage power supply domain ground capable of floating - Google Patents
Low-voltage-to-high-voltage level shift circuit with high-voltage power supply domain ground capable of floating Download PDFInfo
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Abstract
The invention relates to a high-voltage to low-voltage level shift circuit with a high-voltage power supply domain capable of floating, which converts an input control signal of the high-voltage power supply domain into an output control signal of a low-voltage power supply domain and comprises a high-voltage power supply domain control circuit, a core conversion circuit and a low-voltage output shaping circuit; the high-voltage power supply domain control circuit carries out logic preprocessing on the input high-voltage domain control signal to control the core conversion circuit to work; the core conversion circuit converts the control input signals of the high-voltage power domains VBOOT-SW into the output control signals of the low-voltage power domains VIN-VSS, and the ground SW of the high-voltage power domain can float; the low-voltage output shaping circuit converts the signals with slow edge conversion output by the core conversion circuit into the rectangular pulse signals with steep edges by using the positive feedback effect in the conversion process of the Schmitt trigger. The low-voltage to high-voltage level shift circuit realizes the level shift function from a high-voltage power supply domain to a low-voltage power supply domain, and the high-voltage power supply domain can float and can be used in a multi-power supply system.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a high-voltage to low-voltage level shift circuit with a high-voltage power supply domain capable of floating.
Background
In a multi-power system, such as a motor driving circuit or a switching power management system, it is often seen that an output driving transistor of the multi-power system is a P-type MOS transistor rather than an N-type MOS transistor, because a high-voltage control input signal and a low-voltage control output signal of a commonly used high-voltage to low-voltage level shift circuit are grounded, and the ground of the high-voltage control input signal cannot float, there is a great limitation in application, so that the N-type MOS transistor has stronger driving capability and smaller on-resistance than the P-type MOS transistor under the same size, and the P-type MOS transistor is often used as the driving transistor in the conventional motor driving circuit or switching power management system.
Therefore, it is important to design a new level shift circuit, which can convert the high-voltage control signal of the high-voltage power domain into the control signal of the low-voltage power domain, and the ground of the high-voltage power domain can float, so that the high-voltage power domain can freely control the high-side N-type MOS driving transistor, and at the same time, can convert the high-voltage control signal of the high-voltage power domain into the control signal of the low-voltage power domain, so as to provide a feedback control signal for the low-side N-type MOS driving transistor.
Disclosure of Invention
Therefore, the technical problem to be solved by the invention is to overcome the problem that in the prior art, the high-voltage control input signal and the low-voltage control output signal of the level shift circuit are grounded in common, and the ground of the high-voltage output signal cannot float, so that in a multi-power system, a high-voltage driving signal drives a high-side N-type MOS driving tube and cannot provide a quick and accurate low-voltage feedback signal for a low-side N-type MOS driving tube at the same time, so that the N-type MOS driving tube is limited to be used in a motor driving circuit or a switching power management system, and thus, the high-voltage to low-voltage level shift circuit with the ground-floating high-voltage power supply domain is provided.
In order to solve the technical problem, the high-voltage to low-voltage level shift circuit with the high-voltage power supply domain capable of floating converts an input control signal of the high-voltage power supply domain into an output control signal of the low-voltage power supply domain, and comprises a high-voltage power supply domain control circuit, a core conversion circuit and a low-voltage output shaping circuit; the high-voltage power supply domain control circuit carries out logic preprocessing on the input high-voltage domain control signal to control the core conversion circuit to work; the core conversion circuit converts the control input signals of the high-voltage power domain VBOOT to SW into the output control signals of the low-voltage power domain VIN to VSS, and the ground SW of the high-voltage power domain can float; the low-voltage output shaping circuit utilizes the positive feedback effect in the conversion process of the Schmitt trigger to convert the signal with slow edge conversion output by the core conversion circuit into the rectangular pulse signal with steep edge, thereby improving the anti-interference performance of the post-stage circuit.
Optionally, the high-voltage to low-voltage level shift circuit with a floating high-voltage power domain is characterized in that the high-voltage power domain control circuit includes a high-voltage control main Input signal Ctr _ Logic _ Input, a first inverter INV1, and a second inverter INV 2;
the Input end of the first inverter INV1 is connected with a high-voltage control main Input signal Ctr _ Logic _ Input, and the output end of the first inverter INV1 is connected with the Input end of the second inverter INV2 and is connected to a core conversion circuit; the output end of the second inverter INV2 is connected to the core conversion circuit.
Optionally, the high-voltage to low-voltage level shift circuit with a floating high-voltage power domain ground is characterized in that the core conversion circuit includes a first current source I1, a first common high-voltage PMOS transistor HV _ P1, a second common high-voltage PMOS transistor HV _ P2, a first PLDMOS transistor PLD1, a second PLDMOS transistor PLD2, a first common low-voltage NMOS transistor LV _ N1, a second common low-voltage NMOS transistor LV _ N2, a third common low-voltage NMOS transistor LV _ N3, a fourth common low-voltage NMOS transistor LV _ N4, a fifth common low-voltage NMOS transistor LV _ N5, a sixth common low-voltage NMOS transistor LV _ N6, a first common low-voltage PMOS transistor LV _ P1, and a second common low-voltage PMOS transistor LV _ P2;
the positive end of the first current source I1 is connected with VBOOT of a high-voltage power domain, and the negative end of the first current source I1 is connected with the source end of a first common high-voltage PMOS (P-channel metal oxide semiconductor) transistor HV _ P1; the source end of the first common high-voltage PMOS tube HV _ P1 is connected with the negative end of a first current source I1; the grid end is connected with the output end of a second inverter INV2 of the high-voltage power domain control circuit, and the drain end is connected with the source end of a first PLDMOS tube PLD 1; the source end of the second common high-voltage PMOS tube HV _ P2 is connected with the source end of the first common high-voltage PMOS tube HV _ P1, the gate end of the second common high-voltage PMOS tube HV _ P2 is connected with the output end of the first inverter INV1 of the high-voltage power domain control circuit, and the drain end of the second common high-voltage PMOS tube HV _ P1 is connected with the source end of the second PLDMOS tube PLD 2.
Optionally, a source end of the first PLDMOS transistor PLD1 is connected to a drain end of the first common high-voltage PMOS transistor HV _ P1, a gate end of the first PLDMOS transistor PLD1 is connected to a floating ground SW of the high-voltage power domain, and a drain end of the first common low-voltage NMOS transistor LV _ N1 is connected to a drain end of the first common low-voltage NMOS transistor LV _ N3832; the source end of the second PLDMOS tube PLD2 is connected with the drain end of the second common high-voltage PMOS tube HV _ P2, the gate end of the second PLDMOS tube PLD1 is connected with the gate end of the first PLDMOS tube PLD1, and the drain end of the second PLDMOS tube PLD2 is connected with the drain end of the second common low-voltage NMOS tube LV _ N2.
Optionally, a drain end of the first common low-voltage NMOS transistor LV _ N1 is connected to a drain end of the first PLDMOS transistor PLD1, a gate end of the first common low-voltage NMOS transistor LV _ N1 is connected to a drain end of the second PLDMOS transistor PLD2, and a source end of the first common low-voltage NMOS transistor LV _ N1 is connected to a ground VSS of a low-voltage power domain; the drain end of the second common low-voltage NMOS tube LV _ N2 is connected with the drain end of the second PLDMOS tube PLD2, the gate end of the second common low-voltage NMOS tube LV _ N2 is connected with the drain end of the first PLDMOS tube PLD1, and the source end of the second common low-voltage NMOS tube LV _ N1 is connected with the source end of the first common low-voltage NMOS tube LV _ N1;
the drain end and the gate end of the third common low-voltage NMOS tube LV _ N3 are both connected with the drain end of the first common low-voltage NMOS tube LV _ N1, and the source end of the third common low-voltage NMOS tube LV _ N2 is connected with the source end of the second common low-voltage NMOS tube LV _ N2; the drain end of the fourth common low-voltage NMOS tube LV _ N4 is connected with the drain end of the first common low-voltage PMOS tube LV _ P1, the gate end of the fourth common low-voltage NMOS tube LV _ N4 is connected with the gate end of the third common low-voltage NMOS tube LV _ N3, and the source end of the fourth common low-voltage NMOS tube LV _ N3 is connected with the source end of the third common low-voltage NMOS tube LV _ N3;
the drain end and the gate end of the fifth common low-voltage NMOS tube LV _ N5 are both connected with the drain end of the second common low-voltage NMOS tube LV _ N2, and the source end of the fifth common low-voltage NMOS tube LV _ N4 is connected with the source end of the fourth common low-voltage NMOS tube LV _ N4; the drain end of the sixth common low-voltage NMOS tube LV _ N6 is connected with the drain end of the second common low-voltage PMOS tube LV _ P2, the gate end of the sixth common low-voltage NMOS tube LV _ N5 is connected with the gate end of the fifth common low-voltage NMOS tube LV _ N5, and the source end of the sixth common low-voltage NMOS tube LV _ N6 is connected with the source end of the fifth common low-voltage NMOS tube LV _ N5.
Optionally, the source end of the first common low-voltage PMOS transistor LV _ P1 is connected to the low-voltage power supply VIN end, and the gate end and the drain end of the first common low-voltage PMOS transistor LV _ P1 are both connected to the drain end of the fourth common low-voltage NMOS transistor LV _ N4; the source end of the second common low-voltage PMOS tube LV _ P2 is connected with the VIN end of a low-voltage power supply, the grid end of the second common low-voltage PMOS tube LV _ P2 is connected with the grid end of the first common low-voltage PMOS tube LV _ P1, and the drain end of the second common low-voltage PMOS tube LV _ P2 is connected with the input end of the low-voltage output shaping circuit.
Optionally, the low-voltage to high-voltage level shift circuit with a floating high-voltage power domain ground is characterized in that the low-voltage output shaping circuit includes a first schmitt trigger SMIT 1;
the input end of the first Schmitt trigger SMIT1 is connected with the drain end of a second common low-voltage PMOS tube LV _ P2 of the core conversion circuit, and the output end of the first Schmitt trigger SMIT1 is connected with OUT to drive a post-stage circuit.
In one embodiment of the present invention,
compared with the prior art, the technical scheme of the invention has the following advantages: the low-voltage to high-voltage level shift circuit with the floatable high-voltage power supply domain has a simple circuit structure, realizes the level shift function of converting the high-voltage power supply domain to the low-voltage power supply domain, can float the high-voltage power supply domain, and solves the application limitation caused by the fact that the high-voltage power supply domain and the low-voltage power supply domain of the traditional level shift circuit can only be grounded in a multi-power supply system; the control of adopting the N-type MOS tube as the driving tube circuit on the high side and the low side is easy to realize, the high-side P-type MOS driving tube in the traditional motor driving circuit or the switching power supply management system can be replaced by the N-type MOS driving tube, and the control circuit has obvious advantages in the aspects of reducing the chip area, improving the driving capability, reducing the production cost and the like.
Drawings
In order that the present disclosure may be more readily and clearly understood, reference will now be made in detail to the present disclosure, examples of which are illustrated in the accompanying drawings.
Fig. 1 is a schematic diagram of a high-voltage to low-voltage level shift circuit structure of the high-voltage power domain ground floatable provided by the invention.
Detailed Description
As shown in fig. 1, the present embodiment provides a high-voltage to low-voltage level shift circuit with a ground-floating high-voltage power domain, which is used for a multi-power system circuit, such as a motor driving circuit or a switching power management system, to convert an input control signal of the high-voltage power domain into an output control signal of the low-voltage power domain, and includes a high-voltage power domain control circuit, a core conversion circuit, and a low-voltage output shaping circuit; the high-voltage power supply domain control circuit carries out logic preprocessing on the input high-voltage domain control signal and controls the core conversion circuit to work; the core conversion circuit converts a control input signal of a high-voltage power domain (a floating ground signal SW-a high-voltage power signal VBOOT) into an output control signal of a low-voltage power domain (a ground signal VSS-a low-voltage power signal VIN), and the ground SW of the high-voltage power domain can float;
the low-voltage output shaping circuit utilizes the positive feedback effect in the conversion process of the Schmitt trigger to convert the signal with slow edge conversion output by the core conversion circuit into the rectangular pulse signal with steep edge, thereby improving the anti-interference performance of the post-stage circuit.
Further, as shown in fig. 1, the high voltage power domain control circuit includes a high voltage control main Input signal Ctr _ Logic _ Input, a first inverter INV1, a second inverter INV 2;
the Input end of the first inverter INV1 is connected with a high-voltage control main Input signal Ctr _ Logic _ Input, and the output end of the first inverter INV1 is connected with the Input end of the second inverter INV2 and is connected to the core conversion circuit; the output end of the second inverter INV2 is connected to the core conversion circuit.
The core conversion circuit comprises a first current source I1, a first common high-voltage PMOS tube HV _ P1, a second common high-voltage PMOS tube HV _ P2, a first PLDMOS tube PLD1, a second PLDMOS tube PLD2, a first common low-voltage NMOS tube LV _ N1, a second common low-voltage NMOS tube LV _ N2, a third common low-voltage NMOS tube LV _ N3, a fourth common low-voltage NMOS tube LV _ N4, a fifth common low-voltage NMOS tube LV _ N5, a sixth common low-voltage NMOS tube LV _ N6, a first common low-voltage PMOS tube LV _ P1 and a second common low-voltage PMOS tube LV _ P2;
the positive end of the first current source I1 is connected with VBOOT of a high-voltage power domain, and the negative end of the first current source I1 is connected with the source end of a first common high-voltage PMOS tube HV _ P1; the source end of the first common high-voltage PMOS tube HV _ P1 is connected with the negative end of a first current source I1; the grid end is connected with the output end of a second inverter INV2 of the high-voltage power domain control circuit, and the drain end is connected with the source end of a first PLDMOS tube PLD 1; the source end of the second common high-voltage PMOS tube HV _ P2 is connected with the source end of the first common high-voltage PMOS tube HV _ P1, the gate end of the second common high-voltage PMOS tube HV _ P2 is connected with the output end of the first inverter INV1 of the high-voltage power domain control circuit, and the drain end of the second common high-voltage PMOS tube HV _ P1 is connected with the source end of the second PLDMOS tube PLD 2.
The source end of the first PLDMOS tube PLD1 is connected with the drain end of a first common high-voltage PMOS tube HV _ P1, the gate end of the first PLDMOS tube PLD is connected with the floating ground SW of a high-voltage power domain, and the drain end of the first PLDMOS tube PLD is connected with the drain end of a first common low-voltage NMOS tube LV _ N1; the source end of the second PLDMOS tube PLD2 is connected with the drain end of the second common high-voltage PMOS tube HV _ P2, the gate end of the second PLDMOS tube PLD1 is connected with the gate end of the first PLDMOS tube PLD1, and the drain end of the second PLDMOS tube PLD2 is connected with the drain end of the second common low-voltage NMOS tube LV _ N2.
The drain end of the first common low-voltage NMOS tube LV _ N1 is connected with the drain end of the first PLDMOS tube PLD1, the gate end of the first common low-voltage NMOS tube LV _ N1 is connected with the drain end of the second PLDMOS tube PLD2, and the source end of the first common low-voltage NMOS tube LV _ N1 is connected with the ground VSS of a low-voltage power domain; the drain end of the second common low-voltage NMOS tube LV _ N2 is connected with the drain end of a second PLDMOS tube PLD2, the gate end of the second common low-voltage NMOS tube LV _ N2 is connected with the drain end of a first PLDMOS tube PLD1, and the source end of the second common low-voltage NMOS tube LV _ N1 is connected with the source end of the first common low-voltage NMOS tube LV _ N1;
the drain end and the gate end of the third common low-voltage NMOS tube LV _ N3 are both connected with the drain end of the first common low-voltage NMOS tube LV _ N1, and the source end of the third common low-voltage NMOS tube LV _ N2 is connected with the source end of the second common low-voltage NMOS tube LV _ N2; the drain end of the fourth common low-voltage NMOS tube LV _ N4 is connected with the drain end of the first common low-voltage PMOS tube LV _ P1, the gate end of the fourth common low-voltage NMOS tube LV _ N4 is connected with the gate end of the third common low-voltage NMOS tube LV _ N3, and the source end of the fourth common low-voltage NMOS tube LV _ N3 is connected with the source end of the third common low-voltage NMOS tube LV _ N3;
the drain end and the gate end of the fifth common low-voltage NMOS tube LV _ N5 are both connected with the drain end of the second common low-voltage NMOS tube LV _ N2, and the source end of the fifth common low-voltage NMOS tube LV _ N4 is connected with the source end of the fourth common low-voltage NMOS tube LV _ N4; the drain end of the sixth common low-voltage NMOS tube LV _ N6 is connected with the drain end of the second common low-voltage PMOS tube LV _ P2, the gate end of the sixth common low-voltage NMOS tube LV _ N5 is connected with the gate end of the fifth common low-voltage NMOS tube LV _ N5, and the source end of the sixth common low-voltage NMOS tube LV _ N6 is connected with the source end of the fifth common low-voltage NMOS tube LV _ N5.
The source end of the first common low-voltage PMOS tube LV _ P1 is connected with the VIN end of a low-voltage power supply, and the gate end and the drain end of the first common low-voltage PMOS tube LV _ P1 are both connected with the drain end of a fourth common low-voltage NMOS tube LV _ N4; the source end of the second common low-voltage PMOS tube LV _ P2 is connected with the VIN end of a low-voltage power supply, the grid end of the second common low-voltage PMOS tube LV _ P2 is connected with the grid end of the first common low-voltage PMOS tube LV _ P1, and the drain end of the second common low-voltage PMOS tube LV _ P2 is connected with the input end of the low-voltage output shaping circuit.
The low voltage output shaping circuit comprises a first schmitt trigger SMIT 1;
the input end of the first Schmitt trigger SMIT1 is connected with the drain end of a second common low-voltage PMOS tube LV _ P2 of the core conversion circuit, and the output end of the first Schmitt trigger SMIT1 is connected with OUT to drive a post-stage circuit.
The detailed working process of the invention is as follows:
as shown in fig. 1, when the high voltage control Input signal Ctr _ Logic _ Input inputted from the Input terminal of the first inverter INV1 in the high voltage power domain control circuit is low level 0, the output terminal of the first inverter INV1 outputs high level 1, the output terminal of the second inverter INV2 outputs low level 0, the first common high voltage PMOS HV _ P1 is turned on because the gate is connected to low level 0, and the second common high voltage PMOS HV _ P2 is turned off because the gates of the first and second PLDMOS PLD1 and PLD2 in the core conversion circuit are connected to the floating ground SW of the high voltage power domain and are in a normally on state. At the moment, a first current source I1 is connected with the first PLDMOS tube PLD1 through a first common high-voltage PMOS tube HV _ P1, the drain electrode of the first PLDMOS tube PLD is pulled up to a high potential, and source current is provided for a third common low-voltage NMOS tube LV _ N3 connected with the drain electrode of the first PLDMOS tube PLD 1; the third common low-voltage NMOS transistor LV _ N3 mirrors the current of the first current source I1 to the drain of the first common low-voltage PMOS transistor LV _ P1 through a current mirror structure formed by the fourth common low-voltage NMOS transistor LV _ N4, the first common low-voltage PMOS transistor LV _ P1 connected with the drain of the fourth common low-voltage NMOS transistor LV _ N4 provides current, the first common low-voltage PMOS transistor LV _ P1 mirrors the current of the first current source I1 to the drain of the second common low-voltage PMOS transistor LV _ P2 through the current mirror structure formed by the second common low-voltage PMOS transistor LV _ P2, and a pull-up effect is generated on the input end of the first Schmidt trigger SMIT 1;
meanwhile, as the grid electrode of the first common high-voltage PMOS tube HV _ P1 is connected with the low level 0 to be conducted, and the grid electrode of the second common high-voltage PMOS tube HV _ P2 is connected with the high level 1 to be disconnected, the potential of the drain terminal of the second common low-voltage NMOS tube LV _ N2 is pulled down to the low level 0 because the second common low-voltage NMOS tube LV _ N2 is conducted, and the fifth common low-voltage NMOS tube LV _ N5 and the sixth common low-voltage NMOS tube LV _ N6 which are connected with the drain terminal of the second common high-voltage PMOS tube PLD2 are connected with the low level 0 to be closed.
Therefore, a high-voltage control Input signal Ctr _ Logic _ Input by the high-voltage power domain is low level 0, and the low level 0 of the low-voltage power domain is output after the high-voltage power domain control signal Ctr _ Logic _ Input is preprocessed by the high-voltage power domain control circuit, converted by the core conversion circuit and shaped by the low-voltage output shaping circuit.
On the contrary, when the high-voltage control main Input signal Ctr _ Logic _ Input inputted from the Input terminal of the first inverter INV1 in the high-voltage power domain control circuit is at high level 1, the output terminal of the first inverter INV1 outputs low level 0, the output terminal of the second inverter INV2 outputs high level 1, the first common high-voltage PMOS transistor HV _ P1 is turned off because the gate is connected to high level 1, the second common high-voltage PMOS transistor HV _ P2 is turned on because the gate is connected to low level 0, and the gates of the first PLDMOS PLD1 and the second PLDMOS 2 in the core conversion circuit are in a normally on state because the gates are connected to the floating low SW of the high-voltage power domain. At the moment, the first current source I1 is connected with the second PLDMOS tube PLD2 through a second common high-voltage PMOS tube HV _ P2, the drain electrode of the second PLDMOS tube PLD2 is pulled to a high potential, and source current is provided for a fifth common low-voltage NMOS tube LV _ N5 connected with the drain electrode of the second PLDMOS tube PLD 2; the fifth common low-voltage NMOS transistor LV _ N5 generates a pull-down effect on the input end of the first Schmitt trigger SMIT1 through a current mirror structure formed by the fifth common low-voltage NMOS transistor LV _ N6;
meanwhile, as the grid electrode of the first common high-voltage PMOS tube HV _ P1 is turned off by being connected with a high level 1, and the grid electrode of the second common high-voltage PMOS tube HV _ P2 is turned on by being connected with a low level 0, the potential of the drain terminal of the first PLDMOS tube PLD1 is pulled down to the low level 0 due to the conduction of the first common low-voltage NMOS tube LV _ N1, and the third common low-voltage NMOS tube LV _ N3 and the fourth common low-voltage NMOS tube LV _ N4 connected with the drain terminal of the first PLDMOS tube PLD1 are turned off by being connected with the low level 0.
Therefore, when the high-voltage control main Input signal Ctr _ Logic _ Input by the high-voltage power domain is at the high level 1, the high level 1 of the low-voltage power domain is output after the preprocessing of the high-voltage power domain control circuit, the conversion of the core conversion circuit and the shaping of the low-voltage output shaping circuit.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the spirit or scope of the invention.
Claims (7)
1. A high-voltage to low-voltage level shift circuit with a high-voltage power supply domain capable of floating is characterized by comprising a high-voltage power supply domain control circuit, a core conversion circuit and a low-voltage output shaping circuit, wherein the high-voltage power supply domain control circuit is used for converting an input control signal of the high-voltage power supply domain into an output control signal of the low-voltage power supply domain; the high-voltage power supply domain control circuit carries out logic preprocessing on the input high-voltage domain control signal to control the core conversion circuit to work; the core conversion circuit converts the control input signals of the high-voltage power domains VBOOT-SW into the output control signals of the low-voltage power domains VIN-VSS, and the ground SW of the high-voltage power domain can float; the low-voltage output shaping circuit converts a signal with slow edge conversion output by the core conversion circuit into a rectangular pulse signal with steep edge by using the positive feedback effect in the conversion process of the Schmitt trigger.
2. The high voltage to low voltage level shift circuit of claim 1, wherein the high voltage power domain control circuit comprises a high voltage control Input signal Ctr _ Logic _ Input, a first inverter INV1, a second inverter INV 2;
the Input end of the first inverter INV1 is connected with a high-voltage control Input signal Ctr _ Logic _ Input, and the output end of the first inverter INV1 is connected with the Input end of the second inverter INV2 and is connected to the core conversion circuit; the output end of the second inverter INV2 is connected to the core conversion circuit.
3. The high-voltage to low-voltage level shift circuit capable of floating in high-voltage power domain according to claim 1, wherein the core conversion circuit comprises a first current source I1, a first common high-voltage PMOS transistor HV _ P1, a second common high-voltage PMOS transistor HV _ P2, a first PLDMOS transistor PLD1, a second PLDMOS transistor PLD2, a first common low-voltage NMOS transistor LV _ N1, a second common low-voltage NMOS transistor LV _ N2, a third common low-voltage NMOS transistor LV _ N3, a fourth common low-voltage NMOS transistor LV _ N4, a fifth common low-voltage NMOS transistor LV _ N5, a sixth common low-voltage NMOS transistor LV _ N6, a first common low-voltage PMOS transistor LV _ P1 and a second common low-voltage PMOS transistor LV _ P2;
the positive end of the first current source I1 is connected with VBOOT of a high-voltage power domain, and the negative end of the first current source I1 is connected with the source end of a first common high-voltage PMOS (P-channel metal oxide semiconductor) transistor HV _ P1; the source end of the first common high-voltage PMOS tube HV _ P1 is connected with the negative end of a first current source I1; the grid end is connected with the output end of a second inverter INV2 of the high-voltage power domain control circuit, and the drain end is connected with the source end of a first PLDMOS tube PLD 1; the source end of the second common high-voltage PMOS tube HV _ P2 is connected with the source end of the first common high-voltage PMOS tube HV _ P1, the gate end of the second common high-voltage PMOS tube HV _ P2 is connected with the output end of the first inverter INV1 of the high-voltage power domain control circuit, and the drain end of the second common high-voltage PMOS tube HV _ P1 is connected with the source end of the second PLDMOS tube PLD 2.
4. The high voltage to low voltage level shift circuit of claim 3, wherein the source terminal of the first PLDMOS transistor PLD1 is connected to the drain terminal of the first common high voltage PMOS transistor HV _ P1, the gate terminal is connected to the floating ground SW of the high voltage power domain, and the drain terminal is connected to the drain terminal of the first common low voltage NMOS transistor LV _ N1; the source end of the second PLDMOS tube PLD2 is connected with the drain end of the second common high-voltage PMOS tube HV _ P2, the gate end of the second PLDMOS tube PLD1 is connected with the gate end of the first PLDMOS tube PLD1, and the drain end of the second PLDMOS tube PLD2 is connected with the drain end of the second common low-voltage NMOS tube LV _ N2.
5. The high-voltage to low-voltage level shift circuit with the floating high-voltage power domain ground as claimed in claim 3, wherein the drain terminal of the first common low-voltage NMOS transistor LV _ N1 is connected to the drain terminal of the first PLDMOS transistor PLD1, the gate terminal is connected to the drain terminal of the second PLDMOS transistor PLD2, and the source terminal is connected to the ground VSS of the low-voltage power domain; the drain end of the second common low-voltage NMOS tube LV _ N2 is connected with the drain end of the second PLDMOS tube PLD2, the gate end of the second common low-voltage NMOS tube LV _ N2 is connected with the drain end of the first PLDMOS tube PLD1, and the source end of the second common low-voltage NMOS tube LV _ N1 is connected with the source end of the first common low-voltage NMOS tube LV _ N1;
the drain end and the gate end of the third common low-voltage NMOS tube LV _ N3 are both connected with the drain end of the first common low-voltage NMOS tube LV _ N1, and the source end of the third common low-voltage NMOS tube LV _ N2 is connected with the source end of the second common low-voltage NMOS tube LV _ N2; the drain end of the fourth common low-voltage NMOS tube LV _ N4 is connected with the drain end of the first common low-voltage PMOS tube LV _ P1, the gate end of the fourth common low-voltage NMOS tube LV _ N4 is connected with the gate end of the third common low-voltage NMOS tube LV _ N3, and the source end of the fourth common low-voltage NMOS tube LV _ N3 is connected with the source end of the third common low-voltage NMOS tube LV _ N3;
the drain end and the gate end of the fifth common low-voltage NMOS tube LV _ N5 are both connected with the drain end of the second common low-voltage NMOS tube LV _ N2, and the source end of the fifth common low-voltage NMOS tube LV _ N4 is connected with the source end of the fourth common low-voltage NMOS tube LV _ N4; the drain end of the sixth common low-voltage NMOS tube LV _ N6 is connected with the drain end of the second common low-voltage PMOS tube LV _ P2, the gate end of the sixth common low-voltage NMOS tube LV _ N5 is connected with the gate end of the fifth common low-voltage NMOS tube LV _ N5, and the source end of the sixth common low-voltage NMOS tube LV _ N6 is connected with the source end of the fifth common low-voltage NMOS tube LV _ N5.
6. The high-voltage to low-voltage level shift circuit with high-voltage power domain ground floatable of claim 3, wherein the source terminal of the first common low-voltage PMOS transistor LV _ P1 is connected to the VIN terminal of the low-voltage power supply, and the gate terminal and the drain terminal are both connected to the drain terminal of the fourth common low-voltage NMOS transistor LV _ N4; the source end of the second common low-voltage PMOS tube LV _ P2 is connected with the VIN end of a low-voltage power supply, the grid end of the second common low-voltage PMOS tube LV _ P2 is connected with the grid end of the first common low-voltage PMOS tube LV _ P1, and the drain end of the second common low-voltage PMOS tube LV _ P2 is connected with the input end of the low-voltage output shaping circuit.
7. The high voltage power domain ground-floatable low-to-high voltage level shifting circuit of claim 1, wherein said low voltage output shaping circuit comprises a first schmitt trigger SMIT 1;
the input end of the first Schmitt trigger SMIT1 is connected with the drain end of a second common low-voltage PMOS tube LV _ P2 of the core conversion circuit, and the output end of the first Schmitt trigger SMIT1 is connected with OUT to drive a post-stage circuit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210169669.8A CN114553212A (en) | 2022-02-23 | 2022-02-23 | Low-voltage-to-high-voltage level shift circuit with high-voltage power supply domain ground capable of floating |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210169669.8A CN114553212A (en) | 2022-02-23 | 2022-02-23 | Low-voltage-to-high-voltage level shift circuit with high-voltage power supply domain ground capable of floating |
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| CN114553212A true CN114553212A (en) | 2022-05-27 |
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| CN202210169669.8A Pending CN114553212A (en) | 2022-02-23 | 2022-02-23 | Low-voltage-to-high-voltage level shift circuit with high-voltage power supply domain ground capable of floating |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116232011A (en) * | 2023-03-07 | 2023-06-06 | 禹创半导体(深圳)有限公司 | Voltage conversion device with energy recovery mechanism and power supply chip |
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| US20180367132A1 (en) * | 2016-02-24 | 2018-12-20 | Byd Company Limited | Drive circuit of transistor |
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