CN114551597A

CN114551597A - Semiconductor structure and forming method thereof

Info

Publication number: CN114551597A
Application number: CN202011348197.XA
Authority: CN
Inventors: 金吉松
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2020-11-26
Filing date: 2020-11-26
Publication date: 2022-05-27

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, a grid structure, a side wall positioned on the side wall of the grid structure, a source-drain doped region, a bottom dielectric layer and a source-drain contact layer; removing the side wall to form a gap; forming a protective layer covering the bottom and the side wall of the gap in a shape-preserving manner; and forming a top dielectric layer on the bottom dielectric layer, wherein the top dielectric layer seals the gap to form an air gap. According to the embodiment of the invention, after the substrate is provided, the side wall is removed to form the gap, the protective layer is conformally covered on the bottom and the side wall of the gap, and the top dielectric layer for sealing the gap is formed to form the air gap.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background

With the continuous development of integrated circuit manufacturing technology, the requirements for the integration level and performance of integrated circuits become higher and higher. In order to improve the integration level and reduce the cost, the critical dimensions of the devices are becoming smaller, and the circuit density inside the integrated circuits is becoming higher, which makes the wafer surface unable to provide enough area to make the required interconnection lines.

In order to meet the requirement of the interconnection line after the critical dimension is reduced, the conduction of different metal layers or metal layers and the substrate is realized by an interconnection structure at present. The interconnect structure includes an interconnect line and a contact hole plug formed within the contact opening. The contact hole plugs are connected with the semiconductor device, and the interconnection lines realize connection between the contact hole plugs, thereby forming a circuit.

The contact hole plug in the transistor structure comprises a grid contact hole plug positioned on the surface of the grid structure and used for realizing the connection between the grid structure and an external circuit, and a source drain contact hole plug positioned on the surface of the source drain doped region and used for realizing the connection between the source drain doped region and the external circuit.

However, the performance of semiconductor structures is still desired.

Disclosure of Invention

Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which improve the performance of the semiconductor structure.

To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate; the grid structure is positioned on the substrate; the source-drain doped region is positioned in the substrate at two sides of the grid structure; the bottom dielectric layer is positioned on the substrate at the side part of the grid structure and covers the source drain doped region, and a gap is formed between the bottom dielectric layer and the side wall of the grid structure; the source-drain contact layer penetrates through the bottom dielectric layer at the top of the source-drain doped region and is in contact with the source-drain doped region; a gap between the sidewall of the gate structure and the source/drain contact layer; the protective layer is covered on the side wall and the bottom of the gap in a shape-preserving manner, and the protective layer is of an integrated structure; and the top dielectric layer is positioned on the bottom dielectric layer, seals the gap and forms an air gap with the gap in a surrounding manner.

Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate, wherein a grid structure is formed on the substrate, a side wall is formed on the side wall of the grid structure, source and drain doped regions are formed in the substrate at two sides of the grid structure, a bottom dielectric layer is formed on the side parts of the grid structure and the side wall and covers the source and drain doped regions, and source and drain contact layers penetrating through the bottom dielectric layer are formed at two sides of the grid structure and the side wall and are in contact with the source and drain doped regions; removing the side wall, and forming a gap between the side wall of the grid structure and the source drain contact layer; forming a protective layer covering the bottom and the side wall of the gap in a shape-preserving manner; and after the protective layer is formed, forming a top dielectric layer on the bottom dielectric layer, wherein the top dielectric layer seals the gap to form an air gap.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

the semiconductor structure provided by the embodiment of the invention comprises the protective layer which is conformally covered on the side wall and the bottom of the gap, the protective layer is of an integrated structure, the protective effect of the protective layer on the bottom and the side wall of the gap is favorably improved, the probability that film layer structures (such as a grid structure and a substrate) positioned at the bottom and the side wall of the gap are damaged in the forming process of the semiconductor structure is reduced, the integrity of the film layer structures positioned at the bottom and the side wall of the gap is correspondingly improved, and the reliability and the production yield of the semiconductor structure are further improved.

In the method for forming the semiconductor structure provided by the embodiment of the invention, in the step of providing the substrate, a side wall is formed on the side wall of the grid structure, after the substrate is provided, the side wall is removed, a Gap is formed between the side wall of the grid structure and the source drain contact layer, a protective layer is conformally covered on the bottom and the side wall of the Gap, and then a top dielectric layer for sealing the Gap is formed to form an Air Gap (Air Gap); according to the embodiment of the invention, the side wall is removed to form the gap, and the protective layer which covers the bottom and the side wall of the gap in a shape-preserving manner is formed, and the protective layer is correspondingly of an integrated structure, so that the protective effect of the protective layer on the bottom and the side wall of the gap is favorably improved, the damage probability of film layer structures (such as a grid structure and a substrate) at the bottom and the side wall of the gap in the forming process of the semiconductor structure is reduced, the integrity of the film layer structures at the bottom and the side wall of the gap is correspondingly improved, and the reliability and the production yield of the semiconductor structure are further improved.

In addition, the side wall positioned on the side wall of the gate structure is formed firstly, then the side wall is removed, compared with the side wall which is of a laminated structure and only part of the film layer in the side wall is removed, the size of the side wall is larger, the process space for removing the side wall is larger, the process difficulty is smaller, the size of a gap formed after the side wall is removed is larger, when a protective layer is formed, the residual space in the gap is larger easily by adjusting the forming thickness of the protective layer, the size of the air gap is increased correspondingly, the lower dielectric constant between the gate structure and the source drain contact layer is facilitated to be further reduced, and the effective capacitance between the gate structure and the source drain contact layer is facilitated to be further reduced.

Drawings

Fig. 1 to 10 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;

FIG. 11 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention;

fig. 12 to fig. 22 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

As is known in the art, the performance of the semiconductor structure needs to be improved. The reason why the performance of the semiconductor structure needs to be improved is analyzed in combination with a method for forming the semiconductor structure. Fig. 1 to 10 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure.

Referring to fig. 1, a substrate 10 is provided, a dummy gate structure 20 is formed on the substrate 10, and source/drain doped regions 11 are formed in the substrate 10 at two sides of the dummy gate structure 20.

Referring to fig. 2 to 4, a sidewall stack 30 is formed on the sidewall of the dummy gate structure 20.

Specifically, the step of forming the sidewall stack 30 includes:

as shown in fig. 2, a first sidewall film 34 is formed on the top and sidewalls of the dummy gate structure 20 and the top surface of the substrate 10; conformally covering a second sidewall film 35 on the first sidewall film 34;

as shown in fig. 3, removing the first sidewall film 34 and the second sidewall film 35 located at the top of the dummy gate structure 20 and the top surface of the substrate 10, where the remaining first sidewall film 34 is used as a first sidewall 31, and includes a side sidewall (not labeled) extending along the sidewall of the dummy gate structure 20 and a bottom sidewall (not labeled) connected to the bottom of the side sidewall and extending in a direction parallel to the substrate 10, where the remaining second sidewall film 35 is used as a sacrificial sidewall 32, and the sacrificial sidewall 32 covers the sidewalls of the side sidewall and the top surface of the bottom sidewall;

as shown in fig. 4, second sidewalls 33 are formed on the sidewalls of the sacrificial sidewall 32 and the bottom sidewall.

Referring to fig. 5, a bottom dielectric layer 12 covering the source/drain doped region 11 is formed on the substrate 10 at the side of the dummy gate structure 20, and the bottom dielectric layer 12 covers the side wall of the sidewall stack 30.

Referring to fig. 6, the dummy gate structure 20 is removed, and a gate opening (not shown) is formed in the bottom dielectric layer 12; a gate structure 40 is formed in the gate opening.

Referring to fig. 7, a source/drain contact layer 50 penetrating through the bottom dielectric layer 12 and contacting the source/drain doped region 11 is formed.

Referring to fig. 8, a sacrificial dielectric layer 13 is formed on the bottom dielectric layer 12 to cover the source/drain contact layer 50, the gate structure 40 and the sidewall stack 30.

Continuing to refer to fig. 8, forming a source/drain plug 60 penetrating the gate structure 40 and the sacrificial dielectric layer 13 and the bottom dielectric layer 12 on both sides of the sidewall stack 30, and contacting the top of the source/drain contact layer 50; a gate plug 70 is formed through the sacrificial dielectric layer 13 on top of the gate structure 40 and contacts the top of the gate structure 40.

Referring to fig. 9, after forming the source-drain plugs 60 and the gate plugs 70, the sacrificial medium layer 13 and the sacrificial side walls 32 are removed, so that a gap 80 is defined by the first side walls 31 and the second side walls 33.

Referring to fig. 10, a top dielectric layer 14 is formed on the bottom dielectric layer 12 between the source drain plugs 60 and the gate plugs 70, and the top of the gap 80 is sealed to form an air gap 90.

In the forming method, after the source-drain plug 60 and the gate plug 70 are formed, the sacrificial dielectric layer 13 and the sacrificial side wall 32 are removed, so that the first side wall 31 and the second side wall 33 surround to form the gap 80, and after the top dielectric layer 14 is formed, the top of the gap 80 is sealed to form the air gap 90, wherein the air gap 90 is located between the gate structure 40 and the source-drain contact layer 50, which is beneficial to reducing the effective capacitance between the gate structure 40 and the source-drain contact layer 50.

However, the interface position where the bottom of the sidewall of the first sidewall 31 contacts the second sidewall 33 (i.e. the joint shown by the dashed circle in fig. 9) is a Weak Point (Weak Point), which is prone to reduce the reliability of the device, for example: in the step of removing the sacrificial dielectric layer 13 and the sacrificial side wall 32, an etching process is likely to etch along a contact interface between the first side wall 31 and the second side wall 33, so that the joint is likely to be etched, and the source-drain doped region 11 or the substrate 10 of the active region below the joint is also likely to be damaged, which may cause poor performance of the device (e.g., poor reliability of the device) and may also cause a reduction in production yield.

In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, which includes a protection layer conformally covering a sidewall and a bottom of the gap, wherein the protection layer is an integrated structure, which is beneficial to improving a protection effect of the protection layer on the bottom and the sidewall of the gap, and reducing a probability of damage to film structures (e.g., a gate structure and a substrate) located at the bottom and the sidewall of the gap during a formation process of the semiconductor structure, and accordingly, improving integrity of the film structures located at the bottom and the sidewall of the gap, and further improving reliability and production yield of the semiconductor structure.

In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below. Referring to fig. 11, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.

As shown in fig. 11, in the present embodiment, the semiconductor structure includes: a substrate 100; a gate structure 110 on the substrate 100; the source-drain doped region 120 is positioned in the substrate 100 at two sides of the gate structure 110; a bottom dielectric layer 130, located on the substrate 100 at the side of the gate structure 110 and covering the source-drain doped region 120, wherein a space is formed between the bottom dielectric layer 170 and the sidewall of the gate structure 110; the source-drain contact layer 140 penetrates through the bottom dielectric layer 130 at the top of the source-drain doped region 120 and is in contact with the source-drain doped region 120; a gap 150 (refer to fig. 21 in combination) between a sidewall of the gate structure 110 and the source/drain contact layer 140; a protection layer 160 conformally covering the sidewall and the bottom of the gap 150, wherein the protection layer 160 is of an integral structure; and the top dielectric layer 170 is positioned on the bottom dielectric layer 130, and the top dielectric layer 170 seals the gap 150 and forms an air gap 200 with the gap 150.

The substrate 100 is used to provide a process platform for the formation of semiconductor structures.

In the present embodiment, taking the formation of a fin field effect transistor (FinFET) as an example, the substrate 100 includes a substrate (not shown) and a fin portion (not shown) protruding from the substrate.

In other embodiments, the substrate may be used to form other types of transistors such as planar field effect transistors, fully-wrapped-gate transistors (GAA) or fork-type gate transistors (forkheet), and accordingly, the substrate may be a planar substrate or other types of three-dimensional substrates depending on the actual transistor type.

In this embodiment, the substrate is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon-on-insulator substrate or another type of substrate such as a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.

The fin is for providing a conductive channel of a field effect transistor. In this embodiment, the material of the fin portion is the same as the material of the substrate, and the material of the fin portion is silicon. In other embodiments, the material of the fin may also be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other semiconductor materials suitable for forming the fin.

The gate structure 110 is used to control the turn-on and turn-off of the conduction channel of the field effect transistor.

In this embodiment, the gate structure 110 is located on the substrate, and the gate structure 110 crosses over the fin and covers a portion of the top and a portion of the sidewall of the fin.

In this embodiment, the Gate structure 110 is a Metal Gate (Metal Gate) structure, the Gate structure 110 is formed by a process of forming a high-k Gate dielectric layer and then forming a Metal Gate (high-k last Metal Gate), and the Gate structure 110 includes the high-k Gate dielectric layer (not shown), a work function layer (not shown) on the high-k Gate dielectric layer, and a Gate electrode layer (not shown) on the work function layer.

In this embodiment, the semiconductor structure further includes: a gate capping layer 115 between the top of the gate structure 110 and the top dielectric layer 170.

The semiconductor structure generally further includes source and drain plugs 210 in contact with the source and drain contact layer 140, and the gate capping layer 115 is used for protecting the gate structure 110 during the formation of the source and drain plugs 210, so as to reduce the probability that the gate structure 110 is damaged and the source and drain plugs 210 are shorted with the gate structure 110.

The gate capping layer 115 is selected to have an etching selectivity with the bottom dielectric layer 130, thereby being beneficial to ensuring that the gate capping layer 115 can protect the gate structure 110. In this embodiment, the material of the gate capping layer 115 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the gate capping layer 115 is silicon carbide.

In this embodiment, the gate capping layer 115 is flush with the top surface of the bottom dielectric layer 130.

The source-drain doped region 120 serves as a source region or a drain region of the formed transistor, and is used for providing a carrier source when the device works. In this embodiment, the source/drain doped region 120 includes an epitaxial layer doped with ions.

When the NMOS transistor is formed, the epitaxial layer is made of Si or SiC, the epitaxial layer provides a tensile stress effect for a channel region of the NMOS transistor, and the carrier mobility of the NMOS transistor is improved, wherein doped ions in the epitaxial layer are N-type ions. When the PMOS transistor is formed, the epitaxial layer is made of Si or SiGe, and provides a pressure stress effect for a channel region of the PMOS transistor, so that the carrier mobility of the PMOS transistor is improved, wherein the doped ions in the epitaxial layer are P-type ions.

The bottom dielectric layer 130 is used for isolating adjacent devices, and the bottom dielectric layer 130 is also used for realizing isolation between the source-drain contact layer 140 and the gate structure 110. In this embodiment, the bottom Dielectric Layer 130 is an Inter Layer Dielectric (ILD). The material of the bottom dielectric layer 130 is an insulating material, and includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. As an example, the material of the bottom dielectric layer 130 is silicon oxide.

The source-drain contact layer 140 is in contact with the source-drain doped region 120, and is used for electrically connecting the source-drain doped region 120 with an external circuit or other interconnection structures.

As an example, the material of the source drain contact layer 140 is copper. The resistivity of copper is low, which is beneficial to improving the signal delay of the rear-section RC and improving the processing speed of the chip, and is also beneficial to reducing the resistance of the source-drain contact layer 140, and correspondingly reducing the power consumption. In other embodiments, the source-drain contact layer may also be made of a conductive material such as tungsten or cobalt.

In this embodiment, the semiconductor structure further includes: and the first adhesion layer 145 is positioned on the side wall and the bottom of the source-drain contact layer 140.

The first adhesion layer 145 is used for improving the adhesion between the source/drain contact layer 140 and the bottom dielectric layer 130. In this embodiment, the first adhesion layer 145 is further used as a diffusion barrier layer for preventing the material of the source/drain contact layer 140 from diffusing into the bottom dielectric layer 130, so as to improve the problem of Electro-migration (EM); moreover, the first adhesion layer 145 is also used for preventing impurities such as carbon atoms and oxygen atoms in the bottom dielectric layer 130 from diffusing into the source-drain contact layer 140, which is beneficial to improving the reliability of the semiconductor structure. In other embodiments, the first adhesion layer may also be used as an adhesion layer only, depending on the actual process requirements.

In this embodiment, the material of the first adhesion layer 145 includes one or more of tantalum, tantalum nitride, titanium nitride, cobalt, manganese oxide, ruthenium nitride, and ruthenium. In this embodiment, the first adhesion layer 145 is made of titanium nitride.

In other embodiments, the semiconductor structure may further include: and the source-drain cap layer is positioned between the top dielectric layer and the source-drain contact layer. Correspondingly, the source drain plug penetrates through the source drain cap layer.

The source and drain cap layer is used for protecting the source and drain contact layer. For example: in the process of forming the gate plug which is in contact with the gate structure on the top of the gate structure, the source-drain cap layer is used for protecting the source-drain contact layer, so that the damage of the source-drain contact layer and the probability of short circuit between the gate plug and the source-drain contact layer are reduced.

The source-drain cap layer is made of a material with high etching selectivity with the bottom dielectric layer and the grid cap layer, so that the source-drain cap layer can protect the source-drain contact layer. The material of the source drain cap layer comprises one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride and boron carbonitride. As an example, the top surfaces of the source drain cap layer and the bottom dielectric layer are flush.

The gap 150 is used to form an air gap 200 with the top dielectric layer 170, thereby reducing the effective capacitance between the source drain contact layer 140 and the gate structure 110. Specifically, the gap 150 is formed by removing the sidewall spacers 300 (refer to fig. 16) on the sidewalls of the gate structure 110.

In this embodiment, the sidewall of the gate structure 110, a part of the top surface of the source/drain doped region 120, a part of the top surface of the substrate 100, and a part of the sidewall of the bottom dielectric layer 130 are exposed from the gap 150.

Correspondingly, compared with the gap formed by removing part of the film layer in the sidewall, the width of the gap 150 in the embodiment is larger, which is beneficial to increase the size of the air gap 200, and is further beneficial to enabling the dielectric constant (K value) between the gate structure 110 and the source-drain contact layer 140 to be lower, and the performance of the semiconductor structure is remarkably improved.

It should be noted that, in the direction perpendicular to the sidewall of the gate structure 110, the width of the gap 150 is not too small, otherwise, in the forming process of the protection layer 160, the difficulty of conformally covering the protection layer 160 on the bottom and the sidewall of the gap 150 is large, the film forming quality of the protection layer 160 is easily reduced, the protection effect of the protection layer 160 on the bottom and the sidewall of the gap 150 is easily reduced, and the size of the air gap 200 is also easily too small; the width of the gap 150 is not too large, otherwise, the distance between the source-drain contact layer 140 and the gate structure 110 is too large, which results in an excessively large area occupied by the semiconductor structure, and the development requirement of device miniaturization is difficult to meet. For this reason, in the present embodiment, the width of the gap 150 is 2nm to 15nm in a direction perpendicular to the sidewall of the gate structure 110.

The protective layer 160 serves to protect the bottom and sidewalls of the gap 150.

Specifically, in the embodiment, in the forming process of the semiconductor structure, after the gap 150 is formed, the protective layer 160 is conformally covered on the bottom and the sidewall of the gap 150, and the protective layer 160 is correspondingly an integral structure, which is beneficial to improving the protective effect of the protective layer 160 on the bottom and the sidewall of the gap 150, and reduces the probability that the film structures (e.g., the gate structure 110 and the substrate 100) at the bottom and the sidewall of the gap 150 are damaged in the forming process of the semiconductor structure, so that the integrity of the film structures at the bottom and the sidewall of the gap 150 is correspondingly improved, and further the reliability and the production yield of the semiconductor structure are improved.

Specifically, the protective layer 160 is an integral structure, so that there is no seam in the structure of the protective layer 160, and the sealing performance of the protective layer 160 is good, thereby improving the protective effect on the sidewall and the bottom of the gap 150.

Therefore, the protective layer 160 is made of a material with high density and high etching resistance, so as to ensure the protective effect of the protective layer 160 on the film structure at the bottom and the sidewall of the gap 150, and the protective layer 160 is retained in the semiconductor structure, so that the material of the protective layer 160 is an insulating material. In addition, the protection layer 160 is also located between the source/drain contact layer 140 and the gate structure 110, the protection layer 160 also affects the effective capacitance between the source/drain contact layer 140 and the gate structure 110, and the dielectric constant (K value) of the material of the protection layer 150 cannot be too high.

In this embodiment, the material of the protection layer 160 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, boron carbonitride, aluminum oxide, and aluminum nitride. As an example, the protection layer 160 has a single-layer structure, and the material of the protection layer 160 is silicon nitride.

It should be noted that the thickness of the protection layer 160 is not too small, otherwise the protection effect of the protection layer 160 on the sidewall and the bottom of the gap 150 is easily reduced, and the protection layer 160 is also located between the source-drain contact layer 140 and the gate structure 110, the protection layer 160 may affect the effective capacitance between the source-drain contact layer 140 and the gate structure 110, and the larger the thickness of the protection layer 160 is, the larger the influence on the effective capacitance between the source-drain contact layer 140 and the gate structure 110 is, so the thickness of the protection layer 160 is also not too large, and at the same time, the too large thickness of the protection layer 160 may easily fill the gap 150, or cause the remaining space of the gap 150 to be too small, and accordingly may easily cause the size of the air gap 200 to be too small. For this reason, in the present embodiment, the thickness of the protection layer 160 is 10% to 90% of the width of the gap 150 in the direction perpendicular to the sidewall of the gate structure 110.

Specifically, in the present embodiment, the thickness of the protection layer 160 is 1nm to 10 nm. The thickness of the protection layer 160 is smaller, which is beneficial to making the remaining space of the gap 150 larger, and further beneficial to making the size of the air gap 200 larger, and is beneficial to making the reduction effect of the effective capacitance between the source-drain contact layer 140 and the gate structure 110 more obvious, and further beneficial to further improving the performance of the semiconductor structure.

It should be noted that, in this embodiment, the protection layer 160 is further located between the bottom dielectric layer 130 and the top dielectric layer 170, between the source-drain contact layer 140 and the top dielectric layer 170, and between the gate capping layer 115 and the top dielectric layer 170.

In this embodiment, the semiconductor structure further includes: and the source and drain plugs 210 are positioned on the top of the source and drain contact layer 140 and are in contact with the source and drain contact layer 140. The source and drain plugs 210 are in contact with the source and drain contact layer 140, and are used for electrically connecting the source and drain doped regions 120 with an external circuit or other interconnection structures.

In this embodiment, the source/drain plug 210 further penetrates the protection layer 160 on the source/drain contact layer 140.

In other embodiments, when the semiconductor structure further includes a source-drain cap layer located between the source-drain contact layer and the top dielectric layer, the source-drain plug correspondingly penetrates through the source-drain cap layer.

In this embodiment, the semiconductor structure further includes: and a gate plug 220 located on the top of the gate structure 110 and contacting the gate structure 110. The gate plug 220 is used to electrically connect the gate structure 110 with an external circuit or other interconnect structure.

In this embodiment, the gate plug 220 contacts the top of the gate structure 110 of the active region, and the gate plug 110 correspondingly penetrates through the gate cap layer 115.

In this embodiment, the gate plug 220 is located above the gate structure 110 of the active region, and the gate plug 220 is correspondingly an active gate contact hole plug (COAG), so as to be beneficial to saving the area of the chip and further reducing the size of the chip.

In this embodiment, the gate plug 220 also penetrates through the protection layer 160 on the gate capping layer 115.

In this embodiment, the gate plug 220 and the source/drain plug 210 are made of the same material. For a specific description of the materials of the gate plug 220 and the source drain plug 210, reference may be made to the foregoing description of the source drain contact layer 140, and details are not repeated here.

In this embodiment, the semiconductor structure further includes: the second adhesion layer 230 is disposed on the bottom and the sidewall of the gate plug 220, and on the bottom and the sidewall of the source/drain plug 210.

The second adhesion layer 230 is used to improve adhesion between the gate plug 220 and the top dielectric layer 170, and improve adhesion between the source/drain plug 210 and the top dielectric layer 170. In this embodiment, the second adhesion layer 230 is also used as a diffusion barrier layer for preventing the materials of the gate plug 220 and the source-drain plug 210 from diffusing into the top dielectric layer 170, so as to improve the problem of electromigration; moreover, the second adhesion layer 230 is also used to prevent impurities such as carbon atoms and oxygen atoms in the top dielectric layer 170 from diffusing into the gate plug 220 and the source-drain plug 210, which are both beneficial to improving the reliability of the semiconductor structure. In other embodiments, the second adhesion layer may also be used as the adhesion layer only, depending on the actual process requirements.

It should be further noted that, in this embodiment, the semiconductor structure further includes: and a third adhesion layer 240 on top of the gate plug 220 and the source and drain plugs 210.

The semiconductor structure generally further includes an inter-metal dielectric (IMD) layer located on top of the gate plug 220 and the source-drain plug 210, and the third adhesion layer 240 is used for protecting the top of the gate plug 220 and the source-drain plug 210 and for improving adhesion between the gate plug 220 and the inter-metal dielectric layer and between the source-drain plug 210 and the inter-metal dielectric layer. In this embodiment, the third adhesion layer 240 can also be used as a diffusion barrier layer, which is beneficial to improve electromigration.

For a detailed description of the materials of the second adhesion layer 230 and the third adhesion layer 240, reference may be made to the corresponding description of the first adhesion layer 145, and this embodiment is not repeated herein.

The top dielectric layer 170 serves to seal the gap 150, thereby enclosing an air gap 200.

The air gap 200 has a dielectric constant lower than that of a dielectric material (e.g., a low-k dielectric material or an ultra-low-k dielectric material) commonly used in a semiconductor process, thereby facilitating reduction of effective capacitance between the gate structure 110 and the source-drain contact layer 140, reduction of RC delay, and further improvement of performance of the semiconductor structure.

As can be seen from the foregoing description, the space of the gap 150 provided in the present embodiment is larger, and the protection layer 160 is formed after the gap 150 is formed, so that the remaining space of the gap 150 is larger by adjusting the thickness of the protection layer 160, and accordingly, the size of the air gap 200 enclosed by the top dielectric layer 170 and the gap 150 is larger, which is favorable for providing a lower dielectric constant between the gate structure 110 and the source/drain contact layer 140, and is favorable for further improving the performance of the semiconductor structure.

In this embodiment, the top dielectric layer 170 is located between the source-drain plugs 210. Specifically, the top dielectric layer 170 is located between the gate plug 220 and the source drain plug 210. Correspondingly, in this embodiment, the top dielectric layer 170 is further used to realize electrical isolation between the source-drain plugs 210 and the gate plugs 220.

In this embodiment, in the extending direction perpendicular to the gate structure 110, the cross sections of the gate plug 220 and the source-drain plug 210 are both of inverted trapezoidal structures with a large top and a small bottom, and in the forming process of the top dielectric layer 170, before the gap 150 is filled with the material of the top dielectric layer 170, the materials of the top dielectric layer 170 at the top corners of the gate plug 220 and the source-drain plug 210 gradually contact each other, so that the gap 150 is sealed, and the air gap 200 is formed.

As shown in fig. 11, in this embodiment, the air gaps 200 are further located between the gate plug 220 and the source-drain contact layer 140, and between the gate plug 220 and a portion of the source-drain plug 210, so as to be beneficial to reducing parasitic capacitance between the gate plug 220 and the source-drain contact layer 140, and between the gate plug 220 and the source-drain plug 210, and reducing RC delay, thereby improving performance of the semiconductor structure.

In this embodiment, the gate plug 220 is an active gate contact hole plug (COAG), and compared with a conventional gate plug located in an isolation region, the distance between the source-drain contact layer 140 and the source-drain plug 210 of the gate plug 220 in this embodiment is shorter, and by making the air gap 200 also located between the gate plug 220 and the source-drain contact layer 140, and between the gate plug 220 and the source-drain plug 210, it is beneficial to significantly reduce the parasitic capacitance between the gate plug 220 and the source-drain contact layer 140, and between the gate plug 220 and the source-drain plug 210, and reduce the RC delay problem, thereby significantly improving the performance of the semiconductor structure.

In this embodiment, the top dielectric layer 170 is flush with the tops of the gate plug 220 and the source/drain plug 210 as an example. In other embodiments, the top of the top dielectric layer may be lower than the tops of the gate plug and the source drain plug. In other embodiments, the top dielectric layer may further cover the tops of the gate plug and the source-drain plug, and the top dielectric layer on the tops of the gate plug and the source-drain plug may be used as an inter-metal dielectric layer of a next interconnect structure, which is beneficial to improving compatibility with the existing process.

In this example, the COAG process is described as an example. In other embodiments, when the gate plug is located at the top of the gate structure of the isolation region, the semiconductor structure provided in this embodiment can still reduce the effective capacitance between the gate structure and the source-drain contact layer, the parasitic capacitance between the gate plug and the source-drain contact layer, and the parasitic capacitance between the source-drain plug and the gate plug.

Correspondingly, the invention also provides a forming method of the semiconductor structure. Fig. 12 to fig. 22 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

The method for forming the semiconductor structure of the present embodiment is described in detail below with reference to the accompanying drawings.

Referring to fig. 12 to 16, a substrate 100 is provided, a gate structure 110 is formed on the substrate 100, a side wall 300 is formed on a side wall of the gate structure 110, source and drain doped regions 120 are formed in the substrate 100 on two sides of the gate structure 110, a bottom dielectric layer 130 is formed on the side portions of the gate structure 110 and the side wall 300 to cover the source and drain doped regions 120, and source and drain contact layers 140 penetrating through the bottom dielectric layer 130 are formed on two sides of the gate structure 110 and the side wall 300 to be in contact with the source and drain doped regions 120.

The substrate 100 is used to provide a process platform for subsequent process steps.

In this embodiment, taking the substrate 100 as an example for forming a fin field effect transistor (FinFET), the substrate 100 includes a substrate (not shown) and a fin (not shown) protruding from the substrate.

In other embodiments, the substrate may be used to form other types of transistors such as a planar field effect transistor (fet), a gate all around transistor (GAA), or a fork gate transistor (forkheet), and accordingly, the substrate may be a planar substrate or other types of three-dimensional substrates depending on the type of transistors actually formed.

In this embodiment, the substrate is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.

In this embodiment, the Gate structure 110 is a Metal Gate (Metal Gate) structure, the Gate structure 110 is formed by a process of forming a high-k Gate dielectric layer to form a Metal Gate (high-k last Metal Gate), and the Gate structure 110 includes a work function layer (not shown) and a Gate electrode layer (not shown) on the work function layer.

The sidewall 300 is used to protect the sidewall of the gate structure 110, and the sidewall 300 is further used to isolate the gate structure 110 from the source-drain contact layer 140. In this embodiment, the sidewall Spacer 300 is further used as a Dummy Spacer (Dummy Spacer) to occupy a space for a subsequent gap formation. Specifically, the side wall 300 is subsequently removed, and a gap is formed at the position where the side wall 300 is originally located.

Therefore, the materials of the sidewall 300 are selected as follows: in the subsequent process of removing the sidewall spacer 300, the etching selectivity between the sidewall spacer 300 and other film layers (e.g., the gate structure 110, the bottom dielectric layer 130, etc.) is relatively high, so that the process of removing the sidewall spacer 300 has little damage to the other film layers. Correspondingly, in the embodiment, the material of the side wall 300 can be flexibly selected, so that the material of the side wall 300 is compatible with the subsequent process, and the performance of the semiconductor structure is correspondingly improved.

The sidewall 300 may have a single-layer structure or a stacked-layer structure, and the material of the sidewall 300 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, boron nitride, silicon oxycarbide, silicon oxyboride, aluminum oxide, and aluminum nitride. In this embodiment, the sidewall spacer 300 is made of silicon nitride. By selecting silicon nitride, the compatibility of the sidewall spacer 300 with subsequent processes can be improved.

It should be noted that, the sidewall spacers 300 are subsequently removed to form a gap, and a protective layer is formed to conformally cover the bottom and sidewalls of the gap. When the thickness of the side wall 300 is too small, the difficulty of conformally covering the protective layer on the bottom and the side wall of the gap is high, the formation quality of the protective layer is easily reduced, the protective effect of the protective layer on the bottom and the side wall of the gap is easily reduced, the remaining space in the gap is easily too small, and accordingly, the size of the formed air gap is too small; when the thickness of the sidewall 300 is too large, the distance between the source-drain contact layer 140 and the gate structure 110 is too large, so that the semiconductor structure occupies too large area, and the development requirement of device miniaturization is difficult to meet. For this reason, in the present embodiment, the thickness of the sidewall 300 is 2nm to 15nm in a direction perpendicular to the sidewall of the gate structure 110.

The source-drain doped region 120 serves as a source region or a drain region of the formed transistor, and is used for providing a current carrier source when the device works. In this embodiment, the source/drain doped region 120 includes an epitaxial layer doped with ions.

The following describes in detail the steps of providing the substrate 100, the gate structure 110, the sidewall spacers 300, the source-drain doped region 120, the bottom dielectric layer 130, and the source-drain contact layer 140 in this embodiment with reference to the drawings.

As shown in fig. 12, a substrate 100 is provided; a dummy gate structure 310 is formed on the substrate 100.

Dummy gate structures (dummy gate)310 are used to occupy a spatial location for the formation of gate structures 110.

In this embodiment, the dummy gate structure 310 is a polysilicon gate structure, that is, the dummy gate structure 310 includes a dummy gate layer, and the dummy gate layer is made of polysilicon. In other embodiments, the material of the dummy gate layer may further include other materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or amorphous carbon.

As shown in fig. 13, the sidewall 300 on the sidewall of the dummy gate structure 310 and the source-drain doped region 120 in the substrate 100 on both sides of the dummy gate structure 310 are formed.

As an example, the step of forming the sidewall spacers 300 and the source-drain doped regions 120 includes: after the dummy gate structure 310 is formed, forming a first sidewall (not shown) on a sidewall of the dummy gate structure 310; forming the source-drain doped region 120 in the dummy gate structure 310 and the substrate 100 on both sides of the first sidewall; after the source-drain doped region 120 is formed, a second sidewall (not shown) is formed on the sidewall of the first sidewall, and the first sidewall and the second sidewall located on the first sidewall are used as the sidewall 300.

As an example, in order to improve process compatibility and reduce difficulty in subsequently removing the sidewall spacers 300, the material of the first sidewall spacer is the same as that of the second sidewall spacer.

It should be noted that the above steps of forming the sidewall spacers 300 and the source and drain doped regions 120 are only used as an example, and the steps of forming the sidewall spacers 300 and the source and drain doped regions 120 are not limited thereto. For example: in other embodiments, the step of forming the sidewall spacer and the source/drain doped region may include: forming a side wall on the side wall of the grid structure; and forming the source-drain doped region in the substrate at the two sides of the grid structure and the side wall.

As shown in fig. 14, the bottom dielectric layer 130 is formed on the dummy gate structure 310 and the substrate 100 at the side of the sidewall 300 to cover the source-drain doped region 120.

Specifically, the bottom dielectric layer 130 is formed by deposition and planarization processes (e.g., chemical mechanical polishing processes) such that the bottom dielectric layer 130 exposes the top of the dummy gate structure 310.

As shown in fig. 15, a source/drain contact layer 140 is formed to penetrate through the bottom dielectric layer 130 on the top of the source/drain doped region 120 and to contact the source/drain doped region 120.

Specifically, the step of forming the source/drain contact layer 140 includes: forming a source-drain opening (not shown) penetrating through the bottom dielectric layer 130 on the top of the source-drain doped region 120 to expose the source-drain doped region; and filling the source-drain contact layer 140 in the source-drain opening.

In this embodiment, after forming the source/drain opening and before filling the source/drain contact layer 140 in the source/drain opening, the forming method further includes: a first adhesion layer 145 is formed on the bottom and sidewalls of the source and drain openings.

The first adhesion layer 145 is used for improving the adhesion between the source/drain contact layer 140 and the bottom dielectric layer 130. In this embodiment, the first adhesion layer 145 is further used as a diffusion barrier layer for preventing the material of the source/drain contact layer 140 from diffusing into the bottom dielectric layer 130, so as to improve the problem of electromigration; in addition, the first adhesion layer 145 is also used to prevent impurities such as carbon atoms and oxygen atoms in the bottom dielectric layer 130 from diffusing into the source/drain contact layer 140, which is beneficial to improving the reliability of the semiconductor structure. In other embodiments, the first adhesion layer can also be used as the adhesion layer only according to the actual process requirements.

As an example, the source-drain contact layer 140 is formed before the dummy gate structure 310 is removed and the gate structure 110 is formed. However, the sequence of forming the source/drain contact layer 140, removing the dummy gate structure 310, and forming the gate structure 110 is not limited thereto. For example: in other embodiments, the source/drain contact layer may also be formed after the gate structure is formed.

In other embodiments, in the step of forming the source-drain contact layer, a source-drain capping layer may be further formed on the top of the source-drain contact layer. The source and drain cap layer is used for protecting the source and drain contact layer.

For example: in the steps of removing the dummy gate structure to form a gate opening and forming the gate structure in the gate opening, the source-drain cap layer can protect the source-drain contact layer. Another example is: the subsequent processing procedure also comprises a step of forming a grid electrode plug which is contacted with the grid electrode structure, and the source-drain cover cap layer is used for protecting the source-drain contact layer in the process of forming the grid electrode plug, so that the damage of the source-drain contact layer and the probability of short circuit between the grid electrode plug and the source-drain contact layer are favorably reduced.

The source-drain cap layer is made of materials with high etching selectivity with the side wall, the bottom dielectric layer and the dummy gate structure, and the source-drain cap layer is favorable for protecting the source-drain contact layer. The material of the source drain cap layer comprises one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride and boron carbonitride.

As an example, the step of forming the source and drain cap layer includes: after forming the source drain contact layer, removing the source drain contact layer with partial thickness; and forming a source drain cap layer on the top of the source drain contact layer. As an example, the top surfaces of the source drain cap layer and the bottom dielectric layer are flush.

As shown in fig. 16, the dummy gate structure 310 is removed, and a gate opening (not shown) is formed in the bottom dielectric layer 130; the gate structure 110 is formed in the gate opening.

In this embodiment, a gate capping layer 115 is also formed on top of the gate structure 110. When source and drain plugs are formed subsequently, the gate capping layer 115 is used to protect the gate structure 110, so as to reduce the probability that the gate structure 110 is damaged and the source and drain plugs are shorted with the gate structure 110.

The gate capping layer 115 is made of a material having an etching selectivity with the bottom dielectric layer 130 and the sacrificial dielectric layer formed subsequently, thereby ensuring that the gate capping layer 115 can protect the gate structure 110. In this embodiment, the material of the gate capping layer 115 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the gate capping layer 115 is silicon carbide.

Specifically, in the present embodiment, after the gate structure 110 is formed, the gate structure 110 with a partial thickness is etched back; after etching back the gate structure 110 with a part of the thickness, a gate cap layer 115 is formed in the region surrounded by the sidewall spacers 300 and the remaining gate structure 110. In this embodiment, the gate capping layer 115 is flush with the top surface of the bottom dielectric layer 130.

Referring to fig. 17, the sidewall spacers 300 are removed, and a gap 150 is formed between the sidewall of the gate structure 110 and the source/drain contact layer 140.

The gap 150 is used to form an air gap, thereby reducing the effective capacitance between the source drain contact layer 140 and the gate structure 110, and the gap 150 is also used to provide a process space for forming a protection layer.

In this embodiment, the sidewall spacers 300 on the sidewalls of the gate structures 110 are formed first, and then the sidewall spacers 300 are removed to form the gaps 150, compared with the side wall with a laminated structure and only partial film layers in the side wall are removed, the side wall 300 of the present embodiment has a larger size, a larger process space and a smaller process difficulty for removing the side wall 300, and the size of the gap 150 formed after removing the side wall 300 is larger, when the protective layer conformally covering the bottom and the side wall of the gap 150 is formed subsequently, it is not only beneficial to provide a larger process space for forming the protective layer, it is also easy to make the remaining space in the gap 150 larger by adjusting the formation thickness of the protective layer, which is advantageous in increasing the size of the air gap, and further, a lower dielectric constant is provided between the gate structure 110 and the source-drain contact layer 140, which is beneficial to further reduce the effective capacitance between the gate structure 110 and the source-drain contact layer 140.

In this embodiment, the gap 150 exposes the sidewall of the gate structure 110, a part of the top surface of the source-drain doped region 120, a part of the top surface of the substrate 100, and a part of the sidewall of the bottom dielectric layer 130.

In this embodiment, the gap 150 is formed by removing the sidewall 300, and in a direction perpendicular to the sidewall of the gate structure 110, the size of the gap 150 is the same as the thickness of the sidewall 300, and the size of the gap 150 is 2nm to 15 nm.

In this embodiment, the process of removing the sidewall spacer 300 includes one or both of a dry etching process and a wet etching process. As an example, the sidewall spacers 300 are removed by sequentially using a dry etching process and a wet etching process. The dry etching process is an isotropic dry etching process, so that the side wall 300 can be removed cleanly, and high etching selection ratio and high etching efficiency are easy to realize; the wet etching process also has the characteristic of isotropic etching, which is beneficial to further ensuring that the sidewall 300 is not left.

Referring to fig. 18, a protective layer 160 is formed to conformally cover the bottom and sidewalls of the gap 150.

In this embodiment, in the step of providing the substrate 100, a sidewall 300 is formed on a sidewall of the gate structure 110, after the substrate 100 is provided, the sidewall 300 is removed, a gap 150 is formed between the sidewall of the gate structure 110 and the source-drain contact layer 140, and a protective layer 160 is conformally covered on the bottom and the sidewall of the gap 150, where the protective layer 160 is an integrated structure, which is beneficial to improving the protective effect of the protective layer 160 on the bottom and the sidewall of the gap 150, reducing the probability of damage to film layer structures (e.g., the gate structure 110 and the substrate 100) located at the bottom and the sidewall of the gap 150 in the formation process of the semiconductor structure, and accordingly improving the integrity of the film layer structures located at the bottom and the sidewall of the gap 150, and further improving the reliability and the production yield of the semiconductor structure.

Specifically, in the step of forming the protection layer 160, the protection layer 160 is an integrated structure, so that no seam exists in the structure of the protection layer 160, the sealing performance of the protection layer 160 is good, and the protection layer 160 is not easily etched in the subsequent process (for example, removing a sacrificial medium layer), thereby improving the protection effect on the sidewall and the bottom of the gap 150.

Therefore, the protective layer 160 is made of a material with high density and high etching resistance, so as to ensure the protective effect of the protective layer 160 on the film structure at the bottom and the side wall of the gap 150. Specifically, a sacrificial dielectric layer is further formed on the bottom dielectric layer 130, the sacrificial dielectric layer is further formed in the gap 150, and then the sacrificial dielectric layer is removed, so that the protective layer 160 is made of a material having high etching selectivity with respect to the sacrificial dielectric layer, so that the protective layer 160 can serve as an etching stop layer for removing the sacrificial dielectric layer subsequently, and the damage probability of the protective layer 160 in the process of removing the sacrificial dielectric layer is low.

Moreover, the protection layer 160 is remained in the semiconductor structure, and thus, the material of the protection layer 160 is an insulating material. In addition, the protection layer 160 is also located between the source drain contact layer 140 and the gate structure 110, the protection layer 160 also affects the effective capacitance between the source drain contact layer 140 and the gate structure 110, and the dielectric constant (K value) of the material of the protection layer 150 cannot be too high.

In this embodiment, the material of the protection layer 160 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, boron carbonitride, aluminum oxide, and aluminum nitride. As an example, the material of the protection layer 160 is silicon nitride.

It should be noted that the thickness of the protection layer 160 is not too small, otherwise the protection effect on the sidewalls and the bottom of the gap 150 is easily reduced; the protection layer 160 is also located between the source-drain contact layer 140 and the gate structure 110, the protection layer 160 may also affect the effective capacitance between the source-drain contact layer 140 and the gate structure 110, and the larger the thickness of the protection layer 160 is, the larger the influence on the effective capacitance between the source-drain contact layer 140 and the gate structure 110 is, so the thickness of the protection layer 160 should not be too large, and meanwhile, the too large thickness of the protection layer 160 may easily fill the gap 150, or cause the remaining space of the gap 150 to be too small. For this reason, in the present embodiment, the thickness of the protection layer 160 is 10% to 90% of the width of the gap 150 in the direction perpendicular to the sidewall of the gate structure 110.

Specifically, in the present embodiment, the thickness of the protection layer 160 is 1nm to 10 nm. The thickness of the protection layer 160 is smaller, which is beneficial to making the remaining space of the gap 150 larger, and further beneficial to making the size of the subsequent air gap larger, and is beneficial to making the reduction effect of the effective capacitance between the source-drain contact layer 140 and the gate structure 110 more obvious, and further beneficial to further improving the performance of the semiconductor structure.

In this embodiment, the process of forming the protection layer 160 includes an atomic layer deposition process. The thickness of the protection layer 160 is small, and by adopting the atomic layer deposition process, the protection layer 160 with a small thickness is easily formed, and the thickness uniformity and the density of the protection layer 160 are good, in addition, the protection layer 160 has good step coverage capability, and the adhesion effect of the protection layer 160 on the bottom and the side wall of the gap 150 is further improved.

It should be noted that the step coverage capability of the atomic layer deposition process is good, and therefore, in the step of forming the protection layer 160, the protection layer 160 is further formed on the top surfaces of the bottom dielectric layer 130, the source-drain contact layer 140, and the gate capping layer 115.

Referring to fig. 19, in the embodiment, after forming the protection layer 160, the method for forming the semiconductor structure further includes: a sacrificial medium layer 180 is formed on the bottom medium layer 130, and the sacrificial medium layer 180 is further formed in the gap 150 and covers the gate structure 110 and the source-drain contact layer 140.

The sacrificial dielectric layer 180 is used to provide a process foundation for the subsequent formation of source drain plugs and gate plugs. Specifically, a source-drain plug penetrating through the sacrificial medium layer 180 and corresponding to the source-drain contact layer 140 and a gate plug contacting the gate structure 110 are formed subsequently, and the sacrificial medium layer 180 is used for providing a supporting function for forming the source-drain plug and the gate plug.

The sacrificial dielectric layer 180 is made of an insulating material. Moreover, the sacrificial medium layer 180 is removed subsequently, so that the sacrificial medium layer 180 is made of a material which is easy to etch, so as to reduce the difficulty of removing the sacrificial medium layer 180 subsequently, and in addition, the sacrificial medium layer 180 is made of a material which has a higher etching selection ratio with the protection layer 160, so that the protection layer 160 is not easy to be subjected to false etching by the subsequent process of removing the sacrificial medium layer 180, and the protection effect of the protection layer 160 on the side wall and the bottom of the gap 150 is further ensured.

The material of the sacrificial dielectric layer 180 includes one or more of silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, boron carbonitride, aluminum oxide, and aluminum nitride. In this embodiment, the sacrificial dielectric layer 180 is made of silicon oxide.

In this embodiment, the process of forming the sacrificial dielectric layer 180 includes: one or more of a flow type chemical vapor deposition process, an atomic layer deposition process, a spin coating process and a chemical vapor deposition process.

Referring to fig. 20, a source/drain plug 210 penetrating through the sacrificial medium layer 180 on the top of the source/drain contact layer 140 is formed to contact the source/drain contact layer 140.

The source drain plug 210 is in contact with the source drain contact layer 140, and is used for realizing electrical connection between the source drain doped region 120 and an external circuit or other interconnection structures. In this embodiment, the step of forming the source/drain plug 180 includes: forming source and drain contact holes (not shown) penetrating the sacrificial dielectric layer 180 on the top of the source and drain contact layer 140; source drain plugs 210 are formed in the source drain contact holes.

In other embodiments, when an active drain capping layer is further formed on the top of the source-drain contact layer in the step of forming the source-drain contact layer, the source-drain plug correspondingly penetrates through the source-drain capping layer.

With continuing reference to fig. 20, in this embodiment, the forming method further includes: after the sacrificial medium layer 180 is formed and before the sacrificial medium layer 180 is removed, a gate plug 220 penetrating the sacrificial medium layer 180 at the top of the gate structure 110 is formed and contacts the gate structure 110. The gate plug 220 is used to electrically connect the gate structure 110 with an external circuit or other interconnect structure.

In this embodiment, in the step of forming the gate plug 220, the gate plug 220 contacts the top of the gate structure 110 of the active region, and the gate plug 110 correspondingly penetrates through the gate capping layer 115.

In this embodiment, the gate plug 220 is formed above the gate structure 110 in the active region, and the gate plug 220 is correspondingly an active gate contact hole plug (COAG), so as to be beneficial to saving the area of the chip and further reducing the chip size.

It should be noted that, in the present embodiment, the gate plug 220 is formed before the sacrificial dielectric layer 180 is removed, so that the modification of the current process is reduced, and the process compatibility of the forming method is improved.

In this embodiment, the gate plug 220 also penetrates the protection layer 160 on the gate capping layer 115.

Specifically, the step of forming the gate plug 220 includes: forming a gate contact hole (not shown) penetrating the gate capping layer 115 and the sacrificial dielectric layer 180 at the top of the gate structure 110; the gate plug 220 is formed in the gate contact hole.

In this embodiment, after the source-drain contact hole and the gate contact hole are formed, in the same step, a conductive material is filled in the source-drain contact hole and the gate contact hole to form the source-drain plug 210 and the gate plug 220. Accordingly, the gate plug 220 and the source drain plug 210 are the same material.

For a specific description of the materials of the gate plug 220 and the source drain plug 210, reference may be made to the foregoing description of the source drain contact layer 140, and details are not repeated here.

It should be noted that, in this embodiment, after the source-drain contact hole and the gate contact hole are formed, and before the conductive material is filled in the source-drain contact hole and the gate contact hole, the forming method further includes: a second adhesion layer 230 is formed on the bottom and sidewall of the source-drain contact hole and the bottom and sidewall of the gate contact hole. The gate plugs 220 and the source and drain plugs 210 are correspondingly formed on the second adhesion layer 230.

The second adhesion layer 230 is used to improve adhesion between the gate plug 220 and the top dielectric layer 170, and improve adhesion between the source/drain plug 210 and the top dielectric layer. In this embodiment, the second adhesion layer 230 is further used as a diffusion barrier layer for preventing the materials of the gate plug 220 and the source/drain plug 210 from diffusing into the sacrificial medium layer 180 or the top medium layer, so as to improve the problem of electromigration; moreover, the second adhesion layer 230 is also used to prevent impurities such as carbon atoms and oxygen atoms in the sacrificial dielectric layer 180 or the top dielectric layer from diffusing into the gate plug 220 and the source/drain plug 210, which are both beneficial to improving the reliability of the semiconductor structure. In other embodiments, the second adhesion layer may also be used as the adhesion layer only, depending on the actual process requirements.

It should be further noted that, after forming the gate plug 220 and the source-drain plug 210, the forming method further includes: a third adhesion layer 240 is formed on top of the gate plug 220 and the source-drain plugs 210.

An inter-metal dielectric (IMD) layer is further formed on the top of the gate plug 220 and the top of the source-drain plug 210, and the third adhesion layer 240 is used for protecting the top of the gate plug 220 and the top of the source-drain plug 210 and improving adhesion between the gate plug 220 and the inter-metal dielectric layer and between the source-drain plug 210 and the inter-metal dielectric layer. In this embodiment, the third adhesion layer 240 can also be used as a diffusion barrier layer, which is beneficial to improve electromigration.

For the specific description of the materials of the second adhesion layer 230 and the third adhesion layer 240, reference may be made to the corresponding description of the first adhesion layer 145, and the description of this embodiment is not repeated herein.

Referring to fig. 21, after the source/drain plugs 210 are formed, the sacrificial medium layer 180 is removed to expose the gap 150. The gap 150 is exposed so that the top dielectric layer seals the gap 150 to form an air gap when the top dielectric layer is subsequently formed on the bottom dielectric layer 130.

In this embodiment, the protection layer 160 has an integrated structure, and the sealing property and the density of the protection layer 160 are higher, which is beneficial to preventing the etching gas or solution of the etching process from causing the false etching on the protection layer 160, thereby improving the protection effect of the protection layer 160 on the sidewall and the bottom of the gap 150.

Specifically, in the present embodiment, the process for removing the sacrificial medium layer 180 has a higher etching selectivity ratio for the sacrificial medium layer 180 and the protection layer 160, so that the protection layer 160 is used as an etching stop layer to remove the sacrificial medium layer 180.

In this embodiment, the process of removing the sacrificial dielectric layer 180 includes one or both of a dry etching process and a wet etching process. As an example, the sacrificial dielectric layer 180 is removed by sequentially using a dry etching process and a wet etching process. The dry etching process is an isotropic dry etching process so as to remove the sacrificial dielectric layer 180 cleanly, and the etching selection ratio and the etching efficiency of the dry etching process are high; the wet etching process also has the characteristic of isotropic etching, which is beneficial to further ensuring that the sacrificial medium layer 180 does not remain.

Referring to fig. 22, after the protective layer 160 is formed, a top dielectric layer 170 is formed on the bottom dielectric layer 130, and the top dielectric layer 170 seals the gap 150 to form an air gap 200.

Top dielectric layer 170 is used to seal gap 150. The air gap 200 has a dielectric constant lower than that of a commonly used dielectric material (e.g., a low-k dielectric material or an ultra-low-k dielectric material) in a semiconductor process, so that the effective capacitance between the gate structure 110 and the source-drain contact layer 140 is reduced, the RC delay is reduced, and the performance of the semiconductor structure is improved.

As can be seen from the foregoing description, the gap 150 formed in the present embodiment has a larger space, and the protection layer 160 is formed after the gap 150 is formed, so that the remaining space of the gap 150 is larger by adjusting the thickness of the protection layer 160, and accordingly, when the top dielectric layer 170 for sealing the gap 150 is formed, the size of the air gap 200 enclosed by the top dielectric layer 170 and the gap 150 is larger, which is favorable for providing a lower dielectric constant between the gate structure 110 and the source-drain contact layer 140, and is favorable for further improving the performance of the semiconductor structure.

In this embodiment, in the step of forming the top dielectric layer 170, the top dielectric layer 170 is formed between the source-drain plugs 210. Specifically, the top dielectric layer 170 is formed between the gate plug 220 and the source drain plug 210. Correspondingly, in this embodiment, the top dielectric layer 170 is further used to realize electrical isolation between the source-drain plugs 210 and the gate plugs 220.

In this embodiment, in a direction perpendicular to the extending direction of the gate structure 110, the cross sections of the gate plug 220 and the source-drain plug 210 are both of an inverted trapezoid structure with a large top and a small bottom, and in the process of forming the top dielectric layer 170, with the increase of the deposition thickness of the material of the top dielectric layer 170, before the material of the top dielectric layer 170 fills the gap 150, the materials of the top dielectric layer 170 at the top corners of the gate plug 220 and the source-drain plug 210 gradually contact each other, so that the gap 150 is sealed, and the air gap 200 is formed.

As shown in fig. 22, in this embodiment, the air gaps 200 are further located between the gate plug 220 and the source-drain contact layer 140, and between the gate plug 220 and the source-drain plug 210, so that the parasitic capacitance between the gate plug 220 and the source-drain contact layer 140, and between the gate plug 220 and the source-drain plug 210, and the RC delay are reduced, thereby improving the performance of the semiconductor structure.

In this embodiment, the gate plug 220 is an active gate contact via plug (COAG), and compared with a conventional gate plug located in an isolation region, the distance between the gate plug 220 and the source-drain contact layer 140 or the source-drain plug 210 in this embodiment is closer, and by making the air gaps 200 also located between the gate plug 220 and the source-drain contact layer 140, and between the gate plug 220 and the source-drain plug 210, it is beneficial to significantly reduce parasitic capacitance between the gate plug 220 and the source-drain contact layer 140, and between the gate plug 220 and the source-drain plug 210, and reduce the RC delay problem, thereby significantly improving the performance of the semiconductor structure.

In this embodiment, a deposition process with a weak filling capability is used to form the top dielectric layer 170, so that the top dielectric layer 170 is not easily filled into the gap 150, and the top dielectric layer 170 is easily contacted with the top of the gap 150 to form the air gap 200.

As an example, the process of forming the top dielectric layer 170 is a chemical vapor deposition process. In particular, the chemical vapor deposition process may be a plasma enhanced chemical vapor deposition process.

In this embodiment, the top dielectric layer 170 is flush with the tops of the gate plug 220 and the source/drain plug 210 as an example. In other embodiments, the top of the top dielectric layer may be lower than the tops of the gate plug and the source drain plug. In other embodiments, the top dielectric layer may further cover the top of the gate plug and the top of the source-drain plug, and the top dielectric layer on the top of the gate plug and the top of the source-drain plug may be used as an inter-metal dielectric layer of a next interconnect structure, which is beneficial to improving compatibility with a subsequent process and simplifying a process.

In this example, a COAG process is described as an example. In other embodiments, when the gate plug is located at the top of the gate structure of the isolation region, the method for forming the semiconductor structure provided by the embodiment can still achieve the effect of reducing the effective capacitance between the gate structure and the source-drain contact layer and the parasitic capacitance between the gate plug and the source-drain contact layer or the source-drain plug.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A semiconductor structure, comprising:

a substrate;

the grid structure is positioned on the substrate;

the source-drain doped region is positioned in the substrate at two sides of the grid structure;

the bottom dielectric layer is positioned on the substrate at the side part of the grid structure and covers the source drain doped region, and a gap is formed between the bottom dielectric layer and the side wall of the grid structure;

the source-drain contact layer penetrates through the bottom dielectric layer at the top of the source-drain doped region and is in contact with the source-drain doped region;

a gap between the sidewall of the gate structure and the source/drain contact layer;

the protective layer is covered on the side wall and the bottom of the gap in a shape-preserving manner, and the protective layer is of an integrated structure;

and the top dielectric layer is positioned on the bottom dielectric layer, seals the gap and forms an air gap with the gap in a surrounding manner.

2. The semiconductor structure of claim 1, further comprising:

the source drain plug is positioned at the top of the source drain contact layer and is in contact with the source drain contact layer;

and the top dielectric layer is positioned between the source drain plugs.

3. The semiconductor structure of claim 2, further comprising:

the grid plug is positioned at the top of the grid structure and is in contact with the grid structure;

the top dielectric layer is positioned between the grid plug and the source drain plug.

4. The semiconductor structure of claim 3, wherein the gate plug contacts a top portion of the gate structure of an active region;

the semiconductor structure further includes: the grid electrode cap layer is positioned between the top of the grid electrode structure and the top dielectric layer;

the gate plug penetrates through the gate cap layer.

5. The semiconductor structure of claim 4, further comprising: the source-drain cap layer is positioned between the top dielectric layer and the source-drain contact layer; and the source drain plug penetrates through the source drain cap layer.

6. The semiconductor structure of claim 1, wherein a material of the protective layer comprises one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, boron carbonitride, aluminum oxide, and aluminum nitride.

7. The semiconductor structure of claim 1, wherein the gap has a width in a direction perpendicular to the gate structure sidewalls of 2nm to 15 nm.

8. The semiconductor structure of claim 1, wherein a thickness of the protective layer in a direction perpendicular to sidewalls of the gate structure is 10% to 90% of the gap width.

9. The semiconductor structure of claim 1, wherein the protective layer has a thickness of 1nm to 10 nm.

10. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein a grid structure is formed on the substrate, a side wall is formed on the side wall of the grid structure, source and drain doped regions are formed in the substrate at two sides of the grid structure, a bottom dielectric layer is formed on the side parts of the grid structure and the side wall and covers the source and drain doped regions, and source and drain contact layers penetrating through the bottom dielectric layer are formed at two sides of the grid structure and the side wall and are in contact with the source and drain doped regions;

removing the side wall, and forming a gap between the side wall of the grid structure and the source drain contact layer;

forming a protective layer conformally covering the bottom and the side wall of the gap;

and after the protective layer is formed, forming a top dielectric layer on the bottom dielectric layer, wherein the top dielectric layer seals the gap to form an air gap.

11. The method of forming a semiconductor structure of claim 10, wherein after forming the protective layer and before forming the top dielectric layer, the method of forming a semiconductor structure further comprises: forming a sacrificial medium layer on the bottom medium layer, wherein the sacrificial medium layer is also formed in the gap and covers the grid structure and the source drain contact layer;

forming a source drain plug penetrating through the sacrificial medium layer on the top of the source drain contact layer and contacting with the source drain contact layer;

after the source drain plug is formed, removing the sacrificial medium layer to expose the gap;

in the step of forming the top dielectric layer, the top dielectric layer is formed between the source drain plugs.

12. The method of forming a semiconductor structure of claim 11, further comprising: after the sacrificial medium layer is formed and before the sacrificial medium layer is removed, a grid plug penetrating through the sacrificial medium layer on the top of the grid structure is formed and is in contact with the grid structure;

in the step of forming the top dielectric layer, the top dielectric layer is formed between the gate plug and the source drain plug.

13. The method of forming a semiconductor structure of claim 12, wherein in the step of providing a substrate, a gate cap layer is further formed on top of the gate structure;

and in the step of forming the gate plug, the gate plug is in contact with the top of the gate structure of the active region, and the gate plug penetrates through the gate cap layer.

14. The method for forming the semiconductor structure according to claim 12 or 13, wherein in the step of providing the substrate, a source drain cap layer is further formed on top of the source drain contact layer;

and in the step of forming the source and drain plug, the source and drain plug penetrates through the source and drain cap layer.

15. The method for forming a semiconductor structure of claim 10, wherein the step of providing the substrate, the gate structure, the sidewall spacer, the source and drain doped region, the bottom dielectric layer, and the source and drain contact layer comprises: providing a substrate;

forming a pseudo gate structure on the substrate;

forming the side wall positioned on the side wall of the pseudo gate structure and source drain doped regions positioned in the substrates at two sides of the pseudo gate structure;

forming the bottom dielectric layer on the substrate at the side parts of the pseudo gate structure and the side wall to cover the source-drain doped region;

forming a source drain contact layer, penetrating through the bottom dielectric layer on the top of the source drain doped region and contacting with the source drain doped region;

removing the pseudo gate structure, and forming a gate opening in the bottom dielectric layer;

forming the gate structure in the gate opening.

16. The method for forming the semiconductor structure according to claim 15, wherein the step of forming the sidewall spacers and the source-drain doped regions comprises: after the pseudo gate structure is formed, forming a first side wall on the side wall of the pseudo gate structure;

forming the source-drain doped region in the substrate on the two sides of the dummy gate structure and the first side wall;

and after the source-drain doped region is formed, forming a second side wall on the side wall of the first side wall, wherein the first side wall and the second side wall positioned on the first side wall are used as the side walls.

17. The method of forming a semiconductor structure of claim 10, wherein the process of forming the protective layer comprises an atomic layer deposition process.

18. The method of claim 10, wherein in the step of forming the protective layer, the protective layer has a thickness of 10% to 90% of a width of the gap in a direction perpendicular to sidewalls of the gate structure.

19. The method of forming a semiconductor structure according to claim 10, wherein in the step of forming the protective layer, the protective layer has a thickness of 1nm to 10 nm.

20. The method for forming a semiconductor structure according to claim 10, wherein in the step of forming the protective layer, the protective layer is of an integral structure.

21. The method of forming a semiconductor structure of claim 10, wherein in the step of forming the protective layer, the material of the protective layer comprises one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, boron carbonitride, aluminum oxide, and aluminum nitride.

22. The method of claim 10, wherein in the step of providing the substrate, the sidewall has a thickness of 2nm to 15nm in a direction perpendicular to the sidewall of the gate structure.

23. The method of claim 10, wherein the material of the sidewall spacers comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, boron nitride, silicon oxycarbonitride, silicon oxyboride, aluminum oxide, and aluminum nitride.

24. The method for forming a semiconductor structure according to claim 10, wherein the process for removing the sidewall spacers comprises one or both of a dry etching process and a wet etching process.

25. The method of claim 11, wherein the process of forming the sacrificial dielectric layer comprises: one or more of a flow type chemical vapor deposition process, an atomic layer deposition process, a spin coating process and a chemical vapor deposition process.

26. The method of claim 11, wherein in the step of forming the sacrificial dielectric layer, the material of the sacrificial dielectric layer comprises one or more of silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, boron carbonitride, aluminum oxide, and aluminum nitride.

27. The method of claim 11, wherein the process of removing the sacrificial dielectric layer comprises one or both of a dry etch and a wet etch process.

28. The method of claim 10, wherein the process of forming the top dielectric layer is a chemical vapor deposition process.