CN114551358A - Top layer p-type diamond MOSFET and GaN HEMT monolithic heterogeneous integrated structure and preparation method thereof - Google Patents
Top layer p-type diamond MOSFET and GaN HEMT monolithic heterogeneous integrated structure and preparation method thereof Download PDFInfo
- Publication number
- CN114551358A CN114551358A CN202210090222.1A CN202210090222A CN114551358A CN 114551358 A CN114551358 A CN 114551358A CN 202210090222 A CN202210090222 A CN 202210090222A CN 114551358 A CN114551358 A CN 114551358A
- Authority
- CN
- China
- Prior art keywords
- layer
- type diamond
- substrate
- mosfet
- integrated structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910003460 diamond Inorganic materials 0.000 title claims abstract description 97
- 239000010432 diamond Substances 0.000 title claims abstract description 97
- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 77
- 238000000034 method Methods 0.000 claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 claims abstract description 28
- 238000005530 etching Methods 0.000 claims abstract description 27
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 19
- 230000004888 barrier function Effects 0.000 claims abstract description 18
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 238000000231 atomic layer deposition Methods 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 3
- 230000010354 integration Effects 0.000 abstract description 4
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 230000017525 heat dissipation Effects 0.000 abstract description 2
- 230000020169 heat generation Effects 0.000 abstract description 2
- FFEARJCKVFRZRR-UHFFFAOYSA-N methionine Chemical compound CSCCC(N)C(O)=O FFEARJCKVFRZRR-UHFFFAOYSA-N 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 30
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 22
- 239000003292 glue Substances 0.000 description 12
- 229910021642 ultra pure water Inorganic materials 0.000 description 12
- 239000012498 ultrapure water Substances 0.000 description 12
- 229910052757 nitrogen Inorganic materials 0.000 description 11
- 238000010586 diagram Methods 0.000 description 9
- 238000001259 photo etching Methods 0.000 description 9
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 8
- 238000005566 electron beam evaporation Methods 0.000 description 8
- 238000004026 adhesive bonding Methods 0.000 description 7
- 239000007789 gas Substances 0.000 description 7
- 238000009616 inductively coupled plasma Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 6
- 238000004528 spin coating Methods 0.000 description 6
- 238000005406 washing Methods 0.000 description 6
- 238000000137 annealing Methods 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 5
- 238000001035 drying Methods 0.000 description 5
- 238000001883 metal evaporation Methods 0.000 description 5
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 4
- 238000000861 blow drying Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000009987 spinning Methods 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 210000002469 basement membrane Anatomy 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 238000011010 flushing procedure Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000001534 heteroepitaxy Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000010926 purge Methods 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004506 ultrasonic cleaning Methods 0.000 description 2
- 229910001868 water Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 238000007605 air drying Methods 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000007865 diluting Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- -1 i.e. Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3732—Diamonds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention discloses a top layer p-type diamond MOSFET and GaN HEMT monolithic heterogeneous integrated structure and a preparation method thereof, wherein the method comprises the following steps: providing an epitaxial product, and sequentially growing a SiN dielectric layer and a p-type diamond layer on the surface of one side, away from the substrate, of the AlGaN barrier layer; etching the SiN dielectric layer to remove part of the p-type diamond layer, etching a source electrode groove and a drain electrode groove in the SiN dielectric layer, and manufacturing a first source electrode and a first drain electrode of the HMET device; manufacturing a second source electrode and a second drain electrode of the MOSFET device on the surface of the p-type diamond layer; depositing Al on the surface of the p-type diamond layer2O3Forming a gate dielectric layer; and manufacturing a second gate electrode on the surface of the gate dielectric layer to form a monolithic heterogeneous integrated structure of the top layer p-type diamond MOSFET and the GaN HEMT. The invention is beneficial to reducing the volume of the device and improving the integration level of the device; at the same time modulate GaThe heat generation of N HEMTs is distributed, and the heat dissipation capacity of the device is improved.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a top layer p-type diamond MOSFET and GaN HEMT monolithic heterogeneous integrated structure and a preparation method thereof.
Background
In recent years, the third-generation semiconductor material GaN has the advantages of wide forbidden band width, high breakdown electric field, high electronic saturation velocity and the like, so that the third-generation semiconductor material GaN has unique advantages in high-frequency and high-power fields such as military affairs, aerospace, communication and the like. However, when the ultra-high integration level of the semiconductor device and the GaN-based device are applied in the high-frequency field, the accompanying high heat generation phenomenon cannot be ignored, and the self-heating effect accumulation of the device not only degrades the basic performances of the device such as saturation current, transconductance and the like, but also can cause the device to fail in a more serious case.
The thermal conductivity of GaN itself is only 130W/(m · K) (watt/meter · kelvin), and the substrates commonly used in GaN HEMTs at present mainly include SiC substrates, Si substrates, sapphire substrates, and the like. Even if a SiC substrate with higher thermal conductivity is used, the heat dissipation performance of the SiC substrate can not meet the application of the GaN effect tube in the microwave high-power field. In addition, the maximum working temperature of a silicon-based MOSFET device in the current logic circuit is 125 ℃, the electrical performance of the silicon-based MOSFET device exceeding the working temperature is greatly degraded and even completely failed, and the working temperature of the device applied to the high-frequency high-power field is far higher than 125 ℃. Therefore, new material systems and device structures are needed to solve the thermal problems faced by current GaN devices, as well as the high temperature application problems of the circuits.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a top layer p-type diamond MOSFET and GaN HEMT monolithic heterogeneous integrated structure and a preparation method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:
in a first aspect, the invention provides a method for preparing a monolithic heterogeneous integrated structure of a top layer p-type diamond MOSFET and a GaN HEMT, which comprises the following steps:
providing a substrate, and growing an epitaxial structure on the surface of the substrate, wherein the epitaxial structure comprises a GaN buffer layer and an AlGaN barrier layer which are grown on the surface of the substrate in sequence;
growing an SiN medium layer on the surface of the AlGaN barrier layer, which is far away from one side of the substrate, and growing a p-type diamond layer on the surface of the SiN medium layer, which is far away from one side of the substrate;
etching a source electrode groove and a drain electrode groove on the exposed SiN medium layer after etching and removing part of the p-type diamond layer, manufacturing a first source electrode of the HEMT device in the source electrode groove, and manufacturing a first drain electrode of the HEMT device in the drain electrode groove; wherein the etched p-type diamond layer includes a first sub-portion and a second sub-portion;
manufacturing a second source electrode and a second drain electrode of the MOSFET device on the surface of the p-type diamond layer on the side far away from the substrate;
depositing Al on the surface of the p-type diamond layer far away from the substrate side2O3Forming a gate dielectric layer;
manufacturing a first gate electrode of the HEMT device on the surface of one side of the exposed SiN dielectric layer, which is far away from the substrate; the first sub-part is contacted with the first gate electrode, and the orthographic projection of the first sub-part is positioned between the orthographic projection of the first gate electrode and the orthographic projection of the first drain electrode along the direction vertical to the plane of the substrate; the orthographic projections of the second source electrode and the second drain electrode are both located within the orthographic projection of the second sub-portion;
and manufacturing a second gate electrode on the surface of one side of the gate dielectric layer, which is far away from the substrate, so as to form the monolithic heterogeneous integrated structure of the top layer p-type diamond MOSFET and the GaN HEMT.
In an embodiment of the present invention, the step of growing the SiN dielectric layer on the surface of the AlGaN barrier layer on the side away from the substrate includes:
growing an SiN medium layer on the surface of the AlGaN barrier layer, which is far away from one side of the substrate, by utilizing an MOCVD (metal organic chemical vapor deposition) process; the thickness of the SiN medium layer is 5-20 nm in the direction perpendicular to the plane of the substrate.
In an embodiment of the present invention, the step of growing the p-type diamond layer on the surface of the SiN dielectric layer on the side away from the substrate includes:
by means of H2Diluted CH4Providing a source of C and passing H through the gas phase2Diluted B (CH)3)3And depositing a p-type diamond layer on the surface of the SiN dielectric layer far away from the substrate by using a Microwave Plasma Chemical Vapor Deposition (MPCVD) process under the conditions that the C is equal to 1000ppm, the air pressure is 25torr, the microwave power is 750W, the substrate temperature is 750-800 ℃, and the total gas flow is 400 sccm.
In one embodiment of the invention, the thickness of the p-type diamond layer is 500-1000 nm along the direction vertical to the plane of the substrate.
In one embodiment of the present invention, the deposition rate of the p-type diamond layer is 0.13 to 0.2 μm/h.
In one embodiment of the invention, Al is deposited on the surface of the p-type diamond layer on the side far away from the substrate2O3And forming a gate dielectric layer, which comprises the following steps:
by using an Atomic Layer Deposition (ALD) process of a coating process, H is alternately introduced in a pulse mode at the temperature of 300 DEG C2O and TMA, Al is grown on the surface of the side of the p-type diamond layer far away from the substrate2O3；
Etching to remove Al outside the MOSFET active region2O3And forming a gate dielectric layer.
In one embodiment of the invention, Al is in a direction perpendicular to the plane of the substrate2O3The thickness of (a) is 5to 20 nm.
In a second aspect, the invention provides a monolithic heterogeneous integrated structure of a top layer p-type diamond MOSFET and a GaN HEMT, which is prepared by the preparation method of the monolithic heterogeneous integrated structure of the top layer p-type diamond MOSFET and the GaN HEMT.
Compared with the prior art, the invention has the beneficial effects that:
1. according to the invention, after the p-type diamond layer is heteroepitaxially grown on the top of the epitaxial substrate, part of the p-type diamond layer is removed by graphical etching, and the GaN HEMT device based on the epitaxial substrate is manufactured, so that the high thermal conductivity of the diamond material can be utilized to modulate a thermal field, and the junction temperature of the GaN HEMT device can be effectively reduced.
2. According to the invention, the p-type diamond layer is grown on the top heteroepitaxy, and the MOSFET device based on the p-type diamond is manufactured, so that the heterogeneous integration of the GaN electronic conducting device and the diamond hole conducting device is realized, the GaN electronic conducting device can be applied to a high-temperature logic circuit, and the problem that the logic circuit based on the Si device in the prior art can not be applied when the temperature is higher than 125 ℃ is solved.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a flow chart of a method for fabricating a monolithic heterogeneous integrated structure of a top layer p-type diamond MOSFET and a GaN HEMT according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a method for fabricating a monolithic heterogeneous integrated structure of a top layer p-type diamond MOSFET and a GaN HEMT according to an embodiment of the invention;
FIG. 3 is another schematic diagram of a method for fabricating a monolithic hetero-integrated structure of a top layer p-type diamond MOSFET and a GaN HEMT according to an embodiment of the invention;
FIG. 4 is another schematic diagram of a method of fabricating a monolithic hetero-integrated structure of a top layer p-type diamond MOSFET and a GaN HEMT according to an embodiment of the invention;
FIG. 5 is another schematic diagram of a method of fabricating a monolithic hetero-integrated structure of a top layer p-type diamond MOSFET and a GaN HEMT according to an embodiment of the invention;
FIG. 6 is another schematic diagram of a method of fabricating a monolithic hetero-integrated structure of a top layer p-type diamond MOSFET and a GaN HEMT according to an embodiment of the invention;
FIG. 7 is another schematic diagram of a method of fabricating a monolithic hetero-integrated structure of a top layer p-type diamond MOSFET and a GaN HEMT according to an embodiment of the invention;
FIG. 8 is another schematic diagram of a method of fabricating a monolithic hetero-integrated structure of a top layer p-type diamond MOSFET and a GaN HEMT according to an embodiment of the invention;
fig. 9 is another schematic diagram of a method for manufacturing a monolithic heterogeneous integrated structure of a top layer p-type diamond MOSFET and a GaN HEMT according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Fig. 1 is a flowchart of a method for manufacturing a monolithic hetero-integrated structure of a top layer p-type diamond MOSFET and a GaN HEMT according to an embodiment of the present invention, and fig. 2 to 9 are schematic diagrams of a method for manufacturing a monolithic hetero-integrated structure of a top layer p-type diamond MOSFET and a GaN HEMT according to an embodiment of the present invention. Referring to fig. 1 to 9, an embodiment of the invention provides a method for manufacturing a monolithic heterogeneous integrated structure of a top p-type diamond MOSFET and a GaN HEMT, including:
s1, providing a substrate, and growing an epitaxial structure on the surface of the substrate, wherein the epitaxial structure comprises a GaN buffer layer and an AlGaN barrier layer which are sequentially grown on the surface of the substrate;
s2, growing an SiN medium layer on the surface of the AlGaN barrier layer, which is far away from the substrate, and growing a p-type diamond layer on the surface of the SiN medium layer, which is far away from the substrate;
s3, after removing part of the p-type diamond layer through etching, etching a source electrode groove and a drain electrode groove on the exposed SiN dielectric layer, manufacturing a first source electrode S1 of the HEMT device in the source electrode groove, and manufacturing a first drain electrode D1 of the HEMT device in the drain electrode groove; wherein the etched p-type diamond layer includes a first sub-portion A1 and a second sub-portion A2;
s4, manufacturing a second source electrode S2 and a second drain electrode D2 of the MOSFET device on the surface of the side, away from the substrate, of the p-type diamond layer;
s5, depositing Al on the surface of the side, away from the substrate, of the p-type diamond layer2O3Forming a gate dielectric layer;
s6, manufacturing a first gate electrode G1 of the HEMT device on the surface of one side, away from the substrate, of the exposed SiN dielectric layer; the first sub-part is contacted with the first gate electrode, and the orthographic projection of the first sub-part is positioned between the orthographic projection of the first gate electrode and the orthographic projection of the first drain electrode along the direction vertical to the plane of the substrate; the orthographic projections of the second source electrode and the second drain electrode are both positioned in the orthographic projection of the second sub-part;
s7, manufacturing a second gate electrode G2 on the surface of the side, far away from the substrate, of the gate dielectric layer, and forming a monolithic heterogeneous integrated structure of the top-layer p-type diamond MOSFET and the GaN HEMT.
In this embodiment, an AlGaN/GaN epitaxial structure based on a diamond substrate is taken as an example, and specifically, as shown in fig. 2 to 3, an epitaxial structure is grown on the surface of the diamond substrate, and the epitaxial structure includes a GaN buffer layer located on one side of the substrate and an AlGaN barrier layer located on one side of the GaN buffer layer away from the substrate. And sequentially growing SiN dielectric layers on the surfaces of the AlGaN barrier layers, which are far away from the substrate. Then, cleaning the surface of the sample; illustratively, the sample is firstly put into an acetone solution for ultrasonic cleaning for 3 mm, the ultrasonic intensity is 3.0, then the sample is put into a stripping solution with the temperature of 60 ℃ for water bath heating for 5min, then the sample is sequentially put into the acetone solution and an ethanol solution for ultrasonic cleaning for 3min, the ultrasonic intensity is 3.0, the sample is washed by ultrapure water and dried by nitrogen. And after the surface of the sample is cleaned, growing a p-type diamond layer on the SiN medium layer.
As shown in fig. 2, in step S2, the step of growing a SiN dielectric layer on the surface of the AlGaN barrier layer on the side away from the substrate includes:
growing an SiN medium layer on the surface of the AlGaN barrier layer, which is far away from the substrate, by utilizing an MOCVD (metal organic chemical vapor deposition) process; the thickness of the SiN dielectric layer is 5-20 nm in the direction perpendicular to the plane of the substrate.
With continued reference to fig. 3, in step S2, the step of growing a p-type diamond layer on the surface of the SiN dielectric layer on the side away from the substrate includes:
by means of H2Diluted CH4Providing a source of C and passing H through the gas phase2Diluted B (CH)3)3And depositing a p-type diamond layer on the surface of the SiN dielectric layer far away from the substrate by using a Microwave Plasma Chemical Vapor Deposition (MPCVD) process.
Specifically, 0.3% CH was used4Providing a source of C, and using H2Diluting by adding hydrogen peroxide to the gas phase2Diluted B (CH)3)3Controlling the boron content to ensure that the B, C and the P-type diamond layer are deposited at a deposition rate of 0.13-0.2 mu m/h under the conditions that the gas pressure is 1000ppm, the gas pressure is 25torr, the microwave power is 750W, the substrate temperature is 750-800 ℃, and the total gas flow is 400 sccm.
Optionally, the thickness of the p-type diamond layer is 500-1000 nm in the direction perpendicular to the plane of the substrate.
As shown in fig. 4 to 5, in step S3, after etching and removing part of the diamond layer, etching a source electrode groove and a drain electrode groove in the exposed SiN dielectric layer, and fabricating a first source electrode of the HEMT device in the source electrode groove and a first drain electrode of the HEMT device in the drain electrode groove, the steps include:
s301, placing the sample on a hot plate at 200 ℃ for baking for 5min, then performing gluing and spin coating of photoresist, and placing the sample on a hot plate at 90 ℃ for baking lmin; and then, putting the sample into a photoetching machine to expose the photoresist in the region needing to be removed in the p-type diamond layer, after exposure is finished, putting the sample into a developing solution to remove the photoresist in the p-type diamond layer in the exposed region, and carrying out ultra-pure water washing and nitrogen blow-drying on the photoresist.
Further, etching the p-type diamond layer in the exposure area; specifically, the p-type diamond layer in the exposure area is etched by utilizing an ICP (inductively coupled plasma) process to expose the SiN medium layer below, then the sample is sequentially placed into an acetone solution, a stripping liquid, an acetone solution and an ethanol solution for cleaning, and is washed by using ultrapure water and dried by using nitrogen. As shown in fig. 4, after removing a portion of the p-type diamond layer, the remaining p-type diamond layer includes the first sub-portion a1 and the second sub-portion a 2.
S302, after removing part of the p-type diamond layer through etching, etching the SiN medium layers corresponding to the first source electrode area and the first drain electrode area to the AlGaN barrier layer to form a source electrode groove and a drain electrode groove.
Illustratively, the sample is first baked on a hot plate at 200 ℃ for 5 min; then, gluing and spin coating the photoresist, and placing the sample on a hot plate at 90 ℃ for baking lmin; then, putting the sample into a photoetching machine to expose the photoresist in the source electrode and drain electrode areas; finally, the sample after completing the exposure is put into a developing solution to remove the photoresist in the source electrode and drain electrode regions, and is subjected to ultra-pure water rinsing and nitrogen blow-drying.
And removing the SiN medium layer in the first source electrode area and the first drain electrode area by using an ICP (inductively coupled plasma) etching process, and etching to the upper surface of the AlGaN barrier layer. The etching conditions are as follows: the reaction gas being CF4And O2The pressure of the reaction chamber is l0mTorr, and the radio frequency power of the upper electrode and the lower electrode is 20-50W and 5-l0W respectively.
S303, placing the sample with the etched source electrode groove and drain electrode groove areas into an electron beam evaporation table until the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 multiplied by 10-6After Torr, ohmic metal was evaporated on the sample surface. In this embodiment, the ohmic metal may be a metal stack structure composed of four layers of metals, i.e., Ti, Al, Ni, and Au, in sequence from bottom to top; and then, stripping the sample after the ohmic metal evaporation is finished, removing the ohmic metal, the photoresist and the stripping glue outside the first source electrode area and the first drain electrode area, flushing the sample with ultrapure water, and drying the sample with nitrogen.
And S304, as shown in FIG. 5, putting the sample subjected to ohmic metal evaporation and stripping into a rapid thermal annealing furnace for annealing treatment, so that the ohmic metal in the first source and drain electrode regions sinks to the GaN buffer layer, thereby forming ohmic contact between the ohmic metal and the heterojunction channel. Optionally, the annealing process conditions are as follows: annealing atmosphere is N2The annealing temperature was 830 ℃ and the annealing time was 30 s.
As shown in fig. 6, in the step S4, the second source electrode S2 and the second drain electrode D2 of the MOSFET device are formed on the surface of the second sub-portion a 2.
S401, firstly, photoetching second source and drain electrode areas on the surface of the side, away from the substrate, of the second sub-portion A2; specifically, after a sample is placed on a hot plate at 200 ℃ and baked for 5min, glue coating and spin coating of a stripping glue are carried out, the thickness of the spin coating is 0.35 mu m, and the sample is placed on the hot plate at 200 ℃ and baked for 5 min; then, gluing and spinning photoresist on the stripper, wherein the thickness of the spun photoresist is 0.77 mu m, and baking the sample on a hot plate at 90 ℃ for 1 min; putting the sample subjected to gluing and spinning into a photoetching machine, and exposing the photoresist in the second source electrode area and the second drain electrode area on the surface of the second sub-part A2; and putting the exposed sample into a developing solution to remove the photoresist and the stripping glue in the second source electrode area and the second drain electrode area on the surface of the second sub-part A2, and washing the sample with ultrapure water and drying the sample with nitrogen.
S402, further, the Au metal is evaporated on the photoresist of the second sub-portion a 2. Specifically, a sample is placed into a plasma degumming machine for basement membrane treatment, wherein the treatment time is 5 min; putting the sample into an electron beam evaporation table until the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 multiplied by 10-6After Torr, Au metal was evaporated on the sample surface; next, the sample after the metal evaporation is stripped to remove the metal, the photoresist and the stripping glue outside the second source and drain electrode regions on the surface of the second sub-portion a2, and the second source electrode S2 and the second drain electrode D2 of the MOSFET device are formed by washing with ultra-pure water and drying with nitrogen.
As shown in fig. 7, in the step S5, after the second source electrode S2 and the second drain electrode D2 are fabricated, an ALD (Atomic layer deposition) process is used to prepare Al in the active area of the MOSFET device2O3And forming a gate dielectric layer.
S501, growing Al on the surface of the side, far away from the substrate, of the p-type diamond layer by utilizing an Atomic Layer Deposition (ALD) process of a coating process2O3(ii) a In particular, Al is deposited2O3While using H2O is taken as an oxidant, trimethyl aluminum TMA is taken as an aluminum source, and H is alternately introduced in a pulse mode2O and TMAWherein TMA and H2The pulse time of O is 0.3s, the purging time of TMA is 5s, H2The purging time of O is 7s, and Al with the thickness of 5-20 nm is obtained by growth2O3。
S502, etching to remove Al outside the active region of the MOSFET2O3And forming a gate dielectric layer. Optionally, the area outside the MOSFET active area is first photo-etched: baking the epitaxial wafer on a hot plate at 200 deg.C for 5min, and placing on the dielectric layer Al2O3Coating photoresist and spin coating, and baking the sample on a hot plate at 90 ℃ for lmin; putting the sample subjected to gluing and whirl coating into a photoetching machine, and exposing the photoresist in the region outside the MOSFET active region; then, putting the sample into a developing solution to remove the photoresist in the area outside the MOSFET active area, and carrying out ultra-pure water washing and nitrogen blow-drying on the photoresist; finally, removing the dielectric layer Al outside the MOSFET active region by utilizing an ICP etching process2O3。
Referring to fig. 8, in step S6, a gate electrode of the HEMT device is formed on the exposed surface of the SiN dielectric layer away from the substrate.
S601, etching a gate groove area on the SiN dielectric layer. Specifically, after a sample is placed on a hot plate at 200 ℃ and baked for 5min, photoresist coating and spin coating are carried out, and the sample is placed on a hot plate at 90 ℃ and baked for lmin; then, putting the sample into a photoetching machine to expose the photoresist in the gate electrode area; and putting the exposed sample into a developing solution, removing the photoresist in the gate electrode area, and carrying out ultra-pure water washing and nitrogen blow-drying on the photoresist.
S602, removing the SiN medium layer in the gate groove area by utilizing an ICP (inductively coupled plasma) etching process, and etching to the upper surface of the AlGaN barrier layer, wherein the etching conditions are as follows: with CF4And O2As the reaction gas, the pressure of the reaction chamber is l0mTorr, and the RF power of the upper electrode and the lower electrode is 20-50W and 5-l0W, respectively.
And S603, evaporating the gate electrode in the gate groove area. Putting the sample into an electron beam evaporation table until the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 multiplied by 10-6After Torr, a gate metal, which may be evaporated on the sample surfaceThe metal stack structure is composed of two layers of Ni and Au from bottom to top in sequence; and stripping the sample after the gate metal evaporation is finished, removing the gate metal, the photoresist and the stripping glue outside the first gate electrode groove area, flushing the sample with ultrapure water and drying the sample with nitrogen.
In this embodiment, the p-type diamond layer remaining after etching includes two portions, i.e., the first sub-portion a1 and the second sub-portion a2, along a direction perpendicular to the plane of the substrate, an orthogonal projection of the first sub-portion a1 is located between an orthogonal projection of the first gate electrode and an orthogonal projection of the first drain electrode, orthogonal projections of the second source electrode and the second drain electrode are both located in an orthogonal projection of the second sub-portion a2, and the first sub-portion a1 is in contact with the first gate electrode; that is, the portion of the p-type diamond layer that is etched away refers to the p-type diamond layer located at the corresponding positions of the first source electrode S1, the first gate electrode G1, and the first drain electrode D1 of the HEMT device.
Referring to fig. 9, in step S7, the sample is first baked on a hot plate at 200 ℃ for 5min, then the gate dielectric layer is coated with a release glue and spun, the thickness of the spun glue is 0.35 μm, and the sample is baked on the hot plate at 200 ℃ for 5 min; then, gluing and spinning photoresist on the stripper with the thickness of 0.77 mu m, and placing the sample on a hot plate at 90 ℃ for baking lmin; then, putting the sample subjected to gluing and whirl coating into a photoetching machine to expose the photoresist in the second gate electrode area; and putting the exposed sample into a developing solution, removing the photoresist and the stripping glue in the second gate electrode region, washing the photoresist and the stripping glue with ultrapure water and drying the photoresist and the stripping glue with nitrogen, and photoetching on the gate dielectric layer to form a second gate electrode region.
Further, putting the samples with the photoetching patterns of the active electrode and the drain electrode into a plasma photoresist remover for carrying out basement membrane treatment, wherein the treatment time is 5 min; then, the sample is put into an electron beam evaporation table until the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 multiplied by 10-6Evaporating gate metal Al on the surface of the sample after Torr; stripping the sample subjected to gate metal evaporation, and removing metal Al, the photoresist and the stripping glue outside the second gate electrode area; finally, it is rinsed with ultrapure water and with nitrogenAnd (5) air drying.
As shown in fig. 9, an embodiment of the present invention provides a monolithic heterogeneous integrated structure of a top p-type diamond MOSFET and a GaN HEMT, which is manufactured by the above method for manufacturing the monolithic heterogeneous integrated structure of the top p-type diamond MOSFET and the GaN HEMT.
The beneficial effects of the invention are that:
1. according to the invention, after the p-type diamond layer is heteroepitaxially grown on the top of the epitaxial substrate, part of the p-type diamond layer is removed by graphical etching, and the GaN HEMT device based on the epitaxial substrate is manufactured, so that the junction temperature of the GaN HEMT device can be effectively reduced by utilizing the high thermal conductivity of the diamond material.
2. According to the invention, the p-type diamond layer is grown on the top heteroepitaxy, and the MOSFET device based on the p-type diamond is manufactured, so that the heterogeneous integration of the GaN electronic conducting device and the diamond hole conducting device is realized, the GaN electronic conducting device can be applied to a high-temperature logic circuit, and the problem that the logic circuit based on the Si device in the prior art can not be applied when the temperature is higher than 125 ℃ is solved.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
While the present application has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, numerous simple deductions or substitutions may be made without departing from the spirit of the invention, which shall be deemed to belong to the scope of the invention.
Claims (8)
1. A preparation method of a monolithic heterogeneous integrated structure of a top layer p-type diamond MOSFET and a GaN HEMT is characterized by comprising the following steps:
providing a substrate, and growing an epitaxial structure on the surface of the substrate, wherein the epitaxial structure comprises a GaN buffer layer and an AlGaN barrier layer which are grown on the surface of the substrate in sequence;
growing an SiN medium layer on the surface of the AlGaN barrier layer, which is far away from one side of the substrate, and growing a p-type diamond layer on the surface of the SiN medium layer, which is far away from one side of the substrate;
etching a source electrode groove and a drain electrode groove on the exposed SiN medium layer after etching and removing part of the p-type diamond layer, manufacturing a first source electrode of the HEMT device in the source electrode groove, and manufacturing a first drain electrode of the HEMT device in the drain electrode groove; wherein the etched p-type diamond layer includes a first sub-portion and a second sub-portion;
manufacturing a second source electrode and a second drain electrode of the MOSFET device on the surface of the p-type diamond layer on the side far away from the substrate;
depositing Al on the surface of the p-type diamond layer far away from the substrate side2O3Forming a gate dielectric layer;
manufacturing a first gate electrode of the HEMT device on the surface of one side of the exposed SiN dielectric layer, which is far away from the substrate; the first sub-part is contacted with the first gate electrode, and the orthographic projection of the first sub-part is positioned between the orthographic projection of the first gate electrode and the orthographic projection of the first drain electrode along the direction vertical to the plane of the substrate; the orthographic projections of the second source electrode and the second drain electrode are both located within the orthographic projection of the second sub-portion;
and manufacturing a second gate electrode on the surface of one side of the gate dielectric layer, which is far away from the substrate, so as to form the monolithic heterogeneous integrated structure of the top layer p-type diamond MOSFET and the GaN HEMT.
2. The method for preparing the monolithic heterogeneous integrated structure of the top layer p-type diamond MOSFET and the GaN HEMT according to claim 1, wherein the step of growing the SiN dielectric layer on the surface of the AlGaN barrier layer on the side away from the substrate comprises the following steps:
growing an SiN medium layer on the surface of the AlGaN barrier layer, which is far away from one side of the substrate, by utilizing an MOCVD (metal organic chemical vapor deposition) process; the thickness of the SiN medium layer is 5-20 nm in the direction perpendicular to the plane of the substrate.
3. The method for preparing the monolithic heterogeneous integrated structure of the top layer p-type diamond MOSFET and the GaN HEMT according to claim 2, wherein the step of growing the p-type diamond layer on the surface of the SiN dielectric layer on the side away from the substrate comprises the following steps:
by means of H2Diluted CH4Providing a source of C and passing H through the gas phase2Diluted B (CH)3)3And depositing a p-type diamond layer on the surface of the SiN dielectric layer far away from the substrate by using a Microwave Plasma Chemical Vapor Deposition (MPCVD) process under the conditions that the C is equal to 1000ppm, the air pressure is 25torr, the microwave power is 750W, the substrate temperature is 750-800 ℃, and the total gas flow is 400 sccm.
4. The method for preparing the monolithic heterogeneous integrated structure of the top layer p-type diamond MOSFET and the GaN HEMT according to claim 3, wherein the thickness of the p-type diamond layer is 500-1000 nm along the direction vertical to the plane of the substrate.
5. The method for preparing the monolithic heterogeneous integrated structure of the top layer p-type diamond MOSFET and the GaN HEMT according to claim 3, wherein the deposition rate of the p-type diamond layer is 0.13-0.2 μm/h.
6. The method for preparing the monolithic heterogeneous integrated structure of the top layer p-type diamond MOSFET and the GaN HEMT according to claim 1, wherein Al is deposited on the surface of the p-type diamond layer on the side far away from the substrate2O3And forming a gate dielectric layer, which comprises the following steps:
by using an Atomic Layer Deposition (ALD) process of a coating process, H is alternately introduced in a pulse mode at the temperature of 300 DEG C2O and TMA, Al is grown on the surface of the side of the p-type diamond layer far away from the substrate2O3；
Etching to remove Al outside the MOSFET active region2O3And forming a gate dielectric layer.
7. The method for preparing the monolithic heterogeneous integrated structure of the top layer p-type diamond MOSFET and the GaN HEMT according to claim 6, wherein Al is arranged along the direction vertical to the plane of the substrate2O3The thickness of (a) is 5to 20 nm.
8. A monolithic heterogeneous integrated structure of a top layer p-type diamond MOSFET and a GaN HEMT is characterized by being prepared by the preparation method of the monolithic heterogeneous integrated structure of the top layer p-type diamond MOSFET and the GaN HEMT according to any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210090222.1A CN114551358A (en) | 2022-01-25 | 2022-01-25 | Top layer p-type diamond MOSFET and GaN HEMT monolithic heterogeneous integrated structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210090222.1A CN114551358A (en) | 2022-01-25 | 2022-01-25 | Top layer p-type diamond MOSFET and GaN HEMT monolithic heterogeneous integrated structure and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114551358A true CN114551358A (en) | 2022-05-27 |
Family
ID=81673125
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210090222.1A Pending CN114551358A (en) | 2022-01-25 | 2022-01-25 | Top layer p-type diamond MOSFET and GaN HEMT monolithic heterogeneous integrated structure and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114551358A (en) |
-
2022
- 2022-01-25 CN CN202210090222.1A patent/CN114551358A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106847895B (en) | GaN base high electron mobility transistor and production method based on TiN/Cu/Ni gate electrode | |
| CN107170822B (en) | GaN-based groove insulated gate enhanced high electron mobility transistor based on negative capacitance medium | |
| CN113284948B (en) | GaN device and preparation method thereof | |
| JP2008306027A (en) | Manufacturing method of semiconductor device | |
| CN114497038B (en) | GaN HEMT device and p-type diamond MOSFET integrated device and manufacturing method thereof | |
| CN108847392B (en) | Buddha's warrior attendant ground mass gallium nitride device manufacturing method | |
| CN112466942B (en) | GaN HEMT with finger-inserting type diamond heat dissipation layer and preparation method thereof | |
| CN108922849A (en) | Semiconductor structure manufacturing method | |
| CN114496934B (en) | GaN HEMTs and top-layer hydrogen-terminated diamond MOSFETs integrated structure and preparation method thereof | |
| CN114551358A (en) | Top layer p-type diamond MOSFET and GaN HEMT monolithic heterogeneous integrated structure and preparation method thereof | |
| CN115274851A (en) | Enhanced radio frequency device based on P-GaN cap layer and Fin structure and preparation method thereof | |
| CN108417630B (en) | HEMT device and preparation method thereof | |
| CN109904227B (en) | Diamond-based field effect transistor with low-work-function conductive grid and preparation method thereof | |
| CN114551445A (en) | Diamond substrate GaN HEMT and hydrogen terminal MOSFET integrated structure and preparation method thereof | |
| CN113809154A (en) | Nitride potential barrier stress modulation device and preparation method thereof | |
| WO2019153431A1 (en) | Preparation method for hot electron transistor in high frequency gallium nitride/graphene heterojunction | |
| CN113571416B (en) | Diamond-based gallium nitride transistor with high electron mobility and preparation method thereof | |
| CN116190230A (en) | Polycrystalline diamond film and GaN HEMT integrated preparation method based on cyclic etching technology | |
| CN111446289B (en) | Gallium nitride device structure based on graphene covering layer and preparation method thereof | |
| CN110752162B (en) | Pre-distortion integrated circuit based on X-band gallium nitride and manufacturing method | |
| CN112466944B (en) | GaN HEMT based on inserted-finger-shaped p-type doped diamond and preparation method | |
| TWI751687B (en) | Semiconductor structures having reduced thermally induced bow | |
| CN106711210A (en) | Dielectric auxiliary support nanometer gate device and manufacture method thereof | |
| CN118116804A (en) | Gallium nitride device based on polarization regulation and control mesa isolation structure and manufacturing method | |
| CN115312390A (en) | Low-gate leakage GaN Fin-HEMT device using strong polarization barrier material and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |