CN114551341A - Metal interconnection layer for 3D memory and manufacturing method thereof - Google Patents

Abstract

The invention discloses a metal interconnection layer for a 3D memory and a manufacturing method thereof, wherein the 3D memory comprises a substrate, and the manufacturing method comprises the following steps: forming a plurality of metal connecting wires which are arranged at intervals on the substrate, and forming a first channel between the adjacent metal connecting wires; depositing a first dielectric layer to form an incompletely closed air gap in the first channel; adopting plasma bombardment to make the contour of the air gap move downwards; and depositing a second dielectric layer to form a closed air gap in the first channel, forming an air gap which is not completely closed after the first dielectric layer is preliminarily deposited, cutting an opening of the air gap through plasma bombardment, moving the upper end of the air gap profile downwards, and depositing the second dielectric layer again to close the air gap, so that the aim of reducing the air gap is fulfilled, the problem of collapse above the air gap in the subsequent process due to overhigh position of the air gap is effectively avoided, and the yield and the reliability of products are improved under the condition of reducing RC delay.

Description

Metal interconnection layer for 3D memory and manufacturing method thereof

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to a metal interconnection layer for a 3D memory and a manufacturing method thereof.

Background

The increase in memory density of memory devices is closely related to the progress of semiconductor manufacturing processes. As the feature size (CD) of a semiconductor manufacturing process becomes smaller, the memory density of the memory device becomes higher. In order to further increase the memory density, a memory device of a three-dimensional structure (i.e., a 3D memory device) has been developed. The 3D memory device includes a plurality of memory cells stacked in a vertical direction, can increase integration in multiples on a unit area of a wafer, and can reduce cost.

Existing 3D memory devices are mainly used as non-volatile flash memories. Two major non-volatile flash memory technologies employ NAND and NOR architectures, respectively. The read speed is slightly slower in the NAND memory device compared to the NOR memory device, but the write speed is fast, the erase operation is simple, and a smaller memory cell can be realized, thereby achieving higher memory density. Therefore, the 3D memory device adopting the NAND structure is widely used.

As the feature size of semiconductor devices is smaller and smaller, the density of devices and metal lines is increased sharply, and the parasitic capacitance between adjacent metal lines is also larger and larger, so that the RC delay phenomenon is more and more obvious. The RC delay phenomenon not only increases power consumption, but also adversely affects the operation speed of the semiconductor device, and even affects the reliability of the semiconductor device in a severe case. In the prior art, an air gap (air gap) is formed between adjacent metal lines, so that the parasitic capacitance between the adjacent metal lines is reduced, and the RC delay phenomenon is reduced or avoided. However, as the feature size of semiconductor devices becomes smaller, the air gap becomes susceptible to collapse failure due to size issues, and parasitic capacitance between adjacent metal lines cannot be reduced.

Accordingly, an improved metal interconnection layer for a 3D memory and a method for fabricating the same are desired to solve the above problems, thereby improving the yield and reliability of a semiconductor device.

Disclosure of Invention

In view of the foregoing problems, an object of the present invention is to provide a metal interconnection layer for a 3D memory and a method for manufacturing the same, which can increase the distance between the upper end of an air gap and the upper surface of a metal connection, avoid the problem of air gap collapse in the subsequent process due to an excessively high position of the air gap, and improve the yield and reliability of the product.

According to an aspect of the present invention, there is provided a method of fabricating a metal interconnect layer for a 3D memory, the 3D memory including a substrate, the method comprising: forming a plurality of metal connecting wires which are arranged at intervals on the substrate, and forming a first channel between the adjacent metal connecting wires; depositing a first dielectric layer to form an incompletely closed air gap in the first channel; adopting plasma bombardment to make the profile of the air gap move downwards; and depositing a second dielectric layer to form a closed air gap in the first channel.

Optionally, the moving the profile of the air gap downward using plasma bombardment comprises: and cutting the opening of the incompletely closed air gap by adopting plasma bombardment so as to enable the upper end of the air gap profile to move downwards.

Optionally, after the step of depositing the second dielectric layer, the method further includes: and flattening the second dielectric layer by adopting chemical mechanical polishing.

Optionally, the forming a plurality of metal wires arranged at intervals on the substrate includes: forming a sacrificial layer on the substrate; forming a mask on the sacrificial layer and patterning the mask; etching the sacrificial layer according to the patterned mask until the substrate is exposed so as to form a second channel; depositing a metal layer until the second channel is filled; planarizing the metal layer until the upper surface of the sacrificial layer is exposed; and removing the sacrificial layer to form a plurality of metal connecting wires arranged at intervals and the first channel.

Optionally, the forming a mask on the sacrificial layer and patterning the mask includes: forming a photoresist layer on the sacrificial layer; and patterning the photoresist layer.

Optionally, the depositing the first dielectric layer and the depositing the second dielectric layer include: and depositing the first dielectric layer and the second dielectric layer by adopting a plasma gas chemical vapor deposition method.

Optionally, the first dielectric layer and the second dielectric layer are made of the same low dielectric constant material.

According to another aspect of the present invention, there is provided a metal interconnection layer of a 3D memory, the 3D memory including a substrate, the metal interconnection layer including: a plurality of metal connecting wires arranged on the substrate at intervals; a third dielectric layer covering the plurality of metal connecting lines, wherein the dielectric layer is partially filled in the space between the adjacent metal connecting lines, so that air gaps are included in the space; wherein the upper end of the air gap profile is lower than the upper surface of the metal connecting line.

Optionally, the base includes a substrate and a stacked structure on the substrate, where the stacked structure includes conductive layers and interlayer dielectric layers stacked alternately, and a conductive channel pillar penetrating through the stacked structure; wherein the metal line is electrically connected to the conductive channel pillar.

The manufacturing method of the metal interconnection layer for the 3D memory adopts the manufacturing methods of deposition, bombardment and deposition; after the first dielectric layer is preliminarily deposited, an air gap which is not completely closed is formed, the upper end of the air gap profile is moved downwards by cutting an opening of the air gap through plasma bombardment, and the second dielectric layer is deposited again to close the air gap, so that the purpose of reducing the air gap is achieved.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1a and 1b show a circuit diagram and a structural schematic diagram, respectively, of a memory cell string of a 3D memory device.

FIG. 2a shows a perspective view of a 3D memory device;

FIG. 2b shows a cross-sectional view in the direction A-A of the 3D memory device of FIG. 2 a;

FIG. 3 illustrates a cross-sectional view of a prior art metal interconnect layer;

FIG. 4 shows a flow chart of a method of fabricating a metal interconnect layer of an embodiment of the present invention;

FIGS. 5 a-5 g are cross-sectional views of various stages of a method for fabricating a metal interconnect layer in accordance with an embodiment of the present invention;

fig. 6a and 6b show electron micrographs of a metal interconnect layer of the prior art and the present invention, respectively.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In the various figures, the same elements or modules are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.

It should be understood that in the following description, "circuitry" may comprise singly or in combination hardware circuitry, programmable circuitry, state machine circuitry, and/or elements capable of storing instructions executed by programmable circuitry. When an element or circuit is referred to as being "connected to" another element or circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that the two be absent intermediate elements.

Also, certain terms are used throughout the description and claims to refer to particular components. As one of ordinary skill in the art will appreciate, manufacturers may refer to a component by different names. This patent specification and claims do not intend to distinguish between components that differ in name but not function.

In the present application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a memory device, including all layers or regions that have been formed. In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

Moreover, it is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.

Fig. 1a and 1b show a circuit diagram and a structural schematic diagram, respectively, of a memory cell string of a 3D memory device. The case where the memory cell string includes 4 memory cells is shown in this embodiment. It is to be understood that the present invention is not limited thereto, and the number of memory cells in the memory cell string may be any number, for example, 32 or 64.

As shown in fig. 1a, a first terminal of the memory cell string 100 is connected to a bit line BL, and a second terminal is connected to a source line SL. The memory cell string 100 includes a plurality of transistors connected in series between a first terminal and a second terminal, including: a first select transistor Q1, memory transistors M1-M4, and a second select transistor Q2. The gate of the first selection transistor Q1 is connected to a first selection line SSL, and the gate of the second selection transistor Q2 is connected to a second selection line GSL. The gates of the memory transistors M1 to M4 are connected to respective ones of the word lines WL1 to WL4, respectively.

As shown in FIG. 1b, the first select transistor Q1 and the second select transistor Q2 of the memory cell string 100 include gate conductors 109b and 109c, respectively, and the memory transistors M1-M4 include gate conductor 109a, respectively. The gate conductors 109a, 109b, and 109c are in accordance with the stacking order of the transistors in the memory cell string 100, and adjacent gate conductors are separated from each other by an interlayer insulating layer, thereby forming a gate stack structure. Further, the memory cell string 100 includes a channel pillar 110. The channel pillar 110 is adjacent to or through the gate stack structure. In the middle portion of the channel pillar 110, a tunneling dielectric layer 112, a charge storage layer 113, and a blocking dielectric layer 114 are interposed between the gate conductor 109a and the channel layer 111, thereby forming memory transistors M1 through M4. At both ends of the channel pillar 110, a blocking dielectric layer 114 is sandwiched between the gate conductors 109b and 109c and the channel layer 111, thereby forming a first selection transistor Q1 and a second selection transistor Q2.

In this embodiment, the channel layer 111 is composed of, for example, doped polysilicon, the tunneling dielectric layer 112 and the blocking dielectric layer 114 are respectively composed of an oxide such as silicon oxide, the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals such as silicon nitride and silicon oxynitride containing particles of a metal or a semiconductor, and the gate conductors 109a, 109b, and 109c are composed of a metal such as tungsten. The channel layer 111 serves to provide channel regions of the selection transistor and the memory transistor, and the doping type of the channel layer 111 is the same as the type of the selection transistor and the memory transistor. For example, for N-type select and memory transistors, the channel layer 111 may be N-type doped polysilicon.

In this embodiment, the core of channel pillar 110 is channel layer 111, and tunnel dielectric layer 112, charge storage layer 113, and blocking dielectric layer 114 form a stacked structure around the core sidewall. In an alternative embodiment, the core of channel pillar 110 is an additional insulating layer, and channel layer 111, tunnel dielectric layer 112, charge storage layer 113, and blocking dielectric layer 114 form a stacked structure surrounding the core.

In this embodiment, the first and second selection transistors Q1 and Q2, the memory transistors M1 to M4 use the common channel layer 111 and the blocking dielectric layer 114. In the channel pillar 110, the channel layer 111 provides source-drain regions and a channel layer of a plurality of transistors. In an alternative embodiment, the semiconductor layer and the blocking dielectric layer of the first and second selection transistors Q1 and Q2 and the semiconductor layer and the blocking dielectric layer of the memory transistors M1 to M4 may be formed separately in steps independent of each other. In the channel pillar 110, the semiconductor layers of the first and second select transistors Q1 and Q2 and the semiconductor layers of the memory transistors M1 to M4 are electrically connected to each other.

In a write operation, the memory cell string 100 writes data to a selected one of the memory transistors M1 through M4 using FN tunneling efficiency. Taking the memory transistor M2 as an example, while the Source Line SL is grounded, the second control Gate select Line (Gate Selective Line) GSL is biased to about zero volts, so that the select transistor Q2 corresponding to the second control Gate select Line GSL is turned off, and the first Source Selective Line (Source Selective Line) SSL is biased to the high voltage VDD, so that the select transistor Q1 corresponding to the first select Line SSL is turned on. Further, BIT line BIT2 is grounded, word line WL2 is biased at the programming voltage VPG, e.g., about 20V, and the remaining word lines are biased at the low voltage VPS 1. Since only the word line voltage of the selected memory transistor M2 is higher than the tunneling voltage, electrons in the channel region of the memory transistor M2 reach the charge storage layer 113 through the tunneling dielectric layer 112, thereby converting data into charges stored in the charge storage layer 113 of the memory transistor M2.

In a read operation, the memory cell string 100 determines the amount of charge in the charge storage layer from the on-state of a selected one of the memory transistors M1 through M4, thereby obtaining data indicative of the amount of charge. Taking the memory transistor M2 as an example, word line WL2 is biased at the read voltage VRD, and the remaining word lines are biased at the high voltage VPS 2. The on state of the memory transistor M2 is related to its threshold voltage, i.e., the amount of charge in the charge storage layer, so that a data value can be determined according to the on state of the memory transistor M2. The memory transistors M1, M3, and M4 are always in a conductive state, and therefore, the conductive state of the memory cell string 100 depends on the conductive state of the memory transistor M2. The control circuit judges the conductive state of the memory transistor M2 based on the electric signals detected on the bit line BL and the source line SL, thereby obtaining the data stored in the memory transistor M2.

Fig. 2a shows a perspective view of a 3D memory device. For clarity, the various insulating layers in the 3D memory device are not shown in fig. 2 a.

The 3D memory device 200 shown in this embodiment includes 4 x 4 for a total of 16 memory cell strings 100, each memory cell string 100 including 4 memory cells, thereby forming a memory array of 4 x 4 for a total of 64 memory cells. It is understood that the present invention is not limited thereto and the 3D memory device may include any number of memory cell strings, for example, 1024, and the number of memory cells in each memory cell string may be any number, for example, 32 or 64.

In the 3D memory device 200, the memory cell strings respectively include the respective channel pillars 110, and the common gate conductors 121, 122, and 123. The gate conductors 121, 122, and 123 correspond to a stacking order of transistors in the memory cell string 100, and adjacent gate conductors are spaced apart from each other by an interlayer insulating layer, thereby forming a gate stack structure 120. The interlayer insulating layer is not shown in the figure.

The internal structure of the channel pillar 110 is shown in fig. 1b and will not be described in detail. The channel pillars 110 penetrate through the gate stack structure 120 and are arranged in an array, and a plurality of channel pillars 110 in a same column have first ends commonly connected to a same bit line (i.e., one of the bit lines BL1 to BL 4), second ends commonly connected to the substrate 101, and second ends forming a common source connection through the substrate 100.

The gate conductor 122 of the first selection transistor Q1 is divided into different gate lines by a gate line slit (gate line slit) 102. The gate lines of the channel pillars 110 in the same row are commonly connected to the same string selection line (i.e., one of the string selection lines SSL1 through SSL 4).

The gate conductors 121 of memory transistors M1 and M4 are each connected to a corresponding word line. If the gate conductors 121 of the memory transistors M1 and M4 are divided into different gate lines by the gate line slit 161, the gate lines of the same level reach the interconnect layer 132 via respective conductive paths 131 to be interconnected with each other, and then are connected to the same word line (i.e., one of the word lines WL1 to WL 4) via the conductive path 133.

The gate conductors of the second select transistors Q2 are connected in one piece. If the gate conductor 123 of the second selection transistor Q2 is divided into different gate lines by the gate line slit 161, the gate lines reach the interconnection layer 132 via respective conductive paths 131 to be interconnected with each other, and then are connected to the same ground selection line GSL via the conductive path 133.

Further, referring to fig. 2b, fig. 2b shows a cross-sectional view in the direction a-a of the 3D memory device in fig. 2 a. The 3D memory device 200 includes a substrate 210 and a metal interconnection layer 220 located over the substrate 210. The base 210 includes a substrate 201 and a stacked structure on the substrate 201, the stacked structure including a plurality of interlayer insulating layers 202 and metal layers 203 stacked alternately; and a conductive channel pillar 204 extending through the stacked structure. The material from which substrate 201 is fabricated may be selected from any suitable semiconductor material, for example, a group III-V compound selected from single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOD), or gallium arsenide.

The metal interconnection layer 220 is disposed on the substrate 210 and includes a metal line 206 electrically connected to the conductive trench pillar 204, a dielectric layer 207 covering the metal line 206, and an air gap 2081 between two adjacent metal lines 206. The metal line 206 is preferably copper or copper alloy, but may be other conductive materials such as silver, gold, tungsten, aluminum, or the like.

As the feature size of the semiconductor device decreases, the distance between the metal lines 206 decreases, which results in an increased parasitic capacitance between adjacent metal lines 206, thereby generating an RC delay phenomenon, and in order to reduce the parasitic capacitance, a material with a low node constant is mostly used to fill between the metal lines 206, so that air with a dielectric constant equal to about 1 is one of the ideal filling materials. However, in the prior art, the dielectric layer 207 is deposited by a PECVD (Plasma Enhanced Chemical Vapor Deposition) process, so that an air gap 2081 is formed between adjacent metal lines 206, as shown in fig. 3, the position of the air gap 2081 is shifted upward, the thickness of the dielectric layer above the air gap 2081 is smaller, which is close to the upper surface of the metal line 206, and thus the subsequent process window (process window) is smaller.

In view of the above, the present invention provides an improved method for manufacturing a metal interconnection layer, as shown in fig. 4. The flowchart of the method for manufacturing a metal interconnect layer according to the embodiment of the present invention shown in fig. 4 will be further described with reference to the cross-sectional views of the various stages of the method for manufacturing a metal interconnect layer according to the embodiment of the present invention shown in fig. 5a to 5 g. The manufacturing method of the metal interconnection layer comprises the following steps:

step S10: a plurality of metal connecting wires which are arranged at intervals are formed on the substrate, and a first channel is formed between every two adjacent metal connecting wires. Wherein, the step S10 includes steps S11 to S16.

In step S11, a sacrificial layer 230 is formed on the substrate 210, for example, by depositing the sacrificial layer 230 on the substrate 210 by PECVD.

In step S12, a mask 240 is formed on the sacrificial layer 230 and the mask 240 is patterned. For example, a photoresist layer 240 is formed on the sacrificial layer 230, and the photoresist layer 240 is patterned, resulting in the semiconductor structure shown in fig. 5 a.

In step S13, the sacrificial layer 230 is etched according to the patterned mask 240 until the substrate 210 is exposed to form a second trench 250, resulting in the semiconductor structure shown in fig. 5 b.

In step S14, the metal layer 240 is deposited until the metal layer 240 fills the second trench 250, resulting in the semiconductor structure shown in fig. 5 c. The metal layer 240 is selected from copper, copper alloy, silver, and the like, for example, and is suitable for use as a metal conductor of a metal wiring.

Illustratively, a thin metallic copper seed layer (not shown) is first deposited, preferably using a Physical Vapor Deposition (PVD) process; then, an Electrochemical Plating (ECP) process is used to deposit copper on the surface of the copper seed layer to fill the second trench 250.

In step S15, the metal layer 240 is planarized until the upper surface of the sacrificial layer 230 is exposed, for example, by using a chemical mechanical polishing to planarize the metal layer 240.

In step S16, the sacrificial layer 230 is removed to form a first trench 260, resulting in the semiconductor structure shown in fig. 5 d. The semiconductor structure shown in fig. 5d comprises a substrate 210, a plurality of metal lines 206 spaced apart on the substrate 210, and a first trench 260 between adjacent metal lines 206.

In order to more intuitively explain and explain a related method of forming an air gap in the metal interconnection layer manufacturing method according to an embodiment of the present invention, the substrate 210 is omitted in fig. 5e to 5 g.

Step S20: a first dielectric layer is deposited to form an incompletely closed air gap within the first trench. A first deposition is performed by PECVD to form an incompletely closed air gap 208 in the first trench, resulting in the semiconductor structure shown in fig. 5 e.

Step S30: the profile of the air gap (profile) is moved down using Plasma Bombardment (Plasma Bombardment). The plasma bombardment is used to cut the opening of the air gap 208, moving the upper end of its profile downward, as shown in FIG. 5 f.

Step S40: and depositing a second dielectric layer to form a closed air gap in the first channel. A second deposition is performed by PECVD to close the openings of the air gaps 208 and planarize the upper surface of the second dielectric layer, resulting in the metal interconnect layer shown in fig. 5 g.

Step S50: the second dielectric layer is planarized, for example, by using a chemical mechanical polishing process, and in this process, in order to meet the process requirements, the first dielectric layer may be planarized when the first dielectric layer is partially exposed.

The first dielectric layer and the second dielectric layer are made of the same low dielectric constant material, and the first dielectric layer and the second dielectric layer form a third dielectric layer.

The manufacturing method of the metal interconnection layer provided by the invention adopts a deposition-bombardment-deposition method to move the upper end of the air gap 208 profile downwards, thereby achieving the purpose of depressing the air gap 208. Referring to fig. 6a and 6b, fig. 6a shows an electron microscope image of a metal interconnection layer in the prior art, and it can be seen that the air gap 2081 is located close to the upper end of the metal connection line 206, so that the subsequent process window is small. Fig. 6b shows an electron microscope image of the metal interconnection layer according to the embodiment of the invention, which shows that the upper end of the air gap 208 is pressed down and away from the upper end of the metal connection line 206, so as to increase the process window and effectively improve the yield and reliability of the device.

In summary, the manufacturing method of the metal interconnection layer for the 3D memory provided by the invention adopts a manufacturing method of deposition, bombardment and deposition; after the first dielectric layer is preliminarily deposited, an air gap which is not completely closed is formed, the upper end of the air gap profile is moved downwards by cutting an opening of the air gap through plasma bombardment, and the second dielectric layer is deposited again to close the air gap, so that the purpose of reducing the air gap is achieved.

It should be noted that as used herein, the words "during", "when" and "when … …" in relation to the operation of a circuit are not strict terms indicating an action that occurs immediately upon the start of a startup action, but rather there may be some small but reasonable delay or delays, such as various transmission delays, between it and the reaction action (action) initiated by the startup action. The words "about" or "substantially" are used herein to mean that the value of an element (element) has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there is always a slight deviation that makes it difficult for the value or position to be exactly the stated value. It has been well established in the art that a deviation of at least ten percent (10%) for a semiconductor doping concentration of at least twenty percent (20%) is a reasonable deviation from the exact ideal target described. When used in conjunction with a signal state, the actual voltage value or logic state (e.g., "1" or "0") of the signal depends on whether positive or negative logic is used.

In accordance with the present invention, as set forth above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The scope of the invention should be determined with reference to the appended claims and their equivalents.

Claims (9)

1. A method of fabricating a metal interconnect layer for a 3D memory, the 3D memory including a substrate, the method comprising:

forming a plurality of metal connecting wires which are arranged at intervals on the substrate, and forming a first channel between the adjacent metal connecting wires;

depositing a first dielectric layer to form an incompletely closed air gap in the first channel;

adopting plasma bombardment to make the contour of the air gap move downwards;

and depositing a second dielectric layer to form a closed air gap in the first channel.

2. The method of manufacturing of claim 1, wherein the using plasma bombardment to downscale the profile of the air gap comprises:

and cutting the opening of the incompletely closed air gap by adopting plasma bombardment so as to enable the upper end of the air gap profile to move downwards.

3. The method of manufacturing of claim 1, wherein after the step of depositing a second dielectric layer, further comprising:

and flattening the second dielectric layer by adopting chemical mechanical polishing.

4. The method of claim 1, wherein the forming a plurality of metal lines on the substrate at intervals comprises:

forming a sacrificial layer on the substrate;

forming a mask on the sacrificial layer and patterning the mask;

etching the sacrificial layer according to the patterned mask until the substrate is exposed so as to form a second channel;

depositing a metal layer until the second channel is filled;

planarizing the metal layer until the upper surface of the sacrificial layer is exposed;

and removing the sacrificial layer to form a plurality of metal connecting wires arranged at intervals and the first channel.

5. The manufacturing method according to claim 4, the forming a mask on the sacrifice layer and patterning the mask comprising:

forming a photoresist layer on the sacrificial layer;

and patterning the photoresist layer.

6. The method of manufacturing of claim 1, the depositing a first dielectric layer and the depositing a second dielectric layer comprising:

and depositing the first dielectric layer and the second dielectric layer by adopting a plasma gas chemical vapor deposition method.

7. The method of claim 1, wherein the first dielectric layer and the second dielectric layer are made of the same low-k material.

8. A metal interconnect layer of a 3D memory, the 3D memory comprising a substrate, the metal interconnect layer comprising:

a plurality of metal connecting wires arranged on the substrate at intervals;

a third dielectric layer covering the plurality of metal connecting lines, wherein the dielectric layer is partially filled in the space between the adjacent metal connecting lines, so that air gaps are included in the space; wherein,

the upper end of the air gap profile is lower than the upper surface of the metal connecting line.

9. The metal interconnect layer of claim 8, the base comprising a substrate and a stacked structure on the substrate,

the stacked structure comprises conductive layers and interlayer dielectric layers which are alternately stacked, and a conductive channel column which penetrates through the stacked structure; wherein,

the metal line is electrically connected to the conductive channel pillar.

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