CN114550434A - Alarm circuit, medical equipment and alarm method - Google Patents
Alarm circuit, medical equipment and alarm method Download PDFInfo
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- CN114550434A CN114550434A CN202011346335.0A CN202011346335A CN114550434A CN 114550434 A CN114550434 A CN 114550434A CN 202011346335 A CN202011346335 A CN 202011346335A CN 114550434 A CN114550434 A CN 114550434A
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- G—PHYSICS
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- G08B—SIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
- G08B29/00—Checking or monitoring of signalling or alarm systems; Prevention or correction of operating errors, e.g. preventing unauthorised operation
- G08B29/18—Prevention or correction of operating errors
- G08B29/181—Prevention or correction of operating errors due to failing power supply
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- G—PHYSICS
- G08—SIGNALLING
- G08B—SIGNALLING OR CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
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Abstract
The invention relates to the technical field of electronic circuits, in particular to an alarm circuit, medical equipment and an alarm method, wherein the alarm circuit comprises a power failure detection unit for detecting whether target equipment has power failure; the second processing unit is provided with an alarm module; the first processing unit is connected with the power failure detection unit and the second processing unit; the first processing unit is used for receiving the detection signal of the power failure detection unit and the heartbeat signal of the second processing unit so as to trigger the second processing unit to send an alarm when the second processing unit works normally and the target device is powered off. When the second processing unit works normally and the power failure detection unit detects that the target equipment has power failure, the first processing unit triggers the second processing unit to send out an alarm, and the detection of the power failure and the alarm triggering are split into the two processing units to be processed, so that the problem that alarm information is difficult to send due to the abnormity of the second processing unit can be avoided, and the safety of the target equipment using the alarm circuit is improved.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to an alarm circuit, medical equipment and an alarm method.
Background
The general requirement of medical equipment complete machine design is that it can last stable operation for a long time, if the complete machine appears not to insert the battery, and the disconnection alternating current power supply under the circumstances of abnormal shutdown, for guaranteeing patient's life safety, medical equipment should send the warning to inform medical personnel this medical equipment accident to fall the power. Therefore, in the design of medical equipment, it is generally necessary to provide an alarm circuit.
Currently, the design of the alarm circuit usually includes a power failure detection circuit, which triggers an alarm when an unexpected power failure of the medical device is detected. However, in the technical solution, if the alarm circuit itself is abnormal, which results in that the alarm circuit cannot work normally, when the medical equipment is powered off unexpectedly, the alarm circuit is difficult to send out alarm information, which results in that the safety of the medical equipment is low.
Disclosure of Invention
In view of this, embodiments of the present invention provide an alarm circuit, a medical device, and an alarm method, so as to solve the problem of low safety of the medical device due to an abnormal alarm circuit.
According to a first aspect, an embodiment of the present invention provides an alarm circuit, including:
the power failure detection unit is used for detecting whether the target equipment has power failure;
the second processing unit is provided with an alarm module;
the first processing unit is connected with the power failure detection unit and the second processing unit; the first processing unit is used for receiving the detection signal of the power failure detection unit and the heartbeat signal of the second processing unit so as to trigger the second processing unit to send out an alarm when the second processing unit works normally and the target device is powered off.
According to the alarm circuit provided by the embodiment of the invention, the second processing unit is provided with the alarm module, the first processing unit triggers the second processing unit to send out an alarm when the second processing unit works normally and the power failure detection unit detects the power failure of the target equipment, and the detection of the power failure and the alarm triggering are divided into two processing units for processing, so that the problem that alarm information is difficult to send out due to the abnormality of the second processing unit can be avoided, and the safety of the target equipment applying the alarm circuit is improved.
With reference to the first aspect, in a first implementation manner of the first aspect, the alarm circuit further includes:
the first power supply unit is connected with the first processing unit and the second power supply unit;
the second power supply unit is connected with the second processing unit.
The alarm circuit provided by the embodiment of the invention is provided with the first power supply unit and the second power supply unit, wherein the first power supply unit is a main power supply, the second power supply unit is an auxiliary power supply, and the alarm circuit is powered by the two power supplies so as to ensure that the alarm module can normally work when target equipment is powered off.
With reference to the first embodiment of the first aspect, in a second embodiment of the first aspect, the second power supply unit includes:
the input end of the charging and discharging circuit is connected with the output end of the first power supply unit, and the control end of the charging and discharging circuit is connected with the charging and discharging control end of the second processing unit;
the energy storage module is connected with the output end of the charge and discharge circuit;
and the input end of the voltage reduction circuit is connected with the output end of the first power supply unit and the output end of the energy storage module respectively, and the output end of the voltage reduction circuit is connected with the second processing unit.
According to the alarm circuit provided by the embodiment of the invention, the first power supply unit charges the energy storage module through the charging and discharging circuit, and when the target equipment is powered off, the electric energy stored by the energy storage module supplies power to the second processing unit, so that the normal work of the alarm circuit is ensured, and the reliability of the alarm circuit is improved.
With reference to the second embodiment of the first aspect, in a third embodiment of the first aspect, the charge and discharge circuit includes:
the anode of the first diode is connected with the output end of the first power supply unit, and the cathode of the first diode is connected with the second end of the first controllable switch;
and a first end of the first controllable switch is connected with the charge-discharge control end of the second processing unit, and a third end of the first controllable switch is connected with the energy storage module.
The alarm circuit provided by the embodiment of the invention has the function of preventing reverse through the arrangement of the first diode, firstly, voltage drop is generated, so that the charging voltage of the energy storage module is reduced to be below the rated voltage, and secondly, the reverse charging of a voltage reduction chip in the voltage reduction circuit is prevented when the energy storage module is discharged.
With reference to the second implementation manner of the first aspect, in a third implementation manner of the first aspect, the voltage reduction circuit includes:
a second diode having an anode connected to an output terminal of the first power supply unit;
the anode of the third diode is connected with the output end of the energy storage module, and the cathode of the third diode and the cathode of the second diode are simultaneously connected to the buck chip;
and the output end of the voltage reduction chip is connected with the second processing unit.
In the alarm circuit provided by the embodiment of the invention, the second diode and the third diode are selective diodes, and when the first power supply unit supplies power, the output of the voltage reduction chip is obtained by converting the output of the first power supply unit; when power failure occurs, the output of the voltage reduction chip is obtained by converting the output of the energy storage module.
With reference to the first embodiment of the first aspect, in a fifth embodiment of the first aspect, the alarm module includes:
a first end of the second controllable switch is connected with the alarm signal output end of the second processing unit, and a third end of the second controllable switch is connected with the sound production component;
and the sound production component is connected with the output end of the second power supply unit.
According to the alarm circuit provided by the embodiment of the invention, the second controllable switch and the output end of the second power supply unit are utilized to control the sounding component to give an alarm, so that the misoperation of the sounding component under the condition of voltage fluctuation can be avoided, and the reliability of the alarm is improved.
With reference to any one of the first to fifth embodiments of the first aspect, in a sixth embodiment of the first aspect, the alarm circuit further includes a power on/off multiplexing unit; wherein, the on-off multiplexing unit comprises:
a switch module;
a cathode of the third diode is connected with the switch module, and an anode of the third diode is respectively connected with an output end of the second power supply unit and a reset detection end of the second processing unit;
and the cathode of the fourth diode is connected with the switch module, and the anode of the fourth diode is respectively connected with the output end of the first power supply unit and the on-off detection end of the first processing unit.
According to the alarm circuit provided by the embodiment of the invention, because the anodes of the third diode and the fourth diode are connected with different signals, and the cathodes of the third diode and the fourth diode are connected with the switch modules, the mutual influence of the two branches can be avoided by utilizing the unidirectional conduction characteristic of the diodes, namely, the influence of the anode signals of the two diodes on each other is prevented, and the reliability of the alarm circuit is improved.
With reference to the sixth implementation manner of the first aspect, in a seventh implementation manner of the first aspect, the switching and powering multiplexing unit further includes:
and a second end of the third controllable switch is connected with the output end of the first power supply unit, a first end of the third controllable switch is connected with the anode of the fourth diode, and a third end of the third controllable switch is connected with the startup and shutdown detection end.
According to the alarm circuit provided by the embodiment of the invention, the anode voltage of the fourth diode is reduced through the signal output of the third end of the third controllable switch, so that the anode output signal of the fourth diode can be normally received by the first processing unit, and the current on-off state of the target device can be accurately determined.
According to a second aspect, embodiments of the present invention provide a medical apparatus comprising:
an apparatus body;
in the first aspect of the present invention, or the alarm circuit in any implementation manner of the first aspect, the alarm circuit is connected to a power input end of the device body, and the alarm circuit is configured to detect whether the device body is powered down to trigger an alarm.
According to the medical equipment provided by the embodiment of the invention, the second processing unit is provided with the alarm module, the first processing unit triggers the second processing unit to send out an alarm when the second processing unit works normally and the power failure detection unit detects the power failure of the medical equipment, and the detection of the power failure and the alarm triggering are divided into two processing units for processing, so that the problem that alarm information is difficult to send out due to the abnormality of the second processing unit can be avoided, and the safety of the medical equipment is improved.
According to a third aspect, an embodiment of the present invention further provides an alarm method, including:
receiving a detection signal of a power failure detection unit, wherein the power failure detection unit is used for detecting whether target equipment has power failure;
judging whether a heartbeat signal of the second processing unit is received or not;
and when a heartbeat signal of the second processing unit is received, triggering the action of the second processing unit based on the detection signal so as to trigger the second processing unit to send out an alarm when the target equipment is powered down.
According to the alarm method provided by the embodiment of the invention, the detection of power failure and the alarm triggering are separated into two processing units for processing, so that the problem that alarm information is difficult to send due to the abnormality of the second processing unit can be avoided, and the safety of medical equipment is improved.
With reference to the third aspect, in a first implementation manner of the third aspect, the triggering, based on the detection signal, an action of the second processing unit includes:
when the target equipment is normally powered on, sending a first identifier to the second processing unit so that the second processing unit clears an abnormal power failure state;
and when the target equipment is normally shut down, sending a second identifier to the second processing unit so as to clear the continuous power supply time and clear the abnormal power failure state of the second processing unit.
With reference to the third aspect, in a second implementation manner of the third aspect, the triggering, based on the detection signal, an action of the second processing unit further includes:
when receiving the heartbeat signal of second processing unit, control the charge-discharge circuit of second power supply unit charges energy storage module, second power supply unit respectively with second processing unit and first power supply unit are connected, the output of first power supply unit with charge-discharge circuit's input is connected.
With reference to the third aspect, in a third embodiment of the third aspect, the method further includes:
after the target equipment is powered off, monitoring whether a power supply of the target equipment is accessed;
and when the power supply of the target equipment is accessed, controlling the second processing unit to stop alarming and clear the abnormal power-down state, wherein the second processing unit is also used for stopping alarming and clearing the abnormal power-down state when detecting that the switch module of the on-off multiplexing unit is switched on.
According to the alarm method provided by the embodiment of the invention, the trigger condition for stopping the alarm can be that the target equipment is connected with a power supply, or the switch module of the on-off multiplexing unit is conducted, and the alarm can be stopped and the abnormal power failure state can be cleared through any one of the target equipment and the switch module, so that the application scene of the circuit is expanded.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic diagram of an alarm circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an alarm circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a second power supply unit according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of an alarm module according to an embodiment of the invention;
fig. 5 is a schematic structural diagram of an on/off multiplexing unit according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of a switch multiplexing unit according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a second processing unit according to an embodiment of the invention;
FIG. 8 is a flow chart of an alarm method according to an embodiment of the invention;
FIG. 9 is a flow chart of an alarm method according to an embodiment of the present invention;
fig. 10 is a flowchart of an alarm method according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the lines with arrows in the drawings of the present invention only indicate the data flow.
An alarm circuit according to an embodiment of the present invention is shown in fig. 1, and includes a power failure detection unit 10, a first processing unit 20, and a second processing unit 30. The first processing unit 20 is connected to the power failure detection unit 10 and the second processing unit 30, and the second processing unit 30 has an alarm module 31.
Specifically, the power down detection unit 10 is configured to detect whether the target device is powered down. The power failure described herein refers to an abnormal power failure of the target device, not a power failure in a normal shutdown. The power failure detection unit 10 may be connected to a power input terminal of the target device, or may be connected to other power signal terminals of the power failure detection unit 10, where a specific position of the power failure detection unit 10, which is connected to the target device, is not limited, and may be set according to an actual situation. The power failure detection unit 10 may be a voltage detection circuit or a current detection circuit, and when the target device works normally, the detection result of the power failure detection unit 10 is a first voltage value or a first current value; when the target device is abnormally powered off, the detection result of the power-off detection unit 10 is a second voltage value or a second current value.
The power down detection unit 10 transmits a power down signal to the first processing unit 20 after detecting the power down signal of the target device. For example, when the target device works normally, the power down detection unit 10 may send a first signal to the first processing unit 20; when the target device is abnormally powered down, the power down detection unit 10 may send a second signal to the first processing unit 20. The first processing unit 20 may determine whether the target device is currently powered down abnormally according to the signal received by the first processing unit.
The first processing unit 20 may be a processor, or may be a hardware circuit composed of other circuit elements. For example, the first processing unit 20 may be implemented by using a comparison circuit, one end of which is connected to a preset voltage signal or a preset current signal, and the other end of which is connected to the output end of the power down detection circuit 10. The comparison circuit compares the magnitude relationship between the received output signal of the power failure detection circuit 10 and the preset voltage signal or the preset current signal in real time, so as to output the corresponding signal to the second processing unit 30.
The first processing unit 20 is configured to receive the detection signal sent by the power failure detection unit 10, and receive the heartbeat signal sent by the second processing unit 30. Specifically, the second processing unit 30 sends a heartbeat signal to the first processing unit 20, so that the first processing unit 20 can know whether the second processing unit 30 is currently operating normally. When the first processing unit 20 can receive the heartbeat signal sent by the second processing unit 30, it indicates that the second processing unit 30 is working normally; when the first processing unit 20 does not receive the heartbeat signal sent by the second processing unit 30, it indicates that the second processing unit 30 is working abnormally.
The heartbeat signal may be a sine wave signal, a square wave signal, a pulse signal, or the like. The second processing unit 30 may transmit the heartbeat signal at intervals or continuously. The specific waveform type and the sending rule of the heartbeat signal are not limited at all, and may be set according to actual conditions.
For example, the second processing unit 30 may generate a heartbeat signal using a timer and a waveform generation circuit, and transmit the generated heartbeat signal to the first processing unit 20. The second processing unit 30 may further include a comparison circuit, configured to compare the output signal of the first processing unit 20 with a preset signal, so as to determine whether the current target device is powered down abnormally, and trigger a corresponding action of the alarm module 31.
When receiving the detection signal indicating the abnormal power failure of the target device sent by the power failure detection unit 10 and receiving the heartbeat signal sent by the second processing unit 30, the first processing unit 20 may send an alarm signal to the second processing unit 30, so that the second processing unit 30 triggers the alarm module 31 thereof to send out an alarm.
The alarm module 31 may be connected to an alarm signal control end of the second processing unit 30, and when the second processing unit 30 receives the alarm signal sent by the first processing unit 20, the alarm signal control end of the second processing unit 30 triggers the alarm module 31 to send out an alarm. For example, when the target device works normally, the alarm signal control terminal of the second processing unit 30 outputs a low level, and the alarm module 31 is in a standby state; when the target device is powered down abnormally, the alarm signal control end of the second processing unit 30 outputs a high level, and the alarm module 31 gives an alarm. When the target device is abnormally powered off, the alarm signal control end of the second processing unit 30 may also output PWM signals with different frequencies to drive the alarm module 31 to generate an alarm prompt sound that is rapid and pleasant.
In the alarm circuit provided by the embodiment, the second processing unit is provided with the alarm module, the first processing unit triggers the second processing unit to send an alarm when the second processing unit works normally and the power failure detection unit detects that the target device is powered off, and the alarm circuit can avoid the problem that alarm information is difficult to send due to the abnormity of the second processing unit by splitting the detection of the power failure and the alarm triggering into two processing units for processing, so that the safety of the target device using the alarm circuit is improved.
The embodiment of the present invention further provides an alarm circuit, as shown in fig. 2, the alarm circuit includes a power failure detection unit 10, a processor 1, a processor 2, an alarm module 31, a first power supply unit 40, a second power supply unit 50, and a switch multiplexing unit 60. The processor 1 is the first processing unit 20 in the above embodiment, and the second processing unit 30 in the above embodiment includes a processor 2 and an alarm module 31.
The first power supply unit 40 is connected to the processor 1 and the second power supply unit 50, respectively, and the second power supply unit 50 is connected to the processor 2 and the alarm module 31, respectively. The first power supply unit 40 may be a main power supply of the alarm circuit, and the second power supply unit 50 may be an auxiliary power supply of the alarm circuit. When the target device normally works, the alarm circuit is powered by the first power supply unit 40, and the first power supply unit 40 charges the second power supply unit 50; in the event of an abnormal power down of the target device, the first power supply unit 40 is powered down and the alarm circuit is powered by the second power supply unit 50.
Optionally, the first power supply unit 40 may be a power supply chip, or may be another power supply circuit; the second power supply unit 50 may be a tank circuit, for example, a tank circuit formed by a capacitor, an inductor, and other energy storage elements. In a case where the first power supply unit 40 is normally operated, the second power supply unit 50 is charged using the first power supply unit 40. When the target device is abnormally powered down, the alarm circuit is supplied with power using the amount of power stored in the second power supply unit 50. The specific structural details of the first power supply unit 40 and the second power supply unit 50 are not limited at all, and may be set according to actual situations.
The alarm circuit is provided with a first power supply unit 40 and a second power supply unit 50, wherein the first power supply unit 40 is a main power supply, the second power supply unit 50 is an auxiliary power supply, and the alarm circuit is powered by the two power supplies so as to ensure that the alarm module can work normally when the target equipment is powered off.
In some optional embodiments of the present embodiment, as shown in fig. 3, the second power supply unit 50 includes a charging and discharging circuit, an energy storage module, and a voltage dropping circuit.
The input terminal of the charge/discharge circuit is connected to the output terminal vasist of the first power supply unit, and the control terminal of the charge/discharge circuit is connected to the charge/discharge control terminal super _ charge of the second processing unit 30. The charging and discharging circuit is used for charging an energy storage module, and in this embodiment, the energy storage module is a super capacitor C5. The output end of the charge and discharge circuit is connected to the super capacitor C5, and the charge and discharge circuit controls the charge and discharge circuit to charge the super capacitor C5 or discharge the super capacitor C5 under the control of the charge and discharge control end super _ charge of the second processing unit 30. Specifically, when the target device works normally, the second processing unit 30 controls the charging and discharging circuit to charge the super capacitor C5; when the target device is abnormally powered down, the second processing unit 30 controls the charging and discharging circuit to stop charging the super capacitor C5, and at this time, the super capacitor C5 discharges outwards. Here, the control of stopping the charging of the super capacitor C5 by the charge/discharge circuit is controlled by the charge/discharge control terminal super _ charge of the second processing unit 30 and also by the charging period. For example, by setting the charging time period of the charging and discharging circuit to the super capacitor C5 to be 10min, when the charging time period reaches 10min, the charging and discharging circuit also stops charging the super capacitor C5, regardless of whether the target device is currently abnormally powered down.
As shown in fig. 3, the input end of the voltage-reducing circuit is connected to the output end vasisst of the first power supply unit and the output end Vsupercap of the energy storage module, respectively, and the output end of the voltage-reducing circuit is connected to the second processing unit, and is configured to provide the voltage vasisst to the second processing unit.
Further, the charge and discharge circuit further includes a first diode D3, an anode of the first diode D3 is connected to the output terminal vasist of the first power supply unit, a cathode of the first diode D3 is connected to the second terminal S of the first controllable switch Q3, a first terminal Q of the first controllable switch Q3 is connected to the charge and discharge control terminal super _ charge of the second processing unit, and a third terminal D of the first controllable switch Q3 is connected to the super capacitor C5. And a first resistor R11 is also connected between the third end D of the first controllable switch Q3 and the super capacitor C5.
As shown in FIG. 3, the voltage reduction circuit includes a second diode, a third diode, a capacitor C3, a voltage reduction chip U1, an inductor L1, a resistor R10/R4, and a capacitor C4. The anode of the second diode is connected with the output end Vmain of the first power supply unit, the anode of the third diode is connected with the output end Vsupercap of the energy storage module, and the cathode of the second diode and the cathode of the third diode are simultaneously connected to the buck chip U1. The second diode and the third diode are both denoted as D2 in fig. 3.
When the target equipment works normally, Vmini is converted into a Vassist power supply through a voltage reduction circuit to supply power to the processor 2; at this point, Q3 is closed and vasisst charges supercapacitor C5 through current limiting resistor R11. When the target device is abnormally powered down, Q3 is disconnected, Vsupercap is converted into Vassist through the voltage reduction circuit, and power is supplied to the processor 2 and the alarm module. Specifically, the first controllable switch Q3 may be a MOS transistor, and when Super _ charge is low, Q3 is closed, and the Super capacitor C5 is charged; when Super _ charge is high, Q3 is off and the Super capacitor C5 discharges.
And the current limiting resistor R11 is used for Vassist to charge the super capacitor R11 for current limiting. D2 is a selective diode, and when the target device works normally, Vassist is converted by Vmain; when the target device is abnormally powered down, Vmain is 0V, and Vassist is converted by Vsupercap.
The capacitor C3 is an input filter capacitor of the voltage reduction circuit, a DCDC conversion chip U1 is adopted in the voltage reduction circuit to carry out voltage reduction processing on input voltage, the L1 is a DCDC inductor, the R10/R4 is a DCDC feedback resistor, and the C4 is a DCDC output filter capacitor.
Preferably, TPS61021A manufactured by TI company is adopted as the voltage reduction chip U1, the voltage input range of the chip is 0.5V-4.4V, and the output voltage is 1.8V-4.0V; through TI official network design, under the condition of 0.5V-3.3V input and 3.3V/6mA output load, the conversion efficiency exceeds 80%. The super capacitor C5 is made of ELNA DZ-2R7D475H5T, has the advantages of high charging speed, long cycle service life, 50 ten thousand times of deep charging and discharging cycle use, no memory effect, super-strong heavy current discharging capacity, high energy conversion efficiency, small process loss, more than or equal to 90 percent of heavy current energy cycle efficiency, simple charging and discharging circuit, no need of a charging circuit like a rechargeable battery, high safety factor and no maintenance after long-term use, and the rated capacity of the super capacitor can be more than 95 percent after 5min of charging.
Fig. 4 shows a schematic diagram of an alarm module comprising a second controllable switch Q1 and a sound emitting component. The first end of the second controllable switch Q1 is connected with the alarm signal output end Speaker _ pwm of the second processing unit, the third end of the second controllable switch Q2 is connected with the sound-producing component, and the sound-producing component is connected with the output end vasist of the second power supply unit. In the present embodiment, the sound emission part employs a buzzer BZ 1. Preferably, the buzzer BZ1 is a permanent sound passive buzzer PT-2130PQ, the response frequency is 3.0KHZ, the rated working voltage is 5V, and the rated current is not more than 5 mA. The alarm signal output end Speaker _ PWM of the second processing unit can output PWM waves with two frequencies of 3KHZ &3.4KHZ to drive the buzzer BZ1 to sound.
Further, the alarm module further comprises a current limiting resistor R1, a pull-down resistor R2 and an impedance matching resistor R12. The pull-down resistor R2 is used to keep the second controllable switch Q1 in an off state when the processor 2 is powered up or down. The impedance matching resistor R12 is used for releasing the electric energy accumulated by the buzzer in the buzzer BZ 1.
In some optional implementations of this embodiment, the switching and shutdown multiplexing unit includes a switching module, a third diode, and a fourth diode. The cathode of the third diode is connected with the switch module, and the anode of the third diode is connected with the output terminal Vassist of the second power supply unit and the reset detection terminal Alarm _ key of the second processing unit respectively; the cathode of the fourth diode is connected with the switch module, and the anode of the fourth diode is connected with the output end Vmain of the first Power supply unit and the Power _ switch of the on-off detection end of the first processing unit.
As shown in fig. 5, the switch module is implemented by using a key SW 1. Specifically, when the key SW1 is closed, the Alarm _ key and the Power _ switch are simultaneously at low level. When the target equipment works normally, the processor 1 is started and shut down by detecting the Power _ switch level; when the target equipment is abnormally powered off, the processor 2 controls the Alarm module to be switched on and off by detecting the Alarm _ key level. Of course, the switch module is not limited to the keys shown in fig. 5, and may be other types of switches, such as buttons, toggle switches, and the like.
Further, as shown in fig. 6, the switching multiplexing unit further includes a third controllable switch Q2, a pull-up resistor R7, and voltage dividing resistors R6 and R8. The second end of the third controllable switch Q2 is connected to the output terminal Vmain of the first Power supply unit, the first end of the third controllable switch Q2 is connected to the anode of the fourth diode, and the third end of the third controllable switch Q2 is connected to the Power _ switch _ signal of the switching detection terminal of the first processing unit. The pull-up resistor R7 enables the third controllable switch Q2 to keep an off state when the target device is powered on and powered off; the divider resistors R6 and R8 ensure that the high level of the Power _ switch _ signal input is within the high level required voltage range of the processor 1; the current limiting resistor R5 is a current limiting resistor; the third diode and the fourth diode are used for ensuring that the Alarm _ key and the Power _ switch voltage signals are isolated.
In some alternative implementations of the present embodiment, fig. 7 shows a pin diagram of the processor 2. Specifically, the processor 2 controls the charging and discharging of the Super capacitor C5 through a pin Super _ charge; receiving a power-down detection signal sent by the processor 1 through pins MCU1_ TO _ MCU2_1 and MCU1_ TO _ MCU2_ 2; sending a heartbeat signal TO the processor 1 through the MCU2_ TO _ MCU1_ 1; when the target equipment is abnormally powered off, generating PWM waves through a pin Speaker _ PWM to drive an alarm unit to sound; when the switch module in the on-off multiplexing unit is pressed down or the processor 1 detects that the power supply is switched on again, the low level is detected through the Alarm _ key, and the Alarm module is closed.
Specifically, when two IOs of the processor 1 send "10 or 11" levels TO the pins MCU1_ TO _ MCU2_1 and MCU1_ TO _ MCU2_2 of the processor 2, indicating that the target device is working normally at this time, the processor 2 turns off the buzzer alarm; when two IOs of the processor 1 send '01' levels TO pins MCU1_ TO _ MCU2_1 and MCU1_ TO _ MCU2_2 of the processor 2, indicating that the target device is normally powered off at the moment, the processor 2 turns off the buzzer TO alarm; only when two IO of the processor 1 send a "00" level TO the pins MCU1_ TO _ MCU2_1 and MCU1_ TO _ MCU2_2 of the processor 2, which indicate that the target device is abnormally powered down at this time, the processor 2 drives the alarm module TO sound until the processor 1 detects that the power supply is reconnected or the key SW1 in the power on/off multiplexing unit is pressed, the buzzer is not driven. Meanwhile, after the system is powered on, the processor 1 determines whether the processor 2 functions normally by detecting a square wave with a fixed frequency sent by the pin MCU2_ TO _ MCU1 of the processor 2.
The resistor R3 and the capacitor C1 form an automatic reset circuit, so that the processor 2U2 is automatically reset when powered on.
Preferably, the processor 2U2 is a global minimum MCU based on the ARMR technology, employing NXP MKL03Z8VFG4, with ultra-small size and ultra-low power consumption. The processor 2 adopts a micro package, comprises 1.6x 2.0mm2 WLCSP, the operation power consumption is as low as 50 muA/MHz, the static power consumption is as low as 2.2 muA, the wake-up time of a sleep site is completely kept to be 7.5 mus, and the lowest static mode current during deep sleep is as low as 77 nA; and highly integrated peripherals including a brand new ROM boot program, a high-precision internal voltage reference and the like.
The alarm circuit adopts the mode that the double MCUs detect the power-off alarm signal and drive the alarm unit to sound respectively, and greatly prolongs the power-down alarm time under the condition of limited capacity of the super capacitor. The power supply mode of the super capacitor is more reliable and the service life is longer than that of a rechargeable button lithium battery; the alarm unit adopts a mode of alternately driving the passive buzzer by two different frequencies, so that the alarm unit can drive the active buzzer by a single frequency to be more urgent and more pleasant to the ear to alarm and prompt; the on-off reuse is a power-down alarm prompt tone key switch, so that the whole machine structure is simpler and controllable. The circuit has the advantages of simple structure, reliable control, long alarm time and the like.
The embodiment of the invention also provides medical equipment which comprises an equipment body and an alarm circuit. The alarm circuit is connected with the power input end of the equipment body and used for detecting whether the equipment body is powered down or not so as to trigger alarm.
For example, when the alarm circuit is applied to a monitor, the device body is the monitor, and the alarm circuit is arranged in the monitor and used for detecting that the monitor is powered off to trigger alarm.
For details of the alarm circuit, please refer to the detailed description of the embodiments shown in fig. 1 to 7, which is not repeated herein.
In accordance with an embodiment of the present invention, there is provided an alarm method embodiment, it being noted that the steps illustrated in the flowchart of the drawings may be performed in a computer system such as a set of computer-executable instructions and that, although a logical order is illustrated in the flowchart, in some cases the steps illustrated or described may be performed in an order different than presented herein.
In the embodiment, an alarm method is provided, which can be used in a first processing unit of the above target device, for example, a first processing unit of a medical device, and fig. 8 is a flowchart of the alarm method according to the embodiment of the present invention, as shown in fig. 8, the flowchart includes the following steps:
s11, receiving the detection signal of the power down detection unit.
The power failure detection unit is used for detecting whether the target device is powered down.
The first processing unit receives a detection signal of the power failure detection unit, and when the power failure detection unit detects that the target device works normally, the first processing unit receives a first signal; and when the power failure detection unit detects abnormal power failure of the target equipment, the first processing unit receives the second signal. Therefore, the first processing unit can determine the current working state of the target device according to the signal received from the power failure detection unit.
And S12, judging whether the heartbeat signal of the second processing unit is received.
When the second processing unit works normally, the second processing unit sends a heartbeat signal to the first processing unit; when the second processing unit is abnormal, the first processing unit cannot receive the heartbeat signal of the second processing unit.
When receiving the heartbeat signal of the second processing unit, indicating that the second processing unit works normally at the moment, executing S13; otherwise, it indicates that the second processing unit is abnormal at this time, S11 is executed, or a prompt may be sent to the user.
And S13, triggering the action of the second processing unit based on the detection signal so as to trigger the second processing unit to send out an alarm when the target equipment is powered down.
And under the condition that the second processing unit works normally, the first processing unit triggers the action of the second processing unit based on the difference of the detection signals. For example, when the target device is powered down, the second processing unit is triggered to send out an alarm.
Details about this step will be described later.
According to the alarm method provided by the embodiment, the detection of power failure and the alarm triggering are split into the two processing units for processing, so that the problem that alarm information is difficult to send due to the abnormality of the second processing unit can be avoided, and the safety of medical equipment is improved.
In the present embodiment, an alarm method is provided, which can be used in the above-mentioned target device, for example, a medical device, and fig. 9 is a flowchart of the alarm method according to the embodiment of the present invention, as shown in fig. 9, the flowchart includes the following steps:
s21, receiving the detection signal of the power down detection unit.
The power failure detection unit is used for detecting whether the target device is powered down.
Please refer to S11 in fig. 8, which is not described herein.
And S22, judging whether the heartbeat signal of the second processing unit is received.
Executing S23 when the heartbeat signal of the second processing unit is received; otherwise, S21 is executed.
Please refer to S12 in fig. 8, which is not described herein.
And S23, controlling the charging and discharging circuit of the second power supply unit to charge the energy storage module.
When the second processing unit works normally, the first processing unit controls the charge and discharge circuit of the second processing unit to charge the energy storage module. For details of the second power supply unit and its operation principle, please refer to the above description, which is not repeated herein.
Optionally, the first processing unit may count the charging duration, and when the charging duration reaches the preset charging duration, the energy storage module is stopped to be charged.
And S24, triggering the second processing unit to work based on the detection signal so as to trigger the second processing unit to send out an alarm when the target equipment is powered down.
The operation state of the target device can be classified into the following three cases:
(1) normal operation of the target device
(2) Normal shutdown of target device
(3) Abnormal power down of target device
In the following, the actions performed by the first processing unit and the second processing unit in the above three cases will be described in detail.
Specifically, the step S24 includes the following steps:
and S241, judging whether the target equipment is powered down.
As described above, whether the target device is powered down is obtained by performing power down detection on the target device by the power down detection unit. For details, please refer to the above description, which is not repeated herein.
When the target device is not powered off and the target device is in normal operation, executing S242; when the target device is not powered off and the target device is normally powered off, S243 is executed; when the target device is powered down, S244 is performed.
And S242, sending the first identifier to the second processing unit so that the second processing unit clears the abnormal power failure state.
When the target device works normally, the first processing unit sends the first identifier to the second processing unit. For example, the two IOs of the first processing unit send "10 or 11" level TO the pin MCU1_ TO _ MCU2_1 and the pin MCU1_ TO _ MCU2_2 of the processor 2 in the second processing unit, and the second processing unit clears the abnormal power-down state after receiving the first identifier sent by the first processing unit.
And S243, sending a second identifier to the second processing unit, so that the second processing unit clears the continuous power supply time and clears the abnormal power failure state.
And when the target equipment is normally powered off, the first processing unit sends the second identifier to the second processing unit. For example, the two IOs of the first processing unit send "01" levels TO the MCU1_ TO _ MCU2_1 and the MCU1_ TO _ MCU2_2 of the pin of the processor 2 in the second processing unit, and the second processing unit clears the continuous power supply time and clears the abnormal power-down state after receiving the second identifier sent by the first processing unit. The continuous power supply time is the duration of continuous charging of the energy storage module.
And S244, triggering the second processing unit to send out an alarm.
When the target device is abnormally powered down, the two IOs of the first processing unit send "00" level TO pins MCU1_ TO _ MCU2_1 and MCU1_ TO _ MCU2_2 of processor 2. And when the target equipment is abnormally powered off, triggering the second processing unit to send out an alarm.
And S25, monitoring whether the power supply of the target device is connected.
After the target device is abnormal in power failure, the first processing unit monitors whether the power supply of the target device is connected again. When the power of the target device is accessed, S26 is executed; otherwise, S25 is executed.
And S26, controlling the second processing unit to stop alarming and clear the abnormal power-down state.
And the second processing unit is also used for stopping alarming and clearing the abnormal power failure state when detecting that the switch module of the on-off multiplexing unit is switched on.
When the power supply of the target equipment is accessed again, the first processing unit controls the second processing unit to stop alarming and clear the abnormal power failure state.
According to the alarm method provided by the embodiment, the trigger condition for stopping the alarm can be that the target equipment is connected with the power supply, or the switch module of the on-off multiplexing unit is conducted, and the alarm can be stopped and the abnormal power-down state can be cleared through any one of the target equipment and the switch module, so that the application scene of the circuit is expanded.
As a specific application example of this embodiment, as shown in fig. 10, the alarm method may include the following steps:
s1, the target device initializes and processor 1 and processor 2 start operating.
S2, the processor 1 detects whether the power supply of the target equipment is normal, if the power supply of the target equipment is abnormal, the target equipment is reinitialized; and if the power supply of the target equipment is normal, the next step is carried out.
S3, the processor 1 determines whether the processor 2 can work normally by detecting the square wave signal sent by the processor 2. If the processor 2 sends signal waveform, frequency and amplitude abnormity, the system is initialized again; if the signal sent by the detection processor 2 is normal, the next step is carried out.
And S4, the processor 2 opens the super capacitor charging switch, and after charging for 10min, the next step is carried out.
S5, the processor 1 detects whether the target device has been powered down unexpectedly. When the target device works normally, the processor 1 sends a level of '10 or 11' to the processor 2 through two IO pins; when the target equipment is abnormally powered down, the processor 1 sends a '00' level to the processor 2 through two IO pins; when the target device is normally powered off, processor 1 sends a "01" level to processor 2 through two IO pins.
S6, the processor 2 receives the normal power supply signal of the processor 1, and returns to the step S5 that the processor 1 detects whether the target device is powered down accidentally.
And S7, the processor 2 receives the abnormal power-down signal of the target device of the processor 1, and the processor 2 drives the alarm unit to sound until the processor 1 detects that the power supply is reinserted or the key in the on-off multiplexing unit is pressed.
And S8, the processor 2 receives the target equipment normal shutdown signal detected by the processor 1, and clears the continuous power supply time and the abnormal power failure state.
And S9, the processor 2 receives the abnormal power failure signal of the target device of the processor 1, and stops the alarm of the buzzer and clears the abnormal power failure alarm if the processor 1 detects that the power supply is inserted again.
And S10, stopping the alarm of the buzzer, clearing the abnormal power failure alarm, and waiting for the power-on initialization again by the system.
S11, the processor 2 receives the abnormal power failure signal of the whole processor 1, if the processor 2 detects that the multiplexing button is pressed, the buzzer is stopped to alarm, and the abnormal power failure alarm is cleared; otherwise, S13 is executed. Wherein, S9 and S11 are a parallel process.
S12, S12 is the same as S10.
And S13, turning on a buzzer to alarm.
When the target equipment is abnormally powered down, the second power supply unit only supplies power to the processor 2 and the alarm unit, so that the power consumption of the whole machine is extremely low, and the processor 2 drives the alarm unit to sound.
Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope defined by the appended claims.
Claims (13)
1. An alarm circuit, comprising:
the power failure detection unit is used for detecting whether the target equipment has power failure;
the second processing unit is provided with an alarm module;
the first processing unit is connected with the power failure detection unit and the second processing unit; the first processing unit is used for receiving the detection signal of the power failure detection unit and the heartbeat signal of the second processing unit so as to trigger the second processing unit to send out an alarm when the second processing unit works normally and the target device is powered off.
2. The alarm circuit of claim 1, further comprising:
the first power supply unit is connected with the first processing unit and the second power supply unit;
the second power supply unit is connected with the second processing unit.
3. The alarm circuit of claim 2, wherein the second power supply unit comprises:
the input end of the charging and discharging circuit is connected with the output end of the first power supply unit, and the control end of the charging and discharging circuit is connected with the charging and discharging control end of the second processing unit;
the energy storage module is connected with the output end of the charge and discharge circuit;
and the input end of the voltage reduction circuit is connected with the output end of the first power supply unit and the output end of the energy storage module respectively, and the output end of the voltage reduction circuit is connected with the second processing unit.
4. The alarm circuit of claim 3, wherein the charging and discharging circuit comprises:
the anode of the first diode is connected with the output end of the first power supply unit, and the cathode of the first diode is connected with the second end of the first controllable switch;
and a first end of the first controllable switch is connected with the charge-discharge control end of the second processing unit, and a third end of the first controllable switch is connected with the energy storage module.
5. The alarm circuit of claim 3, wherein the voltage reduction circuit comprises:
a second diode having an anode connected to an output terminal of the first power supply unit;
the anode of the third diode is connected with the output end of the energy storage module, and the cathode of the third diode and the cathode of the second diode are simultaneously connected to the buck chip;
and the output end of the voltage reduction chip is connected with the second processing unit.
6. The alarm circuit of claim 2, wherein the alarm module comprises:
a first end of the second controllable switch is connected with the alarm signal output end of the second processing unit, and a third end of the second controllable switch is connected with the sound production component;
and the sounding component is connected with the output end of the second power supply unit.
7. The alarm circuit according to any one of claims 2-6, wherein the alarm circuit further comprises a power on/off multiplexing unit; wherein, the on-off multiplexing unit comprises:
a switch module;
a cathode of the third diode is connected with the switch module, and an anode of the third diode is respectively connected with an output end of the second power supply unit and a reset detection end of the second processing unit;
and the cathode of the fourth diode is connected with the switch module, and the anode of the fourth diode is respectively connected with the output end of the first power supply unit and the on-off detection end of the first processing unit.
8. The alarm circuit of claim 7, wherein the on/off multiplexing unit further comprises:
and a second end of the third controllable switch is connected with the output end of the first power supply unit, a first end of the third controllable switch is connected with the anode of the fourth diode, and a third end of the third controllable switch is connected with the startup and shutdown detection end.
9. A medical device, comprising:
an apparatus body;
the alarm circuit of any one of claims 1-8, connected to a power input of the device body, the alarm circuit for detecting whether the device body is powered down to trigger an alarm.
10. An alarm method, comprising:
receiving a detection signal of a power failure detection unit, wherein the power failure detection unit is used for detecting whether target equipment has power failure;
judging whether a heartbeat signal of the second processing unit is received or not;
and when the heartbeat signal of the second processing unit is received, triggering the action of the second processing unit based on the detection signal so as to trigger the second processing unit to send out an alarm when the target equipment is powered off.
11. The method of claim 10, wherein the act of triggering the second processing unit based on the detection signal comprises:
when the target equipment is normally powered on, sending a first identifier to the second processing unit so that the second processing unit clears an abnormal power failure state;
and when the target equipment is normally shut down, sending a second identifier to the second processing unit so as to clear the continuous power supply time and clear the abnormal power failure state of the second processing unit.
12. The method of claim 10, wherein the act of triggering the second processing unit based on the detection signal further comprises:
when receiving the heartbeat signal of second processing unit, control the charge-discharge circuit of second power supply unit and charge to energy storage module, second power supply unit respectively with second processing unit and first power supply unit are connected, first power supply unit's output with charge-discharge circuit's input is connected.
13. The method of claim 10, further comprising:
after the target equipment is powered off, monitoring whether a power supply of the target equipment is accessed;
and when the power supply of the target equipment is accessed, controlling the second processing unit to stop alarming and clear the abnormal power failure state, wherein the second processing unit is also used for stopping alarming and clearing the abnormal power failure state when detecting that the switch module of the on-off multiplexing unit is switched on.
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