CN114511492A - Circuit board detection method, circuit board detection device and computer readable storage medium - Google Patents
Circuit board detection method, circuit board detection device and computer readable storage medium Download PDFInfo
- Publication number
- CN114511492A CN114511492A CN202111539228.4A CN202111539228A CN114511492A CN 114511492 A CN114511492 A CN 114511492A CN 202111539228 A CN202111539228 A CN 202111539228A CN 114511492 A CN114511492 A CN 114511492A
- Authority
- CN
- China
- Prior art keywords
- circuit board
- layer
- detected
- image
- core
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T7/00—Image analysis
- G06T7/0002—Inspection of images, e.g. flaw detection
- G06T7/0004—Industrial image inspection
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2207/00—Indexing scheme for image analysis or image enhancement
- G06T2207/30—Subject of image; Context of image processing
- G06T2207/30108—Industrial image inspection
- G06T2207/30141—Printed circuit board [PCB]
Abstract
The application discloses a circuit board detection method, a detection device and a computer readable storage medium, wherein the detection method comprises the following steps: obtaining a circuit board to be detected; wherein, at least one set position of each layer of core board of the circuit board to be detected is provided with a corresponding layer of Cedrub figure; carrying out first image acquisition on a layer deviation Kebang graph of a circuit board to be detected; and responding to the fact that the layer deviation Coco graph of at least one layer core board of the circuit board to be detected deviates based on the collected first image, and performing early warning output. In this way, this application can reduce personnel and detect intensity, avoids the staff healthy impaired, can also improve detection efficiency to reduce the risk and the waste that the false retrieval or miss-detection result in, thereby improve production efficiency.
Description
Technical Field
The present disclosure relates to the field of circuit board manufacturing, and in particular, to a circuit board detection method, a circuit board detection device, and a computer-readable storage medium.
Background
With the development of the 5G technology, the functions of electronic products are more and more comprehensive, the requirements for Circuit boards are higher and higher, and the development of the PCB (printed Circuit board) industry towards high density, high integration and multilayering is driven, and with the stricter requirement for the interlayer alignment precision of the PCB, the problem of layer deviation appears. In the manufacturing process of the multilayer PCB, if the layer between the inner layer circuit and the outer layer circuit exceeds the standard, the reliability risks such as conduction failure between layers, copper leakage during cutting and the like can be caused.
In the prior art, the monitoring of the layer deviation is generally added in the manufacturing process to confirm the layer deviation condition of the PCB. For example, after the outer layer circuit of the PCB is processed, the PCB needs to be sliced at a position where the layer offset kebang pattern is disposed, and the actual layer offset needs to be determined by manually measuring the position.
However, if the mass production product needs manual full inspection, a large amount of repeated mechanical work can lead to low efficiency, and manual judgment often fails, which causes the abnormal scrapping of the plate layer and leads to unnecessary process cost waste. Further, the staff visually inspect Kobang continuously use eyestrain, which easily causes visual deterioration and affects the health of the staff.
Disclosure of Invention
The technical problem mainly solved by the application is to provide a circuit board detection method, a detection device and a computer readable storage medium, which can solve the problems of low efficiency and health damage caused by manual detection of PCB layer deviation.
In order to solve the above technical problem, a first technical solution adopted by the present application is to provide a circuit board detection method, including: obtaining a circuit board to be detected; wherein, at least one set position of each layer of core board of the circuit board to be detected is provided with a corresponding layer of Cedrub figure; carrying out first image acquisition on a layer deviation Kebang graph of a circuit board to be detected; and responding to the fact that the layer deviation Coco graph of at least one layer core board of the circuit board to be detected deviates based on the collected first image, and performing early warning output.
The method comprises the following steps of responding to the situation that the layer deviation Conation graph of at least one layer core board of the circuit board to be detected deviates based on the collected first image, and outputting early warning, and specifically comprises the following steps: and determining that the layer-side Cowbond graphs of at least two layers of core boards of the circuit board to be detected are tangent based on the first image, and determining that the layer-side Cowbond graphs of the circuit board to be detected are deviated.
Wherein, treat that the settlement position of layer part nation graph on every layer core board of circuit board is the same, treat that the layer part nation graph of detecting the circuit board carries out the step of first image acquisition, include: and photographing the layer deviation nation graph corresponding to the set position from one side of the circuit board to be detected by using photographing equipment to obtain a first image.
Wherein, utilize the shooting equipment to shoot the layer partially nation figure that the settlement position corresponds from one side of waiting to detect the circuit board, obtain the step of first image, specifically include: acquiring specific coordinates of a upper layer askoppon figure of a core plate at one side of a circuit board to be detected; and photographing the layer deviation Cowbond graph at the specific coordinate to acquire a first image.
The layer-level Kebang graphics of the circuit boards in different set positions or different models have different gradient offset values; responding to the situation that the layer deviation Coco graph of at least one layer core plate of the circuit board to be detected deviates based on the collected first image, and outputting early warning, wherein the step comprises the following steps: determining that the layer Cedrupont graph of at least one layer of core board of the circuit board to be detected deviates according to the precision requirement matched with the gradient deviation value of each layer Cedrupont graph.
The circuit board detection method further comprises the following steps: and sending the circuit board to be detected to the next procedure in response to determining that the layer deviation Cowbond graph of at least one layer core board of the circuit board to be detected does not deviate based on the acquired first image.
The circuit board to be detected is characterized in that a corresponding plate number is arranged at a preset position of each layer of core board of the circuit board to be detected; the circuit board detection method further comprises the following steps: carrying out second image acquisition on plate numbers corresponding to each layer of core plate of the circuit board to be detected; and responding to the situation that the plate number of at least one layer of core plate of the circuit board to be detected is inconsistent with the plate numbers of the other layers of core plates based on the acquired second image, and performing early warning output.
Wherein, treat that the plate number that every layer of core plate of inspection circuit board corresponds carries out the step of second image acquisition, specifically includes: and photographing the plate number corresponding to the preset position from one side of the circuit board to be detected by using photographing equipment to obtain a second image.
In order to solve the above technical problem, a second technical solution adopted by the present application is to provide a detection apparatus, including: a memory for storing program data, wherein when the stored program data is executed, the steps of the circuit board detection method are realized; and the processor is used for executing the program instructions stored in the memory to realize the steps in the circuit board detection method.
In order to solve the above technical problem, a third technical solution adopted by the present application is to provide a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps in the circuit board detection method according to any one of the above items are implemented.
The beneficial effect of this application is: different from the prior art, the application provides a circuit board detection method, a detection device and a computer-readable storage medium, the first image of the corresponding layer-side Cowbond graph of the circuit board to be detected is automatically acquired, layer-side judgment is carried out based on the acquired first image, and early warning output is carried out when the layer-side Cowbond graph of at least one layer core board of the circuit board to be detected is determined to deviate, so that the personnel detection intensity is reduced, the damage to the health of workers is avoided, the detection efficiency can be improved, the risk and waste caused by false detection or missing detection are reduced, and the production efficiency is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic flow chart diagram of an embodiment of a circuit board inspection method according to the present application;
FIG. 2 is a schematic diagram of a structure of an embodiment of a layer Centraalbond graph according to the present application;
FIG. 3 is a schematic structural diagram of an embodiment of a circuit board to be tested according to the present application;
FIG. 4 is a schematic flow chart of another embodiment of the circuit board inspection method of the present application;
FIG. 5 is a schematic structural diagram of an embodiment of the detection apparatus of the present application;
FIG. 6 is a schematic structural diagram of an embodiment of a computer-readable storage medium according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, the "plural" includes at least two in general, but does not exclude the presence of at least one.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
It should be understood that the terms "comprises," "comprising," or any other variation thereof, as used herein, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
In the prior art, the monitoring of the layer deviation is generally added in the manufacturing process to confirm the layer deviation condition of the PCB. For example, after the outer layer circuit of the PCB is processed, the PCB needs to be sliced at a position where the layer offset kebang pattern is disposed, and the actual layer offset needs to be determined by manually measuring the position. However, if the mass production product needs manual full inspection, a large amount of repeated mechanical work can lead to low efficiency, and manual judgment often fails, which causes the abnormal scrapping of the plate layer and leads to unnecessary process cost waste. Further, the staff visually inspect Kobang continuously use eyestrain, which easily causes visual deterioration and affects the health of the staff.
Based on the above situation, the application provides a circuit board detection method, a detection device and a computer readable storage medium, which can solve the problems of low efficiency and health damage caused by manual detection of PCB layer deviation.
The present application will be described in detail below with reference to the drawings and embodiments.
Referring to fig. 1, fig. 1 is a schematic flow chart of an embodiment of a circuit board detection method according to the present application. As shown in fig. 1, in the present embodiment, the method includes:
s11: acquiring a circuit board to be detected; wherein, at least one set position of each layer of core board of the circuit board to be detected is provided with a corresponding layer of Cedrub figure.
In this embodiment, the circuit board to be detected is a circuit board for completing the outer-layer circuit processing.
The kebang graph refers to a general name of a tool graph or a hole for monitoring, and the layer bias kebang graph used in the present embodiment is a tool graph for monitoring a layer bias.
The set position refers to a position on the core board where the layer deviation kebab graph is arranged, and one or more set positions can be arranged on each layer of the core board to monitor the layer deviation of different areas, which is not limited in the application.
In this embodiment, the layer-top graph is rectangular as a whole.
Specifically, please refer to fig. 2, fig. 2 is a schematic structural diagram of an embodiment of a layer-top meta-nation diagram of the present application. As shown in fig. 2, the layer-partion bond pattern 100 includes a rectangular copper frame 10 and a rectangular frame 20, where the rectangular copper frame 10 is an outer copper frame and the rectangular frame 20 is an inner copper layer. The rectangular copper frame 10 and the rectangular frame 20 have a certain distance D, which is an allowable error between the outer copper frame and the inner copper layer, for example, 25 kobang means that an allowable offset value between the rectangular copper frame 10 and the rectangular frame 20 is 25 micrometers, and 75 kobang means that an allowable offset value between the rectangular copper frame 10 and the rectangular frame 20 is 75 micrometers.
In this embodiment, the layer offset kebab patterns used at the same set position on each core board are completely the same. In the multilayer circuit board, it can be understood that only if the layer offset kebab patterns at the same set position on each layer of core board are completely the same, whether the layer offset between the layers meets the precision requirement can be judged.
In this embodiment, the layer-level coop graphics of the circuit board in different set positions or different types may have different gradient offset values. It can be understood that the areas corresponding to different set positions are different, the required precision of the line is also different, and the requirements of different types of products on the layer offset can be met by using the layer offset kebang graphs with different gradient offset values. For example, some plates may have high precision requirements using a 25 kebang layer-offset kebang pattern, and some plates may have lower precision requirements using a 75 kebang, 90 kebang, or even a 110 kebang layer-offset kebang pattern.
Specifically, please refer to fig. 3, wherein fig. 3 is a schematic structural diagram of an embodiment of the circuit board to be detected according to the present application. As shown in fig. 3, the circuit board 200 to be tested includes 4 different setting positions in total, namely, a first setting position 11, a second setting position 12, a third setting position 13, and a fourth setting position 14.
The first setting position 11, the second setting position 12, the third setting position 13, and the fourth setting position 14 may use layer-part kebang patterns with the same precision requirement, or may use different layer-part kebang patterns according to different requirements, which is not limited in the present application.
S12: and carrying out first image acquisition on the layer deviation Kebang graph of the circuit board to be detected.
In the embodiment, the image of the layer deviation kebab figure corresponding to the set position is photographed from one side of the circuit board to be detected by using the photographing device, so that a first image is obtained.
Specifically, specific coordinates of an upper layer of a core board of the circuit board to be detected are obtained, and the upper layer of the core board at the specific coordinates is photographed to obtain a first image.
And the core board at one side of the circuit board to be detected refers to the outermost core board of the circuit board to be detected.
In this embodiment, the shooting device is connected to an Artificial Intelligence (AI) software, and the specific coordinates of the border graphic in the layer of the circuit board to be detected are input into the AI software, so that the shooting device can only shoot the image at the specific coordinates without shooting the whole board.
S13: and responding to the fact that the layer deviation Coco graph of at least one layer core board of the circuit board to be detected deviates based on the collected first image, and performing early warning output.
In this embodiment, it is determined that the layer-part koppon patterns of the at least two core boards of the circuit board to be detected are offset in response to determining that the layer-part koppon patterns of the at least two core boards of the circuit board to be detected are tangent based on the first image.
The tangency of the layer-partion bond graphs of the at least two layers of core boards means that pixel points of two rectangular frames in the first image are overlapped.
In this embodiment, the occurrence of the offset of the layer partiunder pattern of at least one layer core board of the circuit board to be detected is determined by using the accuracy requirement matched with the gradient offset value of each layer partiunder pattern.
Specifically, after the shooting equipment collects the first image, the first image is transmitted to the AI software, the AI software identifies the first image to determine whether a pixel point overlapping phenomenon exists, and if the pixel point overlapping phenomenon exists, early warning output is immediately performed so that an operator can timely process unqualified PCB boards.
In this embodiment, in response to determining that the layer deviation cooppon pattern of at least one layer core board of the circuit board to be detected does not deviate based on the acquired first image, the circuit board to be detected is sent to the next process.
According to the image acquisition system, the AI software is used for controlling the shooting equipment to acquire the first image, the AI software is used for identifying the first image, and machine detection can be used for replacing manual detection, so that the problems of false detection, missing detection, low efficiency, health damage and the like caused by manual detection are avoided.
Be different from prior art, this embodiment treats the first image of the corresponding layer part of the branch of the academic or vocational study nation graphic of circuit board through automatic acquisition to carry out the layer part of the country based on the first image of collection and judge, and when confirming that the layer part of the layer of at least one layer core board of treating the circuit board of treating the skew appears, carry out early warning output, not only reduced personnel and detected intensity, avoid staff healthy impaired, can also improve detection efficiency, and reduce the risk and the waste that wrong examination or missed measure lead to, thereby improve production efficiency.
Furthermore, in the application, corresponding plate numbers (ID) are arranged at preset positions of each layer of core board of the circuit board to be detected, the corresponding plate numbers are a group of character strings which are composed of 0-9 numbers and used for distinguishing identity information in the plate machining process, and the content of the character strings can be directly recognized by naked eyes relative to the two-dimensional codes, and the character strings are also called as plain codes.
In the production and manufacturing process of the PCB, each layer plate piece has a plate ID in order to meet the processing control of semi-finished products. For a multilayer PCB, each layer of core board has a board ID to meet the transmission of processing information of inner and outer layers of boards, so that the consistency of the board IDs among the layers of the multilayer board is very important. In the prior art, a manual sampling inspection mode is often adopted to inspect whether plate IDs in a multilayer PCB are consistent, the sampling inspection is easy to cause missing inspection, and the mode still increases the workload of staff.
Based on this, please refer to fig. 4, fig. 4 is a schematic flow chart of a circuit board detection method according to another embodiment of the present application. As shown in fig. 4, in the present embodiment, the method includes:
s21: and carrying out second image acquisition on plate numbers corresponding to each layer of core plate of the circuit board to be detected.
In the embodiment, the positions of the plate numbers of each layer of core plate are adjacent, and in the processing process, the positions of the plate numbers of the lower layer of core plate covered by the upper layer of core plate are bitten into the positions to expose the plate numbers of each layer of core plate, so that the plate numbers of each layer of core plate are not shielded during photographing.
In the embodiment, the plate numbers corresponding to the preset positions are photographed from one side of the circuit board to be detected by using the photographing device, and a second image is obtained.
Specifically, specific coordinates of plate numbers on a core plate on one side of the circuit board to be detected are obtained, and a plurality of plate numbers at the specific coordinates are photographed to obtain a second image.
In this embodiment, the shooting device is connected to an Artificial Intelligence (AI) software, and the specific coordinates of the plate numbers on each layer of the core board in the circuit board to be detected are input into the AI software, so that the shooting device can only shoot images at the specific coordinates without shooting the whole board.
S22: and responding to the situation that the plate number of at least one layer of core plate of the circuit board to be detected is inconsistent with the plate numbers of the other layers of core plates based on the acquired second image, and performing early warning output.
In the embodiment, after the shooting equipment collects the second image, the second image is transmitted to the AI software, the AI software identifies the second image to determine whether the plate codes are inconsistent, and if the plate codes are inconsistent, early warning output is immediately performed so that an operator can timely handle the unqualified PCB.
In this embodiment, in response to determining that the plate number of at least one layer of core board of the circuit board to be detected is identical to the plate numbers of the remaining layers of core boards based on the acquired second image, the circuit board to be detected is sent to the next process.
The AI software is used for controlling the shooting equipment to acquire the second image, the AI software is used for identifying the second image, and the machine detection can be used for replacing manual spot inspection, so that the problems of false detection, missing detection, low efficiency, health damage and the like caused by manual spot inspection are avoided.
Correspondingly, the application provides a detection device.
Specifically, please refer to fig. 5, fig. 5 is a schematic structural diagram of an embodiment of the detection apparatus of the present application. As shown in fig. 5, the detection device 50 includes a memory 51 and a processor 52 coupled to each other.
In this embodiment, the memory 51 is used for storing program data, and the program data can realize the steps of the circuit board detection method according to any one of the above embodiments when executed; the processor 52 is configured to execute the program instructions stored in the memory 51 to implement the steps in any of the above embodiments or the steps correspondingly executed by the detection device 50 in any of the above embodiments. The detection device 50 may include a touch screen, a communication circuit, etc. in addition to the processor 52 and the memory 51, which are not limited herein.
Specifically, the processor 52 is configured to control itself and the memory 51 to implement the steps in any of the above embodiments of the circuit board detection method. Processor 52 may also be referred to as a CPU (Central Processing Unit). Processor 52 may be an integrated circuit chip having signal processing capabilities. The Processor 52 may also be a general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. In addition, processor 52 may be commonly implemented by a plurality of integrated circuit chips.
Be different from prior art, the application provides a detection device, wait to detect the first image of the layer part of branch nation graph that corresponds of circuit board through treater automatic acquisition, carry out the layer part of branch judgement with the first image based on the collection, and when the skew appears in the layer part of branch nation graph of confirming at least one layer core board of waiting to detect the circuit board, carry out the early warning output, not only reduced personnel and detected intensity, avoid staff healthy impaired, can also improve detection efficiency, and reduce the risk and the waste that wrong examination or missed measure lead to, thereby improve production efficiency.
Accordingly, the present application provides a computer-readable storage medium.
Referring to fig. 6, fig. 6 is a schematic structural diagram of an embodiment of a computer-readable storage medium according to the present application.
As shown in fig. 6, the computer-readable storage medium 60 includes a computer program 601 stored on the computer-readable storage medium 60, and when executed by the processor, the computer program 601 implements the steps of any of the above embodiments or the steps correspondingly executed by the material level data generating device in the above embodiments.
In particular, the integrated unit, if implemented in the form of a software functional unit and sold or used as a separate product, may be stored in a computer readable storage medium 60. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed to by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a computer-readable storage medium 60 and includes several instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) or a processor (processor) to execute all or part of the steps of the method of the embodiments of the present application. And the aforementioned computer-readable storage medium 60 includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
In the several embodiments provided in the present application, it should be understood that the disclosed method and apparatus may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a module or a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some interfaces, and may be in an electrical, mechanical or other form.
Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed to by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) or a processor (processor) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (10)
1. A circuit board detection method is characterized by comprising the following steps:
obtaining a circuit board to be detected; at least one set position of each layer of core board of the circuit board to be detected is provided with a corresponding layer-deviation Cowboy graph;
performing first image acquisition on the layer deviation Cowbond graph of the circuit board to be detected;
and responding to the situation that the layer deviation Coco graph of at least one layer core board of the circuit board to be detected deviates based on the acquired first image, and performing early warning output.
2. The method according to claim 1, wherein the step of performing early warning output in response to determining that the layer Cedrupont pattern of at least one layer core board of the circuit board to be detected deviates based on the acquired first image specifically includes:
determining that the layer-by-layer Copons graphics of at least two layers of core boards of the circuit board to be detected are tangent based on the first image, and determining that the layer-by-layer Copons graphics of the circuit board to be detected are offset.
3. The circuit board detection method according to claim 1 or 2, wherein the set positions of the layer Cedrub graphics on each layer of the core board of the circuit board to be detected are the same,
the step of performing first image acquisition on the layer boundary graph of the circuit board to be detected comprises the following steps of:
and shooting the layer deviation Coppon graph corresponding to the set position from one side of the circuit board to be detected by utilizing shooting equipment to obtain the first image.
4. The method according to claim 3, wherein the step of taking a picture of the Cedrumbeat diagram corresponding to the set position from one side of the circuit board to be detected by using a shooting device to obtain the first image specifically comprises:
acquiring specific coordinates of the layer Centraalbo graph on the core board at one side of the circuit board to be detected;
and photographing the layer-side-Cowboy graph at the specific coordinate to acquire the first image.
5. The circuit board detection method according to claim 1, wherein the layer-level Clay patterns of the circuit boards in different set positions or different models have different gradient offset values;
the step of responding to the situation that the layer deviation Cowbond graph of at least one layer core board of the circuit board to be detected deviates based on the collected first image and outputting early warning comprises the following steps of:
determining that the layer of the Centra graphics of at least one layer of the core board of the circuit board to be detected have deviation by utilizing the precision requirement matched with the gradient deviation value of each layer of the Centra graphics.
6. The circuit board detection method according to claim 1, further comprising:
and sending the circuit board to be detected to the next procedure in response to determining that the layer deviation Coco graph of at least one layer core board of the circuit board to be detected does not deviate based on the acquired first image.
7. The circuit board detection method according to claim 1, wherein a corresponding plate number is arranged at a preset position of each layer of the core board of the circuit board to be detected; the circuit board detection method further comprises the following steps:
carrying out second image acquisition on the plate number corresponding to each layer of core plate of the circuit board to be detected;
and responding to the situation that the plate number of at least one layer of core plate of the circuit board to be detected is inconsistent with the plate numbers of the other layers of core plates based on the acquired second image, and performing early warning output.
8. The method for detecting a circuit board according to claim 7, wherein the step of performing second image acquisition on the plate number corresponding to each layer of core board of the circuit board to be detected specifically comprises:
and photographing the plate numbers corresponding to the preset positions from one side of the circuit board to be detected by using photographing equipment to obtain the second image.
9. A detection device, comprising:
a memory for storing program data, which when executed implements the steps in the wiring board inspection method of any one of claims 1 to 8;
a processor for executing the program instructions stored in the memory to realize the steps in the circuit board detection method according to any one of claims 1 to 8.
10. A computer-readable storage medium, wherein a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps in the circuit board detection method according to any one of claims 1 to 8 are realized.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111539228.4A CN114511492A (en) | 2021-12-15 | 2021-12-15 | Circuit board detection method, circuit board detection device and computer readable storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111539228.4A CN114511492A (en) | 2021-12-15 | 2021-12-15 | Circuit board detection method, circuit board detection device and computer readable storage medium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114511492A true CN114511492A (en) | 2022-05-17 |
Family
ID=81547892
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111539228.4A Pending CN114511492A (en) | 2021-12-15 | 2021-12-15 | Circuit board detection method, circuit board detection device and computer readable storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114511492A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115601322A (en) * | 2022-10-11 | 2023-01-13 | 中山芯承半导体有限公司（Cn） | Method for detecting interlayer offset of circuit board |
-
2021
- 2021-12-15 CN CN202111539228.4A patent/CN114511492A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115601322A (en) * | 2022-10-11 | 2023-01-13 | 中山芯承半导体有限公司（Cn） | Method for detecting interlayer offset of circuit board |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP3106948A1 (en) | Quality management device and method for controlling same | |
| US5564183A (en) | Producing system of printed circuit board and method therefor | |
| DE102015113068B4 (en) | Quality control device and control method for a quality control device | |
| CN110045688B (en) | Inspection management system, inspection management device, and inspection management method | |
| JP2015142032A (en) | Quality management apparatus and control method for quality management apparatus | |
| KR20130050236A (en) | System, device, and method for assisting visual check operation of inspection result | |
| JP2009245435A (en) | Process control system with ability to exchange data with production line machine controller | |
| JP6988499B2 (en) | Inspection management system, inspection management device, inspection management method | |
| JP2011138930A (en) | Method and apparatus for inspecting and managing electronic substrate, and visual inspection apparatus | |
| JP6922694B2 (en) | Management systems, management devices, management methods, and programs | |
| CN114511492A (en) | Circuit board detection method, circuit board detection device and computer readable storage medium | |
| JP2011180058A (en) | Solder printing inspection device and solder print system | |
| CN108966631A (en) | Producing line technical solution applied to surface mounting technology | |
| WO2013001594A1 (en) | Method for management of inspection of electronic substrate, apparatus for same, and apparatus for visual inspection of electronic substrate | |
| CN113012097B (en) | Image rechecking method, computer device and storage medium | |
| WO2016165828A1 (en) | Method for checking an electronic component | |
| JP2011128030A (en) | Defect inspection device and defect information management method | |
| JP2015132507A (en) | Control device of internal inspection device and control method of the internal inspection device | |
| JP2015148507A (en) | Quality control system | |
| CN206332009U (en) | No ink spot wafer appearance inspecting system | |
| JP2002031605A (en) | Defect-confirming apparatus and automatic visual inspection apparatus | |
| JP2015075412A (en) | Appearance inspection system | |
| KR102410920B1 (en) | Methode for collecting Printed circuit board and scanning device of printed circuit board therefor | |
| US20240061408A1 (en) | Quality improvement assistance device | |
| JP2006253567A (en) | Apparatus and method for analysis of aggregation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |