CN114497315A - LED chip structure and preparation method thereof - Google Patents
LED chip structure and preparation method thereof Download PDFInfo
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- CN114497315A CN114497315A CN202210139488.0A CN202210139488A CN114497315A CN 114497315 A CN114497315 A CN 114497315A CN 202210139488 A CN202210139488 A CN 202210139488A CN 114497315 A CN114497315 A CN 114497315A
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- 238000002360 preparation method Methods 0.000 title description 4
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 claims abstract description 10
- 239000010408 film Substances 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 5
- 238000009713 electroplating Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 238000007639 printing Methods 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 3
- 239000013039 cover film Substances 0.000 claims description 3
- 230000008020 evaporation Effects 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 238000007731 hot pressing Methods 0.000 claims description 3
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 3
- 239000012811 non-conductive material Substances 0.000 claims description 3
- 229910052594 sapphire Inorganic materials 0.000 claims description 3
- 239000010980 sapphire Substances 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 4
- 206010070834 Sensitisation Diseases 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 230000008313 sensitization Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007888 film coating Substances 0.000 description 1
- 238000009501 film coating Methods 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000009740 moulding (composite fabrication) Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
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- 230000001737 promoting effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
Abstract
The present disclosure provides an LED chip structure and a method for manufacturing the same, the LED chip structure including: the device comprises a substrate, an epitaxial layer, a PN electrode layer and a photosensitive developing layer, wherein the epitaxial layer is formed on the surface of the substrate; the PN electrode layers are formed on the surface of the epitaxial layer and are positioned at two ends of the surface of the epitaxial layer; the photosensitive developing layer covers the substrate and the rest surfaces of the epitaxial layer, and the surface of the photosensitive developing layer is higher than the surface of the epitaxial layer.
Description
Technical Field
The disclosure relates to the field of photoelectric devices, in particular to an LED chip structure and a preparation method thereof.
Background
A Light Emitting Diode (LED) is a junction-type electroluminescent semiconductor device capable of converting an electrical signal into an optical signal, and has been widely used in the field of solid-state lighting as a third-generation green light source, and in recent years, it has been increasingly used in the field of flat panel display, especially in the field of novel display such as small-pitch LED display and micro light emitting diode (Mini/micro LED) display. The small-spacing LED display and the MiniLED display generally adopt a flip LED chip to improve contrast and reliability, the MicroLED display generally interconnects LED chips into a display array through electrodes, and the electrode interconnection of the flip LED chip and the display array needs an electric insulation layer with reliable performance and thickened electrodes. At present, a PECVD deposited silicon dioxide film is mainly used as an electric insulating layer, but the electric insulating property is influenced due to the fact that the film is not compact and the film layer is thin, and short circuit between electrodes is caused. A Distributed Bragg Reflector (DBR) can also be prepared by electron beam evaporation, which serves as both a reflector and an electrical insulating layer, but the DBR is too thick (more than 2 um) and needs to be etched, which can damage the electrodes.
Disclosure of Invention
Technical problem to be solved
In view of the above, the present disclosure is directed to an LED chip structure and a method for manufacturing the same, which are intended to solve at least one of the above-mentioned technical problems.
(II) technical scheme
According to an aspect of the present disclosure, there is provided an LED chip structure including:
a substrate;
an epitaxial layer formed on a surface of the substrate;
the PN electrode layers are formed on the surface of the epitaxial layer and are positioned at two ends of the surface of the epitaxial layer; and
the photosensitive developing layer covers the rest surfaces of the substrate and the epitaxial layer, and the surface of the photosensitive developing layer is higher than the surface of the epitaxial layer; the residual surface of the substrate is a partial surface which is not covered by the epitaxial layer, and the residual surface of the epitaxial layer is a partial surface which is not covered by the PN electrode layer.
In some embodiments of the present disclosure, the epitaxial layer comprises:
a u-GaN buffer layer formed on a surface of the substrate;
the N-GaN epitaxial layer covers the surface of the u-GaN buffer layer;
the multi-quantum well MQW layer covers the surface of the N-GaN epitaxial layer, and one end of the PN electrode layer is formed on the MQW layer; and
the P-GaN layer is formed on the surface of the multi-quantum well MQW layer and extends from the surface edge of the multi-quantum well MQW layer, and the other end of the PN electrode layer is formed on the P-GaN layer;
the photosensitive developing layer covers the partial surface of the P-GaN layer, which is not covered by the PN electrode layer, the photosensitive developing layer covers the partial surface of the MQW layer, which is not covered by the PN electrode layer and the P-GaN layer, of the multiple quantum well, and the surface of the photosensitive developing layer is higher than the surface of the P-GaN layer.
In some embodiments of the present disclosure, the PN electrode layer includes:
a P electrode formed on a surface of the P-GaN layer and extending from a surface edge of the P-GaN layer; and
the N electrode is formed on the surface of the multi-quantum well MQW layer and extends from the surface edge of the multi-quantum well MQW layer;
the photosensitive developing layer covers the side walls of the P electrode and the N electrode and is higher than the surfaces of the P electrode and the N electrode.
In some embodiments of the present disclosure, further comprising:
and the thickened electrode layer covers the PN electrode layer and part of the surface of the photosensitive developing layer.
In some embodiments of the present disclosure, the material of the substrate is a sapphire material; the epitaxial layer is made of a non-conductive material; the PN electrode layer is made of CrAlAu.
In some embodiments of the present disclosure, the photosensitive developing layer is a photosensitive developing type cover film, and the film layer thickness of the photosensitive developing type cover film is 20-40 um.
In some embodiments of the present disclosure, the thickness of the thickened electrode layer is greater than 5 um.
According to another aspect of the present disclosure, there is also provided a method for manufacturing an LED chip structure, including:
step 1: taking a substrate in MOCVD equipment, and preparing an epitaxial layer on the substrate;
step 2: performing ICP mesa etching on the epitaxial layer;
and step 3: preparing a PN electrode layer on the epitaxial layer;
and 4, step 4: covering a photosensitive developing layer on the uncovered parts of the substrate, the epitaxial layer and the PN electrode layer;
and 5: and irradiating the photosensitive developing layer by using ultraviolet light on the back surface of the substrate, and developing the photosensitive developing layer covering the PN electrode layer.
In some embodiments of the present disclosure, the above preparation method further comprises:
step 6: and preparing a thickened electrode layer on the PN electrode layer and the photosensitive developing layer partially covered on the epitaxial layer.
In some embodiments of the present disclosure, the step 4 employs a vacuum hot-pressing method and/or a coating method to prepare the photosensitive developing layer; and step 6, preparing the thickened electrode layer by adopting a method of one or more of electroplating, printing, evaporation and sputtering.
(III) advantageous effects
Based on the technical scheme, compared with the prior art, the method has at least one or one part of the following beneficial effects:
1. according to the method, the photosensitive developing layer is prepared, the electric insulating layer can be prepared without photoetching and film coating processes, the process is simple, and the cost is low;
2. according to the method, the photosensitive developing layer is prepared, the thickness of the thickened electrode can be more than 5 micrometers through an electroplating or printing process, and the reliability of a chip flip-chip bonding process is improved;
3. according to the method, the photosensitive developing layer is prepared, so that light from the LED active area can be reflected to the light-emitting surface of the substrate, and the lighting effect is further improved.
Drawings
Fig. 1 is an overall design diagram of an LED chip structure provided in an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a structure in which a photosensitive developing layer on a PN electrode layer of an LED chip structure provided in an embodiment of the present disclosure is not yet developed;
fig. 3 is a schematic structural diagram of an LED chip structure after a thickened electrode layer is prepared according to an embodiment of the present disclosure.
[ description of reference ]
1: substrate
2: u-GaN buffer layer
3: N-GaN epitaxial layer
4: MQW layer of multiple quantum well
5: P-GaN layer
6: p electrode
7: n electrode
8: photosensitive developing layer
9: epitaxial layer
10: PN electrode layer
11: thickened electrode layer
Detailed Description
For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.
Certain embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the disclosure are shown. Indeed, various embodiments of the disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements.
As an aspect of the present disclosure, an LED chip structure is provided, and fig. 1 schematically illustrates an overall design diagram of the LED chip structure according to an embodiment of the present disclosure.
As shown in fig. 1, the LED chip structure includes a substrate 1, an epitaxial layer 9, a PN electrode layer 10, and a photosensitive developing layer 8.
In the embodiment of the present disclosure, the substrate 1 may be a sapphire substrate, the epitaxial layer 9 is formed on the surface of the substrate 1, and the material of the epitaxial layer 9 may be a non-conductive material; the PN electrode layer 10 is formed on the surface of the epitaxial layer 9 and located at two ends of the surface of the epitaxial layer 9, as shown in fig. 1, the PN electrode layer 10 is divided into two parts, one part is located at the left end of the surface of the epitaxial layer 9, the other part is located at the right end of the surface of the epitaxial layer 9, and the PN electrode layer 10 may be made of CrAlAu; the photosensitive developing layer 8 covers the remaining surfaces of the substrate 1 and the epitaxial layer 9, and the upper surface of the photosensitive developing layer 8 is higher than the upper surface of the epitaxial layer 9, in the embodiment of the present disclosure, the photosensitive developing layer 8 can be a photosensitive developing type covering film with a film layer thickness of 20-40um, and the photosensitive developing type covering film can be a polymer organic material and plays an insulating role.
In the embodiment of the present disclosure, the remaining surface of the substrate 1 is a partial surface not covered by the epitaxial layer 9, and the remaining surface of the epitaxial layer 9 is a partial surface not covered by the PN electrode layer 10.
In some embodiments of the present disclosure, epitaxial layer 9 comprises: a u-GaN buffer layer 2, an N-GaN epitaxial layer 3, a multi-quantum well MQW layer 4 and a P-GaN layer 5.
As shown in fig. 1, a u-GaN buffer layer 2 is formed on a surface of a substrate 1; the N-GaN epitaxial layer 3 covers the surface of the u-GaN buffer layer 2; the multi-quantum well MQW layer 4 covers the surface of the N-GaN epitaxial layer 3; the P-GaN layer 5 is formed on the surface of the multiple quantum well MQW layer 4 and extends from the surface edge of the multiple quantum well MQW layer 4, as shown in fig. 1, the P-GaN layer 5 being grown from the left end edge of the multiple quantum well MQW layer 4 in fig. 1; a part of the PN electrode layer 10 is formed on the P-GaN layer 5, and the other part of the PN electrode layer 10 is formed on the multiple quantum well MQW layer 4, as shown in fig. 1, a first part of the PN electrode layer 10 grows from the left end edge of the P-GaN layer 5, and a second part grows from the right end edge of the multiple quantum well MQW layer 4; the photosensitive developing layer 8 covers the partial surface of the P-GaN layer 5 which is not covered by the PN electrode layer 10, the photosensitive developing layer 8 covers the partial surface of the multi-quantum well MQW layer 4 which is not covered by the PN electrode layer 10 and the P-GaN layer 5, and the surface of the photosensitive developing layer 8 is higher than the surface of the P-GaN layer 5.
In some embodiments of the present disclosure, the PN electrode layer 10 includes: a P electrode 6 and an N electrode 7.
As shown in fig. 1, the P-electrode 6 is formed on the surface of the P-GaN layer 5 and extends from the left edge of the surface of the P-GaN layer 5; an N electrode 7 is formed on the surface of the multiple quantum well MQW layer 4 and extends from the right side edge of the surface of the multiple quantum well MQW layer 4, and a photosensitive developing layer 8 covers the side walls of the P electrode 6 and the N electrode 7 and is higher than the surfaces of the P electrode 6 and the N electrode 7.
In some embodiments of the present disclosure, further comprising: the electrode layer 11 is thickened. Thickened electrode layer 11 covers PN electrode layer 10 and partial sensitization development layer 8's surface, and the thickness of thickened electrode layer 11 is greater than 5um, and as shown in FIG. 3, thickened electrode layer 11 is the L type and covers on PN electrode layer 10 and partial sensitization development layer 8's surface.
As another aspect of the present disclosure, a method for manufacturing an LED chip structure is also provided, and fig. 2 to 3 schematically illustrate a method for manufacturing an LED chip structure according to an embodiment of the present disclosure.
As shown in fig. 2 to 3, the method for manufacturing the LED chip structure includes:
step 1: taking a substrate 1, and epitaxially growing a u-GaN buffer layer 2, an N-GaN epitaxial layer 3, a multi-quantum well MQW layer 4 and a P-GaN layer 5 on the substrate in sequence in MOCVD equipment to form an epitaxial layer 9;
and 2, step: carrying out ICP mesa etching on the epitaxial layer 9, and etching part of the epitaxial layer 9 onto the surface of the multi-quantum well MQW layer 4;
and step 3: preparing an N electrode 7 on the multi-quantum well MQW layer 4, and preparing a P electrode 6 on the P-GaN layer 5 to form a PN electrode layer 10;
and 4, step 4: preparing a photosensitive developing layer 8 on the substrate 1, the epitaxial layer 9 and the PN electrode layer 10 by a vacuum hot-pressing method and/or a coating method to form an LED chip substrate, wherein the prepared LED chip substrate is shown in FIG. 2;
and 5: irradiating the photosensitive developing layer 8 on the back surface of the substrate 1 by using ultraviolet light to irradiate the LED chip substrate, developing off the photosensitive developing layer 8 covered on the PN electrode layer 10, and exposing the photosensitive developing layer 8, wherein the structure of the developed LED chip is shown in figure 1;
step 6: preparing a thickened electrode layer 11 on the PN electrode layer 10 and the photosensitive developing layer 8 partially covering the epitaxial layer 9 by adopting a method of one or more of electroplating, printing, evaporation and sputtering, and forming an LED chip structure, as shown in FIG. 3;
according to the embodiment of the disclosure, the LED chip structure formed by the above method is cut, as in fig. 3, at AA/to form individual LED chips.
So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. It is to be noted that, in the attached drawings or in the description, the implementation modes not shown or described are all the modes known by the ordinary skilled person in the field of technology, and are not described in detail.
It should also be noted that directional terms, such as "upper", "lower", "front", "rear", "left", "right", and the like, used in the embodiments are only directions referring to the drawings, and are not intended to limit the scope of the present disclosure. Throughout the drawings, like elements are represented by like or similar reference numerals. Conventional structures or constructions will be omitted when they may obscure the understanding of the present disclosure.
And the shapes and sizes of the respective components in the drawings do not reflect actual sizes and proportions, but merely illustrate the contents of the embodiments of the present disclosure. Furthermore, in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim.
Unless otherwise indicated, the numerical parameters set forth in the specification and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by the present disclosure. In particular, all numbers expressing quantities of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term "about". Generally, the expression is meant to encompass variations of ± 10% in some embodiments, 5% in some embodiments, 1% in some embodiments, 0.5% in some embodiments by the specified amount.
Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.
The use of ordinal numbers such as "first," "second," "third," etc., in the specification and claims to modify a corresponding element does not by itself connote any ordinal number of the element, nor do they represent the order in which an element is sequenced from one element to another or the order of fabrication methods, but are used merely to allow a given element having a given name to be clearly separated from another element having a same name.
In addition, unless steps are specifically described or must occur in sequence, the order of the steps is not limited to that listed above and may be changed or rearranged as desired by the desired design. The embodiments described above may be mixed and matched with each other or with other embodiments based on design and reliability considerations, i.e., technical features in different embodiments may be freely combined to form further embodiments.
Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and furthermore they may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Also in the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various disclosed aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that is, the claimed disclosure requires more features than are expressly recited in each claim. Rather, as the following claims reflect, disclosed aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this disclosure.
The above embodiments are provided to further explain the purpose, technical solutions and advantages of the present disclosure in detail, and it should be understood that the above embodiments are merely exemplary of the present disclosure and are not intended to limit the present disclosure, and any modifications, equivalents, improvements, etc. made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.
Claims (10)
1. An LED chip structure comprising:
a substrate (1);
an epitaxial layer (9) formed on a surface of the substrate (1);
PN electrode layers (10) formed on the surface of the epitaxial layer (9) and positioned at two ends of the surface of the epitaxial layer (9); and
the photosensitive developing layer (8) covers the substrate (1) and the rest surfaces of the epitaxial layer (9), and the surface of the photosensitive developing layer (8) is higher than the surface of the epitaxial layer (9); wherein the rest surface of the substrate (1) is a partial surface which is not covered by the epitaxial layer (9), and the rest surface of the epitaxial layer (9) is a partial surface which is not covered by the PN electrode layer (10).
2. The LED chip structure according to claim 1, wherein the epitaxial layer (9) comprises:
a u-GaN buffer layer (2) formed on a surface of the substrate (1);
an N-GaN epitaxial layer (3) covering the surface of the u-GaN buffer layer (2);
a multi-quantum well MQW layer (4) covering the surface of the N-GaN epitaxial layer (3), wherein one end of the PN electrode layer (10) is formed on the MQW layer (4); and
the P-GaN layer (5) is formed on the surface of the multi-quantum well MQW layer (4) and extends from the surface edge of the multi-quantum well MQW layer (4), and the other end of the PN electrode layer (10) is formed on the P-GaN layer (5);
the photosensitive developing layer (8) covers the partial surface of the P-GaN layer (5) which is not covered by the PN electrode layer (10), the photosensitive developing layer (8) covers the partial surface of the multi-quantum well MQW layer (4) which is not covered by the PN electrode layer (10) and the P-GaN layer (5), and the surface of the photosensitive developing layer (8) is higher than the surface of the P-GaN layer (5).
3. The LED chip structure according to claim 2, wherein said PN electrode layer (10) comprises:
a P electrode (6) formed on the surface of the P-GaN layer (5) and extending from the surface edge of the P-GaN layer (5); and
an N electrode (7) formed on the surface of the multiple quantum well MQW layer (4) and extending from the surface edge of the multiple quantum well MQW layer (4);
wherein the photosensitive developing layer (8) covers the side walls of the P electrode (6) and the N electrode (7) and is higher than the surfaces of the P electrode (6) and the N electrode (7).
4. The LED chip structure according to any one of claims 1 to 3, further comprising:
and the thickened electrode layer (11) covers the PN electrode layer (10) and part of the surface of the photosensitive developing layer (8).
5. The LED chip structure according to any of claims 1 to 3, wherein the material of the substrate (1) is a sapphire material; the epitaxial layer (9) is made of a non-conductive material; the PN electrode layer (10) is made of CrAlAu.
6. The LED chip structure according to any of claims 1 to 3, wherein the photosensitive developing layer (8) is a photosensitive developing type cover film having a film layer thickness of 20-40 um.
7. The LED chip structure according to claim 4, wherein the thickness of the thickened electrode layer (11) is larger than 5 um.
8. A method of making the LED chip structure of any one of claims 1 to 7, comprising:
step 1: taking a substrate (1) in MOCVD equipment, and preparing an epitaxial layer (9) on the substrate (1);
step 2: carrying out ICP mesa etching on the epitaxial layer (9);
and step 3: preparing a PN electrode layer (10) on the epitaxial layer (9);
and 4, step 4: covering a photosensitive developing layer (8) on uncovered parts of the substrate (1), the epitaxial layer (9) and the PN electrode layer (10);
and 5: the back of the substrate (1) is irradiated by ultraviolet light, the LED chip substrate irradiates the photosensitive developing layer (8), and the photosensitive developing layer (8) covering the PN electrode layer (10) is developed.
9. The method of manufacturing according to claim 8, further comprising:
step 6: and preparing a thickened electrode layer (11) on the PN electrode layer (10) and the photosensitive developing layer (8) partially covered on the epitaxial layer (9).
10. The production method according to claim 9, wherein the step 4 produces the photosensitive developing layer (8) by a vacuum hot-pressing method and/or a coating method; the step 6 is to prepare the thickened electrode layer (11) by adopting a method of one or more of electroplating, printing, evaporation and sputtering.
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2022
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| US20030193054A1 (en) * | 2002-04-15 | 2003-10-16 | Semiconductor Energy Laboratory Co., Ltd. | Display device and method of fabricating the same |
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