CN114491395A - Current domain system design applied to analog front-end signal processing based on FFT algorithm - Google Patents
Current domain system design applied to analog front-end signal processing based on FFT algorithm Download PDFInfo
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Abstract
Due to the orthogonal frequency division characteristic of the FFT algorithm, the algorithm has natural advantages in the analog processing of the radio frequency front-end receiver. Especially, a perfect FFT operation system is needed in the ofdm demodulation process used in the current 4G and 5G communications. The invention provides a system design applied to analog front end signal processing based on an FFT algorithm, which is used for analog front end processing when a radio frequency front end receiver receives an extremely high frequency modulation multi-frequency signal. It is characterized by comprising: and inputting the ultrahigh frequency sampling holding circuit at the front end for realizing subsequent discrete Fourier transform calculation. And the input transconductance amplifier is used for converting the input discrete voltage signal into a current signal. And the FFT calculation core module is used for converting the time domain current signal into a current value representing frequency domain information by performing multiply-add operation. And the output trans-impedance amplifier is used for converting the current signal after the FFT operation into a voltage signal.
Description
Technical Field
The invention provides a system design based on an FFT algorithm and applied to analog front-end signal processing, in particular to the technical field of analog integrated circuit design, and specifically relates to a discrete multiply-add operation circuit system with a high-speed sampling switch. The system can process the demodulation process of high-speed multi-frequency signals. The modulated multi-frequency signal is divided into a low-frequency single-frequency signal.
Background
With the rapid development of Internet of Things (IoT), the physical layer requires a high-speed wireless solution. Therefore, according to shannon's theorem, the development of wireless communication technology is accompanied by a wider bandwidth. In conventional software radio systems, Radio Frequency (RF) signals are typically processed in the digital domain by analog-to-digital conversion. This places higher speed and dynamic range requirements on the front-end analog-to-digital converter (ADC). The time-domain ADC may solve the speed limitation, but each sub-ADC requires the same Dynamic Range (DR) requirement to satisfy the overall requirement of signal to noise and distortion ratio (SNDR). On the other hand, a higher bandwidth means a higher sampling frequency, which means more power consumption.
In a Digital Signal Processor (DSP), FFT is a core component of an Orthogonal Frequency Division Multiplexing (OFDM) demodulation process, and is an important technology used in 4G Long Term Evolution (LTE) and 5G New Radio (NR). The high frequency modulated signal is demodulated by a Fast Fourier Transform (FFT) algorithm. More and more broadband systems place higher demands on digital demodulation. For example, the increased bandwidth and channel make the power consumption and area of the digital domain unacceptable. Therefore, current demodulation is more likely to process the process in the analog domain to relieve the performance requirements of the subsequent ADC.
In the existing design of the analog front end FFT algorithm system, one is to complete all addition and multiplication operations in the form of a pure passive switched capacitor circuit. The addition realizes the voltage addition process through a standard charge redistribution process, and the multiplication needs an uncharged empty capacitor and two capacitors which store charges representing the operation to realize coefficient multiplication through charge redistribution. Such a purely passive form has a high accuracy but the required capacitance area is large and the speed and accuracy trade-off limits the speed of such a system due to the need to balance kT/C noise and the effects of charge injection and clock feed-through. Another operation using an operational amplifier to realize multiplication and addition is a great limitation on precision, and has no great advantage in terms of power consumption.
At present, no analog front end FFT system capable of realizing high precision at high speed exists at home and abroad, therefore, the invention provides an analog front end design for realizing FFT algorithm in a current domain, which can avoid extra hardware expenditure caused by all addition operations, and can control the calculation precision of multiplication through a current mirror in the current domain so as to achieve high precision.
Disclosure of Invention
The invention provides a current domain system design applied to analog front end signal processing based on an FFT algorithm, which can realize a 64-channel current domain FFT algorithm system and realize higher speed and medium precision.
In order to achieve the above purpose, the present invention adopts a fully differential circuit system, a sampling module of a bootstrap boost type capacitor lower stage board is used as input, then a discrete voltage signal is converted into a current signal through a current auxiliary local negative feedback transconductance amplifier Gm, then a time domain signal is converted into a signal with specific frequency information through an FFT computation module to complete all operations of FFT, and finally a transimpedance amplifier a with source negative feedback is used to complete all operations of FFTRTo implement the function of converting the current signal back to a voltage signal.
The specific FFT algorithm selects a radix-4 time extraction butterfly algorithm, the series of a computing system can be determined according to different points, and the series of the system and the complexity of basic multiply-add operation are determined through the selection of the algorithm. The multiplication accuracy in the system circuit is selected according to this algorithm to confirm the actual circuit accuracy. FIG. 1 is a basic butterfly diagram of the radix-4 time decimation algorithm. Compared with the basic matrix complexity of the radix-2 algorithm used in the prior art, the radix-4 time extraction butterfly algorithm has a certain degree of increase, but under the same point number, the radix-4 butterfly algorithm takes the power of 4 as the base, so that the operation series can be reduced by half, the transmission of noise in an actual circuit can be further reduced, and the linearity and the precision are improved.
The FFT calculation core module adopts a current domain calculation mode, and the addition in calculation can be prevented from using an additional hardware module by adopting the current domain calculation mode. The addition of the current is realized in a hardware wire connection mode. Meanwhile, the current coefficient multiplication is calculated through the proportional amplification function of the current mirror, and the calculation speed of the whole system is accelerated. The cascode current mirror ensures the calculation accuracy of the current proportion calculation. The cascode tube adopts a self-cascade structure to realize stable drain-source voltage under the low power supply voltage environment.
The input and output conversion stages of the FFT calculation all adopt a local negative feedback mode to realize a high-speed transconductance amplifier and a trans-impedance amplifier. The high-speed transconductance amplifier adopts a current auxiliary branch circuit to open and shunt at each peak value of a differential signal, and high linearity design under the condition of smaller gain is realized. The high-speed transimpedance amplifier reduces the equivalent noise influence of the tail current source in a source negative feedback mode so as to achieve the high-gain high-precision transimpedance amplifier.
The invention has the following advantages: compared with other circuit systems of the analog front-end FFT algorithm, the radix-4 time extraction butterfly algorithm is selected, and the number of stages is reduced by half compared with the traditional radix-2 time extraction butterfly algorithm under the same number of points, so that the method has the advantage at the algorithm level, namely for an actual circuit, more stages mean larger noise transmission, because the reduction of the stages can reduce noise from the system level, and meanwhile, the improvement of the complexity of a basic matrix caused by the radix-4 time extraction is only the improvement of the size of the matrix and does not involve the increase of the angle of a unit circle, so that great benefit can be brought in the actual circuit.
Meanwhile, the system adopts a current domain implementation mode, and compared with the traditional voltage domain implementation mode, the system can completely avoid the additional hardware overhead of all addition operations, and the addition of the currents can be completed only by wire connection. Another advantage of the current domain operation is that the speed is very fast, and here the-3 dB bandwidth can be improved to a very large extent by using the cascode current mirror as the current coefficient multiplier to adjust the size of the tail pipe to control the size of the parasitic capacitance, thereby not limiting the speed in the FFT analog calculation. The transconductance amplifier and the trans-impedance amplifier with the local negative feedback can obtain higher speed on the premise of ensuring that the precision of the input-output conversion stage is greater than that of the whole system, and meanwhile, the auxiliary current feedback branch and the source negative feedback branch cannot generate large power consumption, so that the power consumption of the whole system is further ensured.
Drawings
FIG. 1 is a basic block diagram of a radix-4 time decimation FFT butterfly algorithm.
Fig. 2 is an overall frame diagram of the current domain system design applied to analog front-end signal processing based on the FFT algorithm provided in the present invention.
Fig. 3 is a circuit diagram of an input conversion stage of a current domain system design applied to analog front-end signal processing based on an FFT algorithm provided in the present invention.
Fig. 4 is a circuit diagram of an output conversion stage of the current domain system design applied to analog front-end signal processing based on the FFT algorithm provided in the present invention.
Detailed Description
The following detailed description of embodiments of the invention is provided in connection with the accompanying drawings.
Firstly, the system is a discrete time processing system, so that after an input signal enters the system, a sampling and holding module is required to obtain a discrete voltage input signal. In order to maintain a constant switch on-resistance Ron, so that the accuracy of the sampling is much higher than the accuracy of the system and does not affect the accuracy of the system. The specific sampling and holding module is a sampling switch with bootstrap, then sampling is carried out on input signals successively according to clock control by adopting a capacitance bottom plate sampling mode for preventing the influence of charge injection and the like, and the clock adopts 64-channel non-overlapping clocks to control all switches. The selection of the capacitance value of the sampling capacitor Cs is mainly selected according to the influence of kT/C noise.
An input signal enters an input conversion stage after being sampled, a specific circuit of the input conversion stage is shown in figure 3 and is a fully differential transconductance stage circuit, two auxiliary branches on the left side and the right side are respectively opened at the peak value of a differential signal, current on a part of trunk circuits is extracted to keep good linearity, and a cascode current mirror is used as an output stage after the auxiliary branches are converted into a current signal, so that output impedance can be improved to achieve high current precision.
After passing through the input conversion stage, the input signals enter a calculation module of an FFT algorithm, the sequence of the input signals is arranged according to the input sequence in the radix-4 algorithm, and then corresponding operation of coefficient multiplication and current addition is carried out according to the multiplication coefficient determined by the twiddle factor of each stage. The current and thus the speed are controlled by adjusting the width-to-length ratio of the pair transistors which control the current proportionality coefficient.
Finally, the calculated current signal is converted into a voltage signal through an output conversion stage, wherein in order to reduce the contribution of a current source tube to equivalent noise, the contribution of noise is reduced in a source negative feedback mode, and the gain of the stage is adjusted through a resistor R so that the swing amplitude of the output signal is in a proper interval.
Claims (4)
1. The invention provides a current domain system design applied to analog front end signal processing based on FFT algorithm, which is used for analog front end processing when a radio frequency front end receiver receives an extremely high frequency modulation multi-frequency signal, and is characterized by comprising the following steps: the system comprises an input front-end ultrahigh frequency sampling and holding circuit, an input transconductance amplifier, an FFT (fast Fourier transform) calculation core module and an output transimpedance amplifier, wherein the input front-end ultrahigh frequency sampling and holding circuit is used for realizing subsequent discrete Fourier transform calculation, the input transconductance amplifier is used for converting an input discrete voltage signal into a current signal, the FFT calculation core module is used for performing multiply-add operation on a time domain current signal to convert the time domain current signal into a current value representing frequency domain information, and the output transimpedance amplifier is used for converting the current signal after FFT operation into a voltage signal.
2. The design of the current domain system applied to analog front end signal processing based on the FFT algorithm as claimed in claim 1, wherein the selected algorithm is the radix-4 butterfly algorithm, the number of stages of the computing system can be determined according to different points, the number of stages of the system and the complexity of the basic multiply-add operation are determined by the selection of the algorithm, and the multiplication precision in the system circuit is selected according to the algorithm to confirm the actual circuit precision.
3. The design of the current domain system applied to analog front-end signal processing based on the FFT algorithm as recited in claim 2, wherein the FFT computation core module adopts a current domain computation method, the current domain computation method can avoid the use of an additional hardware module for addition in computation, the current addition is realized in a hardware wire connection manner, and the current coefficient multiplication is computed through the proportional amplification function of the current mirror, so as to accelerate the computation speed of the whole system, the cascode current mirror ensures the computation accuracy of the current proportion computation, and the cascode tube therein adopts a self-cascade structure to realize stable drain-source voltage in a low supply voltage environment.
4. The current domain system design applied to analog front-end signal processing based on the FFT algorithm as recited in claim 3, wherein the input/output conversion stages of the FFT computation all use a local negative feedback manner to implement a high-speed transconductance amplifier and a transimpedance amplifier, wherein the high-speed transconductance amplifier uses a current auxiliary branch to turn on and shunt at each peak of the differential signal to implement a high linearity design with a small gain, and the high-speed transimpedance amplifier uses a source negative feedback manner to reduce the equivalent noise effect of the tail current source to implement a high-gain high-precision transimpedance amplifier.
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Citations (6)
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|---|---|---|---|---|
| US20050275466A1 (en) * | 2004-06-10 | 2005-12-15 | Agency For Science, Technology And Research | Multi-gigabit/s transimpedance amplifier for optical networks |
| US20140079098A1 (en) * | 2012-04-09 | 2014-03-20 | Regents Of The University Of Minnesota | Multi-stage charge re-use analog circuits |
| CN111816232A (en) * | 2020-07-30 | 2020-10-23 | 中科院微电子研究所南京智能技术研究院 | Memory computing array device based on 4-tube storage structure |
| CN112151092A (en) * | 2020-11-26 | 2020-12-29 | 中科院微电子研究所南京智能技术研究院 | Storage unit, storage array and in-memory computing device based on 4-pipe storage |
| WO2021056980A1 (en) * | 2019-09-27 | 2021-04-01 | 东南大学 | Convolutional neural network oriented two-phase coefficient adjustable analog multiplication calculation circuit |
| CN113472295A (en) * | 2021-06-08 | 2021-10-01 | 翱捷科技股份有限公司 | Power mixer capable of suppressing third harmonic of local oscillator |
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2022
- 2022-01-04 CN CN202210014089.1A patent/CN114491395A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050275466A1 (en) * | 2004-06-10 | 2005-12-15 | Agency For Science, Technology And Research | Multi-gigabit/s transimpedance amplifier for optical networks |
| US20140079098A1 (en) * | 2012-04-09 | 2014-03-20 | Regents Of The University Of Minnesota | Multi-stage charge re-use analog circuits |
| WO2021056980A1 (en) * | 2019-09-27 | 2021-04-01 | 东南大学 | Convolutional neural network oriented two-phase coefficient adjustable analog multiplication calculation circuit |
| CN111816232A (en) * | 2020-07-30 | 2020-10-23 | 中科院微电子研究所南京智能技术研究院 | Memory computing array device based on 4-tube storage structure |
| CN112151092A (en) * | 2020-11-26 | 2020-12-29 | 中科院微电子研究所南京智能技术研究院 | Storage unit, storage array and in-memory computing device based on 4-pipe storage |
| CN113472295A (en) * | 2021-06-08 | 2021-10-01 | 翱捷科技股份有限公司 | Power mixer capable of suppressing third harmonic of local oscillator |
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