CN104104387A - Device and method for expanding dynamic range of analog-to-digital converter (ADC) - Google Patents
Device and method for expanding dynamic range of analog-to-digital converter (ADC) Download PDFInfo
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- CN104104387A CN104104387A CN201410369699.9A CN201410369699A CN104104387A CN 104104387 A CN104104387 A CN 104104387A CN 201410369699 A CN201410369699 A CN 201410369699A CN 104104387 A CN104104387 A CN 104104387A
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Abstract
The invention discloses a device and a method for expanding a dynamic range of an analog-to-digital converter (ADC). The device comprises an AGC (automatic gain control) power splitting module, an ADC1, a digital phase-shift gain module, an analog time delay 1, a high-dynamic digital-to-analog conversion (DAC) module, an adder, a filter amplifier module, an analog time delay 2, an ADC2, a digital delay, a coupler, a parameter research/estimation module and a control interface. By means of nonlinear devices, nonlinear component of final output signals is reduced while risk in signal processing is lowered. Wide dynamic range is achieved through the low-performance ADCs and the low-cost DAC. Feedback forecasting circuits are omitted, thus the robustness is improved while signal bandwidth limitation is eliminated.
Description
Technical field
The present invention relates to a kind ofly the present invention relates to analog signal in digital communicating field to conversion equipment and the method for digital signal, particularly relate to a kind of apparatus and method that improve analog to digital converter dynamic range.
Background technology
In digital communication, analog to digital converter is responsible for analog domain to the mapping of numeric field, and the dynamic range of analog to digital converter has directly limited the obtainable highest signal to noise ratio of numeric field.Therefore the dynamic range that, how to improve analog to digital converter has become key point in digital communication.
The existing method that is intended to improve ADC dynamic range mainly contains three kinds:
Preposition logarithmic amplifier: before ADC by analog signal through a logarithmic amplifier, high level signal is compressed to the maximum range of ADC with the raising of the interior ADC of realization dynamic range.First, in the residual output of the sampling to ADC of non-linear meeting due to logarithmic amplifier, therefore the linearity of logarithmic amplifier is had to very high requirement.Secondly, near zero oppositely and be tending towards negative infinite characteristic needs processing especially, this has increased realizes difficulty to logarithmic amplifier.
Multi-stage quantization: the level signal after sampling hold circuit is carried out to successive approximation to quantification, obtain high-precision quantification output, typically comprise two kinds of structures of Two-Step and Pipelined.This method is widely used in ADC product instantly, but this structure for be quantized result how to obtain accurately sampling inhibit signal output level, words sentence is talked about, and the echo signal that this structure is processed is fixing level signal, rather than the signal changing.Be limited by the impact of technique and material, this method is subject to that the impact of integral nonlinearity, DNL and quantizing noise is serious, and price is high, and can only implement at the product design initial stage, and this structure of chip on sale is not modifiable.
Signal estimation: prediction module is predicted next analog signal constantly according to the sampled signal of ADC, DAC by prediction signal be converted to analog domain and and analog signal subtract each other and obtain error signal, error signal through amplification process by ADC, sampled after and prediction module output addition obtain final result.This method is by adopting accurate prediction algorithm and extra a slice DAC can effectively improve the dynamic range of ADC, but its shortcoming is the coherence time of signal and must not be shorter than the time delay of predictive loop, otherwise the power of error signal can obviously not reduced, and this means the Bandwidth-Constrained of analog signal.
Summary of the invention
The object of the invention is to solve dynamic range in the analog to digital converter sampling of broadband signal and be limited by non-linear and problem quantizing noise, a kind of apparatus and method that improve analog to digital converter dynamic range are provided.
The object of the invention is to be achieved through the following technical solutions: a kind of device that improves analog to digital converter dynamic range, it is characterized in that: comprise AGC merit sub-module, analog to digital converter ADC1, digital phase shift gain module, simulation delayer 1, high dynamically D/A converter module, adder, filter and amplification module, simulation delayer 2, analog to digital converter ADC2, digital time delayer, joint control, parameter search/estimation module and control interface, the two-way output of AGC merit sub-module is connected with simulation delayer 1 with analog to digital converter ADC1 respectively, the output of analog to digital converter ADC1 is connected with digital phase shift gain module, the output of digital phase shift gain module is connected with digital time delayer with digital to analog converter DAC1 respectively, the output of simulation delayer 1 and high dynamic number weighted-voltage D/A converter is connected with two inputs of adder respectively, the output of adder is connected with filter and amplification module, the output of filter and amplification module is connected with simulation delayer 2, the output of simulation delayer 2 is connected with analog to digital converter ADC2, the output of digital time delayer and analog to digital converter ADC2 is connected with two inputs of joint control respectively, the output of digital time delayer and analog to digital converter ADC2 is also connected with parameter search/estimation module, parameter search/estimation module is exported five tunnel control signals, wherein You San road is connected to control interface, all the other two-way are connected with digital phase shift gain module with digital time delayer respectively, the output of control interface respectively with simulation delayer 2, filter and amplification module is connected with simulation delayer 1.
Described control interface comprises control interface 1, control interface 2 and control interface 3, the input of control interface 1, control reception 2 and control interface 3 is connected with the output of parameter search/estimation module San road respectively, and the output of control interface 1, control interface 2 and control interface 3 is connected with simulation delayer 2, filter and amplification module and simulation delayer 1 respectively.
A method that improves analog to digital converter dynamic range, is characterized in that: comprise signal treatment step and parameter search/estimating step, wherein, described signal treatment step comprises following sub-step:
S101:AGC merit sub-module receives analog signal a (t), analog signal a (t) is amplified, and be divided into two-way analog signal a
1and a (t)
2(t);
S102: by analog signal a
1(t) send into analog to digital converter ADC1, by sampling and the quantification of analog to digital converter ADC1, obtain digital signal b (n);
S103: digital signal b (n) is sent into digital phase shift gain module, gain and the phase place of digital phase shift gain module correcting digital signal b (n), the digital signal c after being proofreaied and correct (n);
S104: digital signal c (n) is sent into high dynamically D/A converter module, and high dynamically D/A converter module is transformed into analog domain by the digital signal c (n) after proofreading and correct and obtains analog signal d (t);
S105: by analog signal a
2(t) send into simulation delayer 1, analog signal a
2(t) through simulation delayer 1, postpone to obtain later analog signal e (t);
S106: analog signal d (t) and analog signal e (t) are sent into adder, and adder is subtracted each other analog signal e (t) and simulation d (t), obtains analog signal f (t);
S107: analog signal f (t) is sent into filter and amplification module, and filter and amplification module is carried out filtering to analog signal f (t), amplifies through amplifier, obtains analog signal g (t);
S108: analog signal g (t) is sent in simulation delayer 2 and carries out delay process, obtain analog signal h (t);
S109: analog signal h (t) is sent into analog to digital converter ADC2, and analog to digital converter ADC2 samples and quantizes analog signal h (t), obtains digital signal i (n);
S110: digital signal c (n) is sent into digital time delayer, obtain digital signal j (n) through delay process;
S111: digital signal i (n) and digital signal j (n) are sent into joint control, generate the digital signal k (n) of final output;
Described parameter search/estimating step, comprises following sub-step:
S201: the digital signal i in signal treatment step (n) and digital signal j (n) are sent into parameter search/estimation module, obtain simulating the adjustment amount t of delayer 1
1, the gain G in filter amplifier module, simulation delayer 2 adjustment amount t
2, the complex gain S of digital phase shift gain module and the adjustment amount t of digital time delayer
3;
S202: by the adjustment amount t of simulation delayer 1
1, the gain G in filter amplifier module, simulation delayer 2 adjustment amount t
2by control interface 3, control interface 2 and control interface 1, output to simulation delayer 1 respectively and adjust amount of delay, the power of filter amplifier module adjustment g (t) of e (t) and simulate the fraction time sampling cycle amount of delay that delayer 2 is adjusted h (t), by the adjustment amount t of the complex gain S of digital phase shift gain module and digital time delayer
3output to respectively digital phase shift gain module and adjust the integer sampling period time delay of power and phase place and the digital time delayer adjustment j (n) of c (n).
The invention has the beneficial effects as follows: 1, do not adopt nonlinear device, as logarithmic amplifier, thereby reduced the nonlinear component in final output signal and reduced the risk of small signal process;
2, cost, utilize the ADC (analog to digital converter ADC1 and analog to digital converter ADC2) of lower-performance and cheaply DAC (high dynamic number weighted-voltage D/A converter) realize high dynamic range, can directly adopt chip on sale to realize.
3, owing to not there is not feedback forecasting loop, so robustness is better, and no signal limit bandwidth.
Accompanying drawing explanation
Fig. 1 is structured flowchart of the present invention;
Fig. 2 is AGC merit sub-module structured flowchart;
Fig. 3 is digital phase shift gain module structured flowchart;
Fig. 4 is high dynamically D/A converter module structured flowchart;
Fig. 5 is filter and amplification modular structure block diagram;
Fig. 6 is joint control structured flowchart;
Fig. 7 is parameter search/estimation module structured flowchart.
Embodiment
Below in conjunction with accompanying drawing, technical scheme of the present invention is described in further detail: as shown in Figure 1, a kind of device that improves analog to digital converter dynamic range, it is characterized in that: comprise AGC merit sub-module, analog to digital converter ADC1, digital phase shift gain module, simulation delayer 1, high dynamically D/A converter module, adder, filter and amplification module, simulation delayer 2, analog to digital converter ADC2, digital time delayer, joint control, parameter search/estimation module and control interface, the two-way output of AGC merit sub-module is connected with simulation delayer 1 with analog to digital converter ADC1 respectively, the output of analog to digital converter ADC1 is connected with digital phase shift gain module, the output of digital phase shift gain module is connected with digital time delayer with digital to analog converter DAC1 respectively, the output of simulation delayer 1 and high dynamic number weighted-voltage D/A converter is connected with two inputs of adder respectively, the output of adder is connected with filter and amplification module, the output of filter and amplification module is connected with simulation delayer 2, the output of simulation delayer 2 is connected with analog to digital converter ADC2, the output of digital time delayer and analog to digital converter ADC2 is connected with two inputs of joint control respectively, the output of digital time delayer and analog to digital converter ADC2 is also connected with parameter search/estimation module, parameter search/estimation module is exported five tunnel control signals, wherein You San road is connected to control interface, all the other two-way are connected with digital phase shift gain module with digital time delayer respectively, the output of control interface respectively with simulation delayer 2, filter and amplification module is connected with simulation delayer 1.
Described control interface comprises control interface 1, control interface 2 and control interface 3, the input of control interface 1, control reception 2 and control interface 3 is connected with the output of parameter search/estimation module San road respectively, and the output of control interface 1, control interface 2 and control interface 3 is connected with simulation delayer 2, filter and amplification module and simulation delayer 1 respectively.
A method that improves analog to digital converter dynamic range, is characterized in that: comprise signal treatment step and parameter search/estimating step, wherein, described signal treatment step comprises following sub-step:
S101:AGC merit sub-module receives analog signal a (t), analog signal a (t) is amplified, and be divided into two-way analog signal a
1and a (t)
2(t);
S102: by analog signal a
1(t) send into analog to digital converter ADC1, by sampling and the quantification of analog to digital converter ADC1, obtain digital signal b (n);
S103: digital signal b (n) is sent into digital phase shift gain module, gain and the phase place of digital phase shift gain module correcting digital signal b (n), the digital signal c after being proofreaied and correct (n);
S104: digital signal c (n) is sent into high dynamically D/A converter module, and high dynamically D/A converter module is transformed into analog domain by the digital signal c (n) after proofreading and correct and obtains analog signal d (t);
S105: by analog signal a
2(t) send into simulation delayer 1, analog signal a
2(t) through simulation delayer 1, postpone to obtain later analog signal e (t);
S106: analog signal d (t) and analog signal e (t) are sent into adder, and adder is subtracted each other analog signal e (t) and simulation d (t), obtains analog signal f (t);
S107: analog signal f (t) is sent into filter and amplification module, and filter and amplification module is carried out filtering to analog signal f (t), amplifies through amplifier, obtains analog signal g (t);
S108: analog signal g (t) is sent in simulation delayer 2 and carries out delay process, obtain analog signal h (t);
S109: analog signal h (t) is sent into analog to digital converter ADC2, and analog to digital converter ADC2 samples and quantizes analog signal h (t), obtains digital signal i (n);
S110: digital signal c (n) is sent into digital time delayer, obtain digital signal j (n) through delay process;
S111: digital signal i (n) and digital signal j (n) are sent into joint control, generate the digital signal k (n) of final output;
Described parameter search/estimating step, comprises following sub-step:
S201: the digital signal i in signal treatment step (n) and digital signal j (n) are sent into parameter search/estimation module, obtain simulating the adjustment amount t of delayer 1
1, the gain G in filter amplifier module, simulation delayer 2 adjustment amount t
2, the complex gain S of digital phase shift gain module and the adjustment amount t of digital time delayer
3;
S202: by the adjustment amount t of simulation delayer 1
1, the gain G in filter amplifier module, simulation delayer 2 adjustment amount t
2by control interface 3, control interface 2 and control interface 1, output to simulation delayer 1 respectively and adjust amount of delay, the power of filter amplifier module adjustment g (t) of e (t) and simulate the fraction time sampling cycle amount of delay that delayer 2 is adjusted h (t), by the adjustment amount t of the complex gain S of digital phase shift gain module and digital time delayer
3output to respectively digital phase shift gain module and adjust the integer sampling period time delay of power and phase place and the digital time delayer adjustment j (n) of c (n).
As shown in Figure 2, AGC merit sub-module consists of AGC and power distributing circuit.Target simulation signal a
1(t) enter AGC, AGC output connects power distributing circuit, and two outputs of power distributing circuit are respectively a
1and a (t)
2(t), wherein give a
1(t) analog to digital converter ADC1, a
2(t) send into simulation delayer 1.The error that AGC in AGC merit sub-module introduces must be guaranteed, if the error that AGC introduces reaches or surpassed the non-linear and quantization noise level of analog to digital converter ADC1, so further improve the dynamic range of analog to digital converter ADC1 just without any meaning.
Analog signal a
1(t) through analog to digital converter ADC1 sampling with after quantizing, obtain digital signal b (n), in fact in digital signal b (n) except a
1(t), beyond linear segment, also has non-linear and quantizing noise.
As shown in Figure 3, digital phase shift gain module selects circuit Re to form by multiplier 1, multiplier 2, a low pass filter LPF, a duplicate vibration generator, a conjugation change-over circuit Conj and a real part.Digital signal b (n) is connected multiplier 1 with resume classes positive coefficient S and multiple local oscillation signal and carries out frequency-conversion processing, the output of multiplier 1 connects low pass filter LPF, multiple local oscillation signal connects conjugation change-over circuit Conj simultaneously, the output of low pass filter LPF and conjugation change-over circuit Conj is connected multiplier 2 simultaneously and again carries out frequency-conversion processing, the output of multiplier 2 connects real part and selects circuit Re, and real part is selected circuit output signal c (n).Gain and the phase place of digital phase shift gain module correcting digital signal b (n), make in analog signal d (t) and analog signal e (t) about the amplitude same phase of linear component differ p.These gain and phase shift correction amount is caused jointly by analog to digital converter ADC1, high dynamically D/A converter module, AGC merit sub-module and simulation delayer 1, and normally fix in reality.Correcting digital signal is later c (n).
As shown in Figure 4, high dynamically D/A converter module comprises nonlinear model, delay cell, digital to analog converter DAC1, digital to analog converter DAC2, attenuator and analog adder.Digital signal c (n) sends into respectively nonlinear model and delay cell, the algorithmic delay amount of the retardation of delay cell and nonlinear model is identical, the output linking number weighted-voltage D/A converter DAC1 of delay cell, the output linking number weighted-voltage D/A converter DAC2 of nonlinear model, the output of digital to analog converter DAC2 connects attenuator, the output of digital to analog converter DAC1 and attenuator is connected to the input of analog adder, analog adder is output as d (t), and the non-linear and quantizing noise of d (t) is far below the non-linear and quantizing noise in c (n).The nonlinear model of digital to analog converter DAC1 is normally fixed, estimate in advance the negative signal that utilizes after its nonlinear model digital signal to generate nonlinear component, thereby both are added and will effectively suppress nonlinear component and reach higher dynamic range at analog domain.
Analog signal a
2(t) through simulation delayer 1, postpone to obtain later signal e (t), retardation in reality by analog to digital converter ADC1, digital phase shift gain module and digital to analog converter DAC1 and between connecting line jointly determine, and in the situation that hardware state is certain, this retardation is a fixed value.
Adder is by e (t) and subtract each other d (t), obtain linear segment suppressed signal f (t), so the power of f (t) is much smaller than the power of e (t) and d (t).
As shown in Figure 5, filter and amplification module comprises filter and amplifier.Analog signal f (t) enters filter, and to carry out the high dynamically output of D/A converter module be Qwest's interval selection, and filter output connects amplifier, and amplifier is subject to the control of gain parameter G, exports the analog signal g (t) of corresponding power.In this step, to the passband fluctuation of the noise factor of amplifier and filter, need to there are certain requirements, negligible to guarantee quantizing noise and non-linear effects in c (n).
Signal g (t) sends into simulation and carries out delay process in delayer 2 and generate h (t).This is because will guarantee that the time of i (n) and j (n) arrival joint control is synchronous, and digital time delayer can only be adjusted the integral multiple of digit chip clock cycle, therefore need to realize minute several times time delay of digit chip clock cycle at analog domain.
H's analog to digital converter ADC2 (t) is sampled and quantification obtains digital signal i (n).Signal i (n) has comprised nonlinear component and the quantizing noise except the linear component of h (t).
Digital time delayer carries out delay process to c (n) and obtains j (n).The amount of delay is here the integral multiple part of the amount of delay of path c (n) → d (t) → f (t) → g (t) → h (t) → i (n) to digital chip period.
As shown in Figure 6, joint control comprises multiplier 3, multiplier 4, multiplier 5, a duplicate vibration generator, two low pass filters, a complex gain algorithm for estimating circuit and an adder.Digital signal j (n) and duplicate vibration generator are connected to multiplier 3 and carry out computing, digital signal i (n) is connected by multiplier 4 with duplicate vibration generator, the output of multiplier 3 and multiplier 4 is connected to respectively low pass filter 1 and low pass filter 2, the output of low pass filter 1 and low pass filter 2 is connected to complex gain algorithm for estimating circuit simultaneously, the output of low pass filter 2 is also connected to multiplier 3, the output of complex gain algorithm for estimating circuit is connected to multiplier 3, the output of multiplier 3 outputs and low pass filter 1 is connected to adder simultaneously, adder is output as digital signal k (n).
Described parameter search/method of estimation comprises the following steps:
As shown in Figure 7, parameter search/estimation module comprise time delay algorithm for estimating circuit, get power circuit, the Ceil circuit that rounds up, subtracter, calibration of power algorithm circuit and minimum power search circuit.I (n) is connected time delay algorithm for estimating circuit with j (n) simultaneously, time delay algorithm for estimating circuit connects round up Ceil circuit and subtracter negative terminal mouth simultaneously, the output of Ceil circuit of rounding up connects the positive port of subtracter, the adjustment amount t that output signal is digital time delayer simultaneously
3, adder is output as the adjustment amount t of simulation delayer 2
2power circuit is got in i (n) connection, get power circuit output and connect calibration of power algorithm circuit and minimum power search circuit simultaneously, the gain G of calibration of power algorithm circuit output filtering amplification module, the complex gain S (amplitude and phase place be totally two dimensions) of minimum power search output three-dimensional search parameter digital phase shift gain module and the adjustment amount t of simulation delayer 1
1(dimension).Calibration of power algorithm circuit and minimum power search circuit need to carry out reasonably design to guarantee that both can not clash.
The adjustment amount t of simulation delayer 1
1by control interface 3, output to simulation delayer 1, adjust the amount of delay of e (t); The gain G of filter and amplification module outputs to filter amplifier module by control interface 2, adjusts the power of g (t); The adjustment amount t of simulation delayer 2
2by control interface 1, output in simulation delayer 2, adjust the fraction time sampling cycle amount of delay of h (t); The complex gain S of digital phase shift gain module outputs to digital phase shift gain module, adjusts power and the phase place of c (n); The adjustment amount t of digital time delayer
3output to digital time delayer, adjust the integer sampling period time delay of j (n).
The adjustment amount t of simulation delayer 1
1, filter and amplification module gain G and simulation delayer 2 adjustment amount t
2needs be undertaken between sheet respectively mutual by control interface 3, control interface 2 and control interface 1, be such as but not limited to interface or the agreements such as SPI, serial ports, GPIO.
The complex gain S of digital phase shift gain module and the adjustment amount t of digital time delayer
3by software interface, carry out intermodule mutual.
Claims (3)
1. a device that improves analog to digital converter dynamic range, it is characterized in that: comprise AGC merit sub-module, analog to digital converter ADC1, digital phase shift gain module, simulation delayer 1, high dynamically D/A converter module, adder, filter and amplification module, simulation delayer 2, analog to digital converter ADC2, digital time delayer, joint control, parameter search/estimation module and control interface, the two-way output of AGC merit sub-module is connected with simulation delayer 1 with analog to digital converter ADC1 respectively, the output of analog to digital converter ADC1 is connected with digital phase shift gain module, the output of digital phase shift gain module is connected with digital time delayer with digital to analog converter DAC1 respectively, the output of simulation delayer 1 and high dynamic number weighted-voltage D/A converter is connected with two inputs of adder respectively, the output of adder is connected with filter and amplification module, the output of filter and amplification module is connected with simulation delayer 2, the output of simulation delayer 2 is connected with analog to digital converter ADC2, the output of digital time delayer and analog to digital converter ADC2 is connected with two inputs of joint control respectively, the output of digital time delayer and analog to digital converter ADC2 is also connected with parameter search/estimation module, parameter search/estimation module is exported five tunnel control signals, wherein You San road is connected to control interface, all the other two-way are connected with digital phase shift gain module with digital time delayer respectively, the output of control interface respectively with simulation delayer 2, filter and amplification module is connected with simulation delayer 1.
2. a kind of device that improves analog to digital converter dynamic range according to claim 1, it is characterized in that: described control interface comprises control interface 1, control interface 2 and control interface 3, the input of control interface 1, control reception 2 and control interface 3 is connected with the output of parameter search/estimation module San road respectively, and the output of control interface 1, control interface 2 and control interface 3 is connected with simulation delayer 2, filter and amplification module and simulation delayer 1 respectively.
3. a method that improves analog to digital converter dynamic range, is characterized in that: comprise signal treatment step and parameter search/estimating step, wherein, described signal treatment step comprises following sub-step:
S101:AGC merit sub-module receives analog signal a (t), analog signal a (t) is amplified, and be divided into two-way analog signal a
1and a (t)
2(t);
S102: by analog signal a
1(t) send into analog to digital converter ADC1, by sampling and the quantification of analog to digital converter ADC1, obtain digital signal b (n);
S103: digital signal b (n) is sent into digital phase shift gain module, gain and the phase place of digital phase shift gain module correcting digital signal b (n), the digital signal c after being proofreaied and correct (n);
S104: digital signal c (n) is sent into high dynamically D/A converter module, and high dynamically D/A converter module is transformed into analog domain by the digital signal c (n) after proofreading and correct and obtains analog signal d (t);
S105: by analog signal a
2(t) send into simulation delayer 1, analog signal a
2(t) through simulation delayer 1, postpone to obtain later analog signal e (t);
S106: analog signal d (t) and analog signal e (t) are sent into adder, and adder is subtracted each other analog signal e (t) and simulation d (t), obtains analog signal f (t);
S107: analog signal f (t) is sent into filter and amplification module, and filter and amplification module is carried out filtering to analog signal f (t), amplifies through amplifier, obtains analog signal g (t);
S108: analog signal g (t) is sent in simulation delayer 2 and carries out delay process, obtain analog signal h (t);
S109: analog signal h (t) is sent into analog to digital converter ADC2, and analog to digital converter ADC2 samples and quantizes analog signal h (t), obtains digital signal i (n);
S110: digital signal c (n) is sent into digital time delayer, obtain digital signal j (n) through delay process;
S111: digital signal i (n) and digital signal j (n) are sent into joint control, generate the digital signal k (n) of final output;
Described parameter search/estimating step, comprises following sub-step:
S201: the digital signal i in signal treatment step (n) and digital signal j (n) are sent into parameter search/estimation module, obtain simulating the adjustment amount t of delayer 1
1, the gain G in filter amplifier module, simulation delayer 2 adjustment amount t
2, the complex gain S of digital phase shift gain module and the adjustment amount t of digital time delayer
3;
S202: by the adjustment amount t of simulation delayer 1
1, the gain G in filter amplifier module, simulation delayer 2 adjustment amount t
2by control interface 3, control interface 2 and control interface 1, output to simulation delayer 1 respectively and adjust amount of delay, the power of filter amplifier module adjustment g (t) of e (t) and simulate the fraction time sampling cycle amount of delay that delayer 2 is adjusted h (t), by the adjustment amount t of the complex gain S of digital phase shift gain module and digital time delayer
3output to respectively digital phase shift gain module and adjust the integer sampling period time delay of power and phase place and the digital time delayer adjustment j (n) of c (n).
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| CN104467863A (en) * | 2014-11-07 | 2015-03-25 | 武汉虹信通信技术有限责任公司 | System and method for solving small signal output nonlinearity of DAC |
| CN104467863B (en) * | 2014-11-07 | 2017-12-15 | 武汉虹信通信技术有限责任公司 | A kind of system and method for solution DAC small-signal output nonlinears |
| CN106571826A (en) * | 2016-11-11 | 2017-04-19 | 西安电子科技大学 | System for increasing single-chip-microcomputer analog-to-digital-converter dynamic scope and method thereof |
| CN106571826B (en) * | 2016-11-11 | 2019-10-01 | 西安电子科技大学 | A kind of system and method improving single-chip microcontroller analog-digital converter dynamic range |
| CN108363295A (en) * | 2017-12-27 | 2018-08-03 | 国网山东省电力公司电力科学研究院 | Fired power generating unit AGC Performance Assessment indexs based on System Discrimination calculate and prediction technique |
| CN108363295B (en) * | 2017-12-27 | 2020-11-13 | 国网山东省电力公司电力科学研究院 | Thermal power generating unit AGC performance assessment index calculation and prediction method based on system identification |
| CN111130648A (en) * | 2019-12-31 | 2020-05-08 | 中国科学院微电子研究所 | Optical communication signal receiving method, signal receiving device and electronic equipment |
| CN111130648B (en) * | 2019-12-31 | 2021-06-08 | 中国科学院微电子研究所 | Optical communication signal receiving method, signal receiving device and electronic equipment |
| CN112763956A (en) * | 2020-12-29 | 2021-05-07 | 电子科技大学 | Method for increasing dynamic range of magnetic resonance signal by scrambling technique |
| CN112763956B (en) * | 2020-12-29 | 2022-02-15 | 电子科技大学 | Method for increasing dynamic range of magnetic resonance signal by scrambling technique |
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