CN104467863B

CN104467863B - A kind of system and method for solution DAC small-signal output nonlinears

Info

Publication number: CN104467863B
Application number: CN201410624264.4A
Authority: CN
Inventors: 杨杰; 艾锋
Original assignee: Wuhan Hongxin Telecommunication Technologies Co Ltd
Current assignee: CICT Mobile Communication Technology Co Ltd
Priority date: 2014-11-07
Filing date: 2014-11-07
Publication date: 2017-12-15
Anticipated expiration: 2034-11-07
Also published as: CN104467863A

Abstract

The present invention provides a kind of system and method for solution DAC small-signal output nonlinears, including power detecting unit, power threshold setting unit, gain control unit and Gain Automatic recovery unit.Power detection and thresholding are set all to be completed in FPGA numerical portion program, gain is controlled and automatic recovery is completed by the numerical-control attenuator behind MCU control FPGA numerical portions program, DAC, it is less than thresholding to DAC power when MCU detects, increase the gain in FPGA, equivalent to numerical value of the increase numerical portion to DAC, so as to reduce the non-linear of DAC.The present invention can be obviously improved IM3, and effective noise-reduction coefficient present invention has the characteristics of saving hardware cost, reliable and stable in contrast to other method for whole system.

Description

A kind of system and method for solution DAC small-signal output nonlinears

Technical field

The present invention relates to one kind to solve DAC（Digital analog converter）The system and method for small-signal output nonlinear.

Background technology

In existing optic-fiber repeater system, whole link includes receiving link and emitting portion link, receiving portion chain Road signal stream：Low-noise amplifier+ATT+frequency mixer+driving amplifier+anti-mix falls wave filter+ADC+FPGA（Scene can compile Journey gate array）+ laser.Emitting portion signal link signal stream：Laser+FPGA+DAC+IQ modulators+amplifier+ATT+ Amplifier.Specific schematic diagram is shown in Figure of description 1：

To whole signal chains, signal low noise theory reduction formula is as follows：

Useful signal low noise power (dBm)=(- 174+NF+GAIN)/RBW formula（1）

The each carrier wave 200K of gsm system, when single carrier exports, equivalent to RBW=200K（WCDMA single carrier 3.84M, quite In RBW=3.84M）, the power that useful signal bandwidth product is got is also relatively small, small equivalent to DAC power output, defeated When going out power very little, if DAC produce non-linear distortion, caused error compare it is larger, equivalent to low noise ratio itself It is normal bigger than normal, from formula（1）Find out, for system index, influence the noise coefficient of system.To solve system by the small letters of DAC Number non-linear, value of the increase numerical portion to DAC caused by output, it is non-linear caused by the output of DAC small-signals to reduce, so as to Optimize noise coefficient.

In the entire system, the high-speed DAC device used, all it is to use current mode at present, 16 current mode DAC is come Say, it is necessary to=256 current sources and switch.As shown in Figure of description 2.For chip, switch and current source number are more, It is relatively large chip area to be accounted for.So generally low 4 use binary code current source, the DAC framework such as explanation of binary code Shown in book accompanying drawing 3, the current source and switch of occupancy are few a lot;Using binary code mode, such as 4 DAC, using thermometer-code DAC, current source and switch need 16, using binary code, it is necessary to current source and 4, switch.But binary code, due to depositing In such as hopping phenomenon of Figure of description 4, such as during 011 to 100 saltus step, the discontinuity in existence time, can cause non-linear Produce, consider that DAC low levels use binary code, and other positions use thermometer-code in the compromise of linear and chip area.For system For, non-linear caused three ranks are very big on the influence of system low noise, so as to influence noise coefficient to ensure that DAC small-signals are defeated Go out, it is non-linear not influence noise coefficient, it is required for ensureing that IM3 caused by DAC non-linear distortions is less than -25DB（This is a warp Test value）, theory conversion, during IM3=- 25dB, IM3 value is 1/ relative to main signal=3.1/1000, relative to main signal For, IM3 values can be ignored, will not low noise in lifting band.

In the prior art, to solve the problems, such as DAC small-signal output nonlinears, generally increase simulation detection is exported in DAC Device, DAC power outputs are detected, ATT states behind FPGA states and DAC are then controlled by MCU.

The content of the invention

Include LNA before system reception part, frequency mixer, IF amplifier circuit, in not input signal, DAC is effective Working position is 4.The present invention designs a kind of threshold detector in the FPGA of digital processing part, judges in FPGA to DAC's Number of significant digit, when judging to be less than 5 to DAC number of significant digit, increase the numerical value to DAC in numerical portion, numerical value moved to left two, The effective working positions of DAC are allowed to increase by two, so as to reduce non-linear, optimization system noise factor caused by the output of DAC small-signals.Send Numerical value to DAC moves to left two, and due to moving to left one, power is equivalent to increase 6DB, all to move to left two, increases equivalent to power Add 12DB, to ensure that the gain of whole system is constant, it is necessary to the 12DB that decays behind DAC, so Threshold detection is to the effective of DAC Position is less than 5, and numerical portion gives DAC numerical value and moves to left two, the ATT decay 12DB behind transmitting chain.If DAC is big During signal output, it is bigger that FPGA gives DAC numerical value, it is non-linear caused by distortion it is smaller, at this time can not be again giving DAC Numerical value moves to left 2, is not so likely to result in DAC spillings, is shut off the function, system worked well.

Concrete technical scheme is as follows：

Including power detecting unit, power threshold setting unit, gain control unit, Gain Automatic recovery unit；

Power detecting unit, function of the increase calculating to DAC power in FPGA；

Power threshold setting unit, will be small in the significance bit for giving DAC according to the significance bit judged to DAC in FPGA Power when 5, which is used as, judges thresholding；

Gain control unit, in MCU, when FPGA detections give DAC power less than thresholding is judged, then in FPGA Gain becomes big 12DB, and to ensure that whole system gain is constant, FPGA transmits instruction and passes through numerical control attenuation behind DAC to MCU, MCU Device is decayed 12DB automatically；

Gain Automatic recovery unit, in MCU, when FPGA detections give DAC power more than threshold value is judged, Gain recovery in FPGA is normal, while the numerical-control attenuator behind DAC recovers normal.

Comprise the following steps,

Step 1, FPGA calculate the power to DAC, and thresholding is set in FPGA according to result of calculation, give DAC numerical value and are 4, and 4 are 1111, the threshold power now obtained in FPGA is A；

Step 2, when the numerical value power for giving DAC is less than A, then the value for giving DAC moves to left two, for ensure system gain It is constant, while the 12DB that decays in the numerical-control attenuator behind DAC；

Step 3, thresholding is further added by 12DB on the basis of step 2, i.e., moves to left 2 DAC value is given, obtain thresholding B； Using thresholding B as final judgement thresholding；

It is less than B when giving DAC numerical value, FPGA moves to left 2 to DAC, and the numerical-control attenuator behind DAC is decayed 12DB automatically, When the value for giving DAC is more than B, the attenuator function is closed automatically.

Compared with prior art, the present invention has advantages below and beneficial effect：

Compared with prior art, the present invention can save analog detector, save cost, while MCU controls are, it is necessary to MCU Circulation reading is carried out to wave detector power, then controls FPGA and ATT states, the whole time is both greater than 1 second, directly examined in FPGA Ripple, time can be controlled within 20MS, and from the point of view of the implementation result of the present invention, actual control is within 10MS.

Brief description of the drawings

Fig. 1 is that optical fiber repeater receives and radiating circuit structure chart in the prior art.

Fig. 2 is traditional DAC thermometer-codes Organization Chart.

Fig. 3 is traditional DAC binary codes Organization Chart.

Fig. 4 is traditional non-linear schematic diagram of DAC binary codes.

Fig. 5 is the receiving portion circuit structure diagram of the embodiment of the present invention.

Fig. 6 is the emitting portion circuit structure diagram figure of traditional approach.

Fig. 7 is the emitting portion circuit structure diagram that the present invention is implemented.

Embodiment

Describe technical scheme in detail with reference to the accompanying drawings and examples.

Intermodulation is to effect of signals caused by theory analysis non-linear distortion：According to formula：

P=10LG (P/1mW) unit：DBM formula（2）

Assuming that P1 is main signal, P2 is intermodulation signal power, P2-P1=- 25DBC, according to formula（2）, -25=10LG (P2/ P1), theoretical calculation goes out P2/P1=0.316%.

The result of DAC non-linear distortions is individually tested first, and two-tone signal is sent out to DAC with FPGA, it is not non-thread in theory Property distortion, DAC outputs are two single tone signals, and due to non-linear distortion be present, DAC outputs have many intermodulations letters Number.To DAC test results：

The effective working positions of DAC（BIT）	IM3 absolute values (dBm)	IM3 relative values (dB)
			4	-97.8	-15.8

			The effective working positions of DAC	IM3 absolute values (dBm)	IM3 relative values (dB)
6	-103.5	-27.7

From test result above significance bit is can be seen that to work the change of 4 to 6, caused intermodulation signal M1 from- 97.8dBm, which becomes, turns to -103.5dBm, and intermodulation signal declines 5.7DB.Experiment is proved to give DAC numerical value by increase, can subtracted Small DAC is non-linear.Next work：

The first step, FPGA calculate the power to DAC, set thresholding in numerical portion FPGA according to result of calculation, give DAC numerical value is 4, and 4 are 1111,4 bit values maximum equivalent to supply DAC, the door at this time obtained in FPGA Limit power is set to A.

Second step, when the numerical value power for giving DAC is less than A, then the value for giving DAC moves to left two, for ensure system increasing Benefit is constant, while the 12DB that decays in the ATT attenuators behind DAC.

3rd step, uniformity of the decay in batch is automatically controlled for guarantee, thresholding is further added by the basis of second step 12DB, i.e., 2 are moved to left DAC value is given, obtain thresholding B；Using B thresholdings as final judgement thresholding, equivalent to 6 maximums 111111, as final thresholding, ensure when full 6, to move to left two, 16BIT DAC will not be overflowed, do not interfere with and be System function；It is less than B when giving DAC numerical value, numerical portion moves to left 2 to DAC, ATT behind DAC decay 12DB, when giving DAC Value be more than B, the function is closed automatically.

After the completion of said process, verify whether its function meets to require, connect whole system, the system for testing single carrier wave Noise coefficient, begin to shut off the function, test noise coefficient 8.5DB, gain 50DB；It is then turned on the function, test noise system Number 1.5DB, gain 50DB；Prove that the present invention can preferably solve the problems, such as system noise factor.

And in the present invention：

（1）Power detecting unit, power threshold setting unit are handled in FPGA, without extra increase hardware, pass through number Word quantifies, and precision is high, and detection time quickly, can be less than 10MS.

（2）Gain control unit realizes gain control function in MCU, by the numerical-control attenuator behind MCU, DAC, declines Subtract numerical-control attenuator and MCU communications that precision reaches 0.5dB, while FPGA and MCU communicates, after the FPGA big 12DB of gain change, FPGA is accordingly said the word to MCU, and MCU control attenuators are decayed 12DB automatically, ensure that whole system gain is constant.

（3）Gain Automatic recovery unit, if FPGA gives DAC power and is more than thresholding, FPGA increases the work(of 12DB gains It can cancel, FPGA controls the decay 12DB functions of numerical-control attenuator also to cancel by MCU.

The present invention can be effectively improved the non-linear of DAC small-signals output, and actual measurement is obviously improved IM3, for whole system Can effective noise-reduction coefficient.

Specific embodiment described herein is only to spirit explanation for example of the invention.Technology belonging to the present invention is led The technical staff in domain can be made various modifications or supplement to described specific embodiment or be replaced using similar mode Generation, but without departing from the spiritual of the present invention or surmount scope defined in appended claims.

Claims

A kind of 1. system of solution DAC small-signal output nonlinears, it is characterised in that：Including power detecting unit, power threshold Setting unit, gain control unit, Gain Automatic recovery unit；

Power detecting unit, increase the function of calculating and give DAC magnitude of powers in FPGA；

Power threshold setting unit, DAC significance bit is given according to judgement in FPGA, 5 will be less than in the significance bit that giving DAC Power during position, which is used as, judges thresholding；

Gain control unit, in MCU, when FPGA detections give DAC power less than thresholding is judged, then the increasing in FPGA Benefit becomes big 12DB, and to ensure that whole system gain is constant, FPGA transmits instruction and passes through the numerical control attenuation behind DAC to MCU, MCU Device is decayed 12DB automatically；

Gain Automatic recovery unit, in MCU, when FPGA detections give DAC power more than threshold value is judged, in FPGA Gain recovery it is normal, while numerical-control attenuator behind DAC recovers normal.
A kind of 2. method of solution DAC small-signal output nonlinears, it is characterised in that：Comprise the following steps,

Step 1, FPGA calculate the power for giving DAC, and thresholding is set in FPGA according to result of calculation, give DAC numerical value as 4 Position, and 4 are 1111, the threshold power now obtained in FPGA is A；

Step 2, when the numerical value power for giving DAC is less than A, then the value for giving DAC moves to left two, for ensure system gain not Become, while the 12DB that decays in the numerical-control attenuator behind DAC；

Step 3, thresholding is further added by 12DB on the basis of step 2, i.e., moves to left 2 DAC value is given, obtain thresholding B；Door B is limited as final judgement thresholding；

It is less than B when giving DAC numerical value, FPGA moves to left 2 to DAC, and the numerical-control attenuator behind DAC is decayed 12DB automatically, when sending Value to DAC is more than B, and the attenuator function is closed automatically.