CN114464715B

CN114464715B - Infrared emitter and preparation method thereof, display panel and preparation method thereof, and terminal

Info

Publication number: CN114464715B
Application number: CN202110757404.5A
Authority: CN
Inventors: 安亚斌; 贺海明
Original assignee: Honor Device Co Ltd
Current assignee: Honor Device Co Ltd
Priority date: 2021-07-05
Filing date: 2021-07-05
Publication date: 2024-03-29
Anticipated expiration: 2041-07-05
Also published as: CN114464715A

Abstract

The embodiment of the application provides an infrared emitter, a preparation method thereof, a display panel, a preparation method thereof and a terminal. The infrared emitter comprises a P-type silicon substrate, a light-emitting layer positioned on one surface of the P-type silicon substrate, a top electrode positioned on one side of the light-emitting layer away from the P-type silicon substrate, and a bottom electrode electrically connected with the P-type silicon substrate. Wherein the light emitting layer comprises ytterbium-doped quasicrystal oxide.

Description

Infrared emitter and preparation method thereof, display panel and preparation method thereof, and terminal

Technical Field

The application relates to the technical field of display, in particular to an infrared emitter, a preparation method of the infrared emitter, a display panel, a preparation method of the display panel and a terminal.

Background

The 3D camera introduces a 3D sensing technology based on Time of Flight (ToF) ranging or Structured Light (SL) based on a conventional camera. At present, both of the two mainstream 3D sensing technologies are active sensing. Therefore, compared with the traditional camera industry chain, the 3D camera industry chain is mainly and newly added with an infrared light source, an optical component, an infrared sensor and the like. The most critical part of these is the infrared light source, and actively perceived 3D camera technology typically uses infrared light to detect objects.

Regarding infrared light source, III-V compounds such as GaAs are direct forbidden band semiconductors, and the electron hole recombination efficiency is high, so that the method is suitable for manufacturing high-power semiconductor devices. Currently, toF emitters include high power high frequency radiating devices fabricated based on GaAs substrates. However, the preparation of III-V compound light emitting devices such as GaAs is not compatible with silicon-based processes, and the production cost is high. In addition, the silicon-based infrared emitter has the following advantages: the silicon-based material has low raw material cost, rich silicon crust reserve and low preparation cost; is compatible with silicon-based processes; the electrical property is excellent, and the silicon-based semiconductor circuit can be used for direct driving; the expansion coefficient is small, and the optical microcavity structure is stable; high yield strength and stable optical microcavity structure; the heat conduction performance is good; the luminous intensity is not quenched with the temperature rise, and the failure during the high-current work and the like can not be caused. However, since silicon is an indirect forbidden band semiconductor, the recombination process is accompanied by phonon diffusion, and the luminous efficiency is low (millisecond), which limits the development of silicon-based optoelectronic integration.

Thus, challenges remain in how to fabricate infrared emitters compatible with silicon-based processes.

Disclosure of Invention

A first aspect of the present application provides an infrared emitter comprising:

A P-type silicon substrate;

a light emitting layer on one surface of the P-type silicon substrate;

a top electrode located at one side of the light emitting layer away from the P-type silicon substrate; and

a bottom electrode electrically connected to the P-type silicon substrate;

wherein the light emitting layer comprises ytterbium-doped quasicrystal oxide.

In the infrared emitter, the quasicrystal oxide doped with ytterbium is formed on the P-type silicon substrate, and a framework is provided for ytterbium doping by utilizing the characteristic that the quasicrystal oxide has a three-dimensional rigid structure, so that energy level transition can be generated on an inner track sheet of ytterbium, and infrared light with characteristic wavelength of ytterbium is excited. In addition, in the infrared emitter, the substrate is a P-type silicon substrate, so that the cost is low, and the infrared emitter can be integrated with other silicon-based devices. Thus, the preparation of the silicon-based infrared emitter is realized.

In some embodiments of the present application, the quasicrystal form oxide is a material capable of providing a face-centered cubic structure of an octahedron or tetrahedron to provide a framework for ytterbium incorporation.

In some embodiments of the present application, the quasi-crystalline oxide includes at least one of titanium dioxide, silicon oxide. The titanium dioxide and the silicon oxide easily form oxygen vacancies in the lattice structure, and the intrinsic defect concentration is high, so that the injection and the transmission of carriers are easy to realize, and the titanium dioxide and the silicon oxide are suitable ytterbium-doped base materials. And the ytterbium-doped silicon oxide and ytterbium-doped titanium dioxide are inorganic materials, have stable physical and chemical properties, and do not have the common aging problem in organic materials when being used as inorganic electroluminescent materials.

In some embodiments of the present application, the P-type silicon substrate has a resistivity of 0.001 Ω.cm to 0.1 Ω.cm, so that it has a high hole injection capability.

In some embodiments of the present application, the material of the top electrode is selected from at least one of N-type low temperature polysilicon, indium tin oxide, indium zinc oxide, indium gallium zinc oxide. Wherein the N-type low-temperature polysilicon has a very thin thickness, such asIn the following, the transparent glass is almost transparent, and the infrared transmittance is as high as 90 percent. And indium tin oxide, indium zinc oxide and indium gallium zinc oxide are all transparent materials, and have high infrared transmittance. Therefore, the top electrode can be prevented from shielding the emitted infrared light, and the luminous effect of the infrared emitter is improved.

In some embodiments of the present application, the bottom electrode is located on a surface of the P-type silicon substrate remote from the light emitting layer, the material of the bottom electrode being selected from at least one of molybdenum, titanium oxide; alternatively, the bottom electrode is formed by conducting a partial P-type silicon substrate. When the material of the bottom electrode is selected from molybdenum, titanium and other metals, the bottom electrode of the metal material and the P-type silicon substrate can form good ohmic contact. When the material of the bottom electrode is titanium oxide, the titanium oxide has better reflectivity to infrared light, and can reflect the infrared light incident on the titanium oxide, so that the light-emitting efficiency of the infrared light of the infrared emitter is improved. The conductive process implants a large dose of boron or phosphorous (B/P) into the P-type silicon substrate, turning it into a conductor to act as the bottom electrode of the infrared emitter.

A second aspect of the present application provides a method for preparing an infrared emitter, comprising:

forming a quasi-crystal oxide layer on a surface of a P-type silicon substrate;

performing ytterbium-doped treatment on the alignment crystal oxide layer to obtain ytterbium-doped quasi-crystal oxide;

forming a top electrode on one side of the ytterbium-doped quasi-crystal oxide far away from the P-type silicon substrate; and

forming a bottom electrode electrically connected with the P-type silicon substrate;

wherein the luminescent layer of the infrared emitter comprises ytterbium-doped quasicrystal oxide.

In one embodiment, the quasicrystal form oxide layer is a silicon oxide layer. A silicon oxide layer is formed using chemical vapor deposition. And injecting ytterbium into the silicon oxide layer by adopting ion injection to obtain ytterbium-doped silicon oxide, thereby forming the light-emitting layer. An N-type semiconductor is deposited on the ytterbium doped silicon oxide, the N-type semiconductor serving as a top electrode.

In some embodiments of the present application, the bottom electrode is formed on a surface of the P-type silicon substrate remote from the light emitting layer; alternatively, a portion of the P-type silicon substrate is subjected to a conductive process to form a bottom electrode. Wherein the conductive material may be formed on a surface of the P-type silicon substrate remote from the light emitting layer. The conductive material is, for example, at least one selected from molybdenum, titanium, and titanium oxide. The conductive material acts as a bottom electrode. Alternatively, a portion of the P-type silicon substrate is implanted with a high dose of boron/phosphorus (B/P) to become partially doped into a conductor to act as a top electrode.

A third aspect of the present application provides a display panel, including a plurality of first pixels, each first pixel including at least one display sub-pixel for emitting visible light and at least one infrared sub-pixel for emitting infrared light; each display sub-pixel comprises a visible light emitting device and a driving TFT electrically connected with the visible light emitting device; each infrared subpixel comprises an infrared emitter, the infrared emitter being the infrared emitter; the display panel comprises a substrate and a P-type polycrystalline silicon layer positioned on the substrate; the part of the P-type polycrystalline silicon layer located in the display sub-pixel forms an active layer of the driving TFT, and the part of the P-type polycrystalline silicon layer located in the infrared sub-pixel forms a P-type silicon substrate of the infrared emitter.

The display panel is integrated with an infrared emitter, a P-type polycrystalline silicon layer for preparing an active layer of a driving TFT is utilized for preparing a P-type silicon substrate of the infrared emitter, an ytterbium-doped quasi-crystal oxide is formed on the P-type silicon substrate, and a framework is provided for ytterbium doping by utilizing the characteristic that the quasi-crystal oxide has a three-dimensional rigid structure, so that energy level transition can be generated on an inner track sheet of ytterbium, and infrared light with characteristic wavelength of ytterbium is excited. Thus, the preparation of the infrared emitter can be integrated with other silicon-based devices (such as a driving TFT), and the preparation of the infrared emitter compatible with a silicon-based process is realized.

In some embodiments of the present application, the display panel further includes a quasi-crystalline oxide layer covering the P-type polysilicon layer; the part of the quasi-crystal oxide layer positioned in the display sub-pixel forms a gate insulating layer of the driving TFT, and the part of the quasi-crystal oxide layer positioned in the infrared sub-pixel forms a light emitting layer after ytterbium-doped treatment. That is, the light emitting layer of the infrared emitter can be prepared by ytterbium-doped treatment of the quasi-crystal oxide layer of the gate insulating layer of the driving TFT, thereby simplifying the process.

In some embodiments of the present application, a visible light emitting device includes a first electrode electrically connected to a driving TFT; the projection of the first electrode on the substrate does not overlap with the projection of the top electrode on the substrate in the thickness direction of the substrate. Therefore, when the infrared light emitted by the infrared emitter is incident to an object to be detected, the infrared light does not pass through the first electrode of the visible light luminescent device. Thus, the problem that imaging cannot be performed due to optical diffraction generated with the first electrode of the visible light emitting device can be avoided. Moreover, by integrating the infrared emitter into the display panel, the screen duty ratio of the front (display face) of the display panel is further increased compared to the manner of digging holes, a water droplet screen, or Liu Haibing (Notch) in the display panel.

In some embodiments of the present application, the driving TFT further includes:

the grid electrode is positioned on the grid electrode insulating layer;

an interlayer dielectric layer covering the gate; and

the source electrode and the drain electrode are electrically connected with the active layer through a via hole penetrating through the gate insulating layer and the interlayer dielectric layer;

wherein, the interlayer dielectric layer is provided with a through hole in the region corresponding to the infrared sub-pixel, and the top electrode is filled with the through hole to be connected with the light-emitting layer.

In some embodiments of the present application, the top electrode is electrically connected to a chip via leads; the lead, the source electrode and the drain electrode are formed by patterning the same conductive layer. Thus, the process is simplified.

In some embodiments of the present application, the visible light emitting device is an organic light emitting diode or a micro-inorganic light emitting diode. The organic light emitting diode or the miniature inorganic light emitting diode is a self-luminous device, so that the display panel can realize self-luminescence without a backlight source.

In some embodiments of the present application, the display panel further includes a plurality of second pixels, each second pixel includes at least one display sub-pixel but does not include an infrared sub-pixel, and the number of display sub-pixels in the second pixels is the same as the number of display sub-pixels in the first pixels. When the display panel distributes infrared emitters only in a partial area in the display area, the influence of the infrared subpixels on the resolution of the display panel can be reduced. In other embodiments of the present application, only the first pixel is disposed in the entire display area of the display panel. That is, an infrared emitter is disposed in each pixel of the display panel, so that more infrared light is projected to an object to be detected (e.g., a human face), thereby achieving the purpose of improving the 3D depth scanning accuracy.

A fourth aspect of the present application provides a terminal, which includes the display panel described above.

In some embodiments of the present application, the terminal further comprises an imaging sensor, the infrared emitter is configured to emit infrared light to the object to be measured, and the imaging sensor is configured to receive the infrared light reflected back by the object to be measured, so as to obtain depth information of the object to be measured.

A fifth aspect of the present application provides a method for manufacturing a display panel, where the display panel includes a plurality of first pixels, each first pixel including at least one display sub-pixel for emitting visible light and at least one infrared sub-pixel for emitting infrared light; each display sub-pixel comprises a visible light emitting device and a driving TFT electrically connected with the visible light emitting device; each infrared subpixel includes an infrared emitter, the infrared emitter including:

a P-type silicon substrate;

a light emitting layer on one surface of the P-type silicon substrate;

a bottom electrode electrically connected to the P-type silicon substrate;

wherein the light emitting layer comprises ytterbium-doped quasicrystal oxide;

the preparation method comprises the following steps:

preparing an active layer of a driving TFT and a P-type silicon substrate of an infrared emitter by using the same P-type polycrystalline silicon layer;

Preparing a gate insulating layer of a driving TFT and a light emitting layer of an infrared emitter;

preparing a top electrode of an infrared emitter; and

a bottom electrode of an infrared emitter is prepared.

According to the preparation method of the display panel, the P-type polycrystalline silicon layer of the active layer of the driving TFT is utilized to prepare the P-type silicon substrate of the infrared emitter, the ytterbium-doped quasi-crystal oxide is formed on the P-type silicon substrate, and the characteristics of a three-dimensional rigid structure of the quasi-crystal oxide are utilized to provide a framework for ytterbium doping, so that energy level transition can be generated on an inner track sheet of ytterbium, and infrared light with characteristic wavelength of ytterbium is excited. Thus, the preparation of the infrared emitter can be integrated with other silicon-based devices (such as a driving TFT), and the preparation of the infrared emitter compatible with a silicon-based process is realized.

In some embodiments of the present application, the gate insulating layer of the driving TFT and the light emitting layer of the infrared emitter are prepared using the same quasicrystal type oxide layer. That is, the light emitting layer of the infrared emitter can be prepared by ytterbium-doped treatment of the quasi-crystal oxide layer of the gate insulating layer of the driving TFT, thereby simplifying the process.

In some embodiments of the present application, the top electrode is prepared further comprising forming a gate electrode, an interlayer dielectric layer, a source electrode and a drain electrode of the driving TFT; the grid electrode is positioned on the grid electrode insulating layer, the interlayer dielectric layer covers the grid electrode, the source electrode and the drain electrode are electrically connected with the active layer, and a through hole is formed in the interlayer dielectric layer in a region corresponding to the infrared sub-pixel; the top electrode fills the through hole to be electrically connected with the light emitting layer.

In some embodiments of the present application, the step of preparing the bottom electrode includes patterning a conductive layer to form a light blocking layer and the bottom electrode; the light blocking layer is positioned on one side of the active layer, which is far away from the gate insulating layer, and the bottom electrode is positioned on the surface of the P-type silicon substrate, which is far away from the light emitting layer. When the light blocking layer is made of molybdenum, titanium and other metals, the bottom electrode of the metal material and the P-type silicon substrate can form good ohmic contact. When the light blocking layer is made of titanium oxide, the titanium oxide has better reflectivity to infrared light, so that the infrared light incident on the light blocking layer can be reflected, and the light emitting efficiency of the infrared light of the infrared emitter is improved.

In some embodiments of the present application, the step of preparing the bottom electrode includes conducting a portion of the P-type silicon substrate to form the bottom electrode. That is, the bottom electrode of the infrared emitter can be prepared by doping and conducting the active layer of the driving TFT to simplify the process.

Drawings

Fig. 1 is a schematic structural diagram of a terminal according to some embodiments of the present application.

Fig. 2 is a schematic structural view of the display panel in fig. 1.

Fig. 3 is a schematic structural view of a visible light emitting device according to some embodiments of the present application.

Fig. 4 is another schematic structural view of a visible light emitting device according to some embodiments of the present application.

Fig. 5 is a schematic diagram of the structure of an infrared emitter provided in some embodiments of the present application.

Fig. 6 is a schematic cross-sectional view of an infrared emitter provided in some embodiments of the present application.

Fig. 7 is another cross-sectional schematic view of an infrared emitter provided in some embodiments of the present application.

Fig. 8 is a schematic cross-sectional view of a display panel according to some embodiments of the present application.

Fig. 9 is a schematic structural diagram of a pixel driving circuit according to some embodiments of the present application.

Fig. 10 is a schematic diagram of the structure of an infrared projector, an imaging sensor and a controller according to some embodiments of the present application.

Fig. 11 is a schematic diagram of a 3D depth scan performed by a terminal according to some embodiments of the present application.

Fig. 12 is a schematic diagram of a depth detection performed by a terminal according to the prior art.

Fig. 13 is a flow chart of a method of manufacturing an infrared emitter according to some embodiments of the present application.

Fig. 14 is a flow chart illustrating a method for manufacturing a display panel according to some embodiments of the present invention.

Description of the main reference signs

Terminal 100

Cover plate 10

Display panel 20

Support structure 30

First pixel 22

Display sub-pixel 222

Infrared subpixel 224

Visible light emitting device 40

Anode 41

Hole transport layer 42

Organic light-emitting layer 43

A first organic light emitting layer 431

Electron hole pair secondary generation layer 44

Second organic light-emitting layer 432

Hole blocking layer 45

Electron transport layer 46

Cathode 47

First electrode 48

Infrared emitter 50

P-type silicon substrate 51

Light emitting layer 52

Top electrode 53

Bottom electrode 54

Light blocking layer 55

Lead 56

TFT backboard 60

Substrate 61

Drive circuit layer 62

Pixel driving circuit 620

Driving TFT T1

Switching TFT T2

Capacitor C

Buffer layer 621

First buffer layer 6211

Second buffer layer 6212

Opening 6213

Active layer 622

Gate insulating layer 623

First gate insulating layer 6231

Second gate insulating layer 6232

Grid 624

Bottom gate 6241

Top gate 6242

Interlayer dielectric layer 625

Source electrode 626

Drain 627

Planarization layer 628

Through hole 629

Pixel definition layer 63

Opening 632

Support column 64

Infrared projector 70

Imaging sensor 71

Controller 72

Object 80 to be measured

Display screen 1

Infrared emission end 2

Infrared receiving end 3

The following detailed description will further illustrate the application in conjunction with the above-described figures.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

The embodiment of the application provides a terminal, which can be a product with a display interface such as a mobile phone, a display, a tablet personal computer, a vehicle-mounted computer and the like, and an intelligent display wearing product such as an intelligent watch and an intelligent bracelet. The following will exemplify a mobile phone using a terminal.

As shown in fig. 1, the terminal 100 includes a cover plate 10, a display panel 20, and a support structure 30. The cover plate 10 defines a display surface of the terminal 100. The display panel 20 is used for displaying pictures. The support structure 30 is also referred to as a housing or back cover or battery cover. The cover plate 10 and the supporting structure 30 cooperate to form a containing space, and the display panel 20 is located in the containing space between the cover plate 10 and the supporting structure 30. In addition, other functional components/electronic components, such as a main board, a battery and the like, can be arranged in the accommodating space.

The structure of the display panel 20 will be described below.

As shown in fig. 2, the display panel 20 includes a plurality of first pixels (pixels) 22. Each first pixel 22 comprises at least one display sub-pixel 222 for emitting visible light and at least one infrared sub-pixel 224 (denoted IR) for emitting infrared light (IR). In fig. 2, the first pixel 22 includes three display sub-pixels 222, which are respectively a red-light-emitting display sub-pixel R, a green-light-emitting display sub-pixel G, and a blue-light-emitting display sub-pixel B.

In some embodiments of the present application, the visible light emitted by three display sub-pixels 222 in the first pixel 22 is cyan, magenta, and yellow, respectively. Alternatively, in other embodiments of the present application, the first pixel 22 includes four display sub-pixels 222, and the visible light emitted by the four display sub-pixels 222 is red light, green light, blue light, and white light, respectively. That is, the number of display sub-pixels 222 and the combination of the emission colors in the first pixel 22 are not limited.

On this basis, in order to enable the above-described display sub-pixel 222 to emit visible light, in some embodiments of the present application, the display panel 20 further includes a plurality of visible light emitting devices 40. Each of the visible light emitting devices 40 corresponds to one of the display sub-pixels 222, and each of the visible light emitting devices 40 is located within the display sub-pixel 222 corresponding to the visible light emitting device 40, thereby enabling the display panel 20 to achieve self-luminescence without providing a backlight.

The manner in which the above-described visible light emitting device 40 is disposed in the display panel 20 is exemplified below.

Example of visible light emitting device 40

In this example, the visible light emitting device 40 is an organic light emitting diode (Organic Light Emitting Diode, OLED). In this case, the display panel 20 is an active matrix organic light emitting diode (Active Matrix Organic Light Emitting Diode, AMOLED) display panel.

As shown in fig. 3, the visible light emitting device 40 is an OLED including an organic light emitting layer 43, and an anode 41 and a cathode 47 positioned at opposite sides of the organic light emitting layer 43.

In some embodiments of the present application, the material of the anode 41 may be a metal material, such as aluminum (A1), magnesium (Mg), silver (Ag), magnesium silver alloy (Mg/Ag), or the like. The material of the cathode 47 may be a transparent conductive material, for example, indium Tin Oxide (ITO), indium zinc Oxide (Indium Zinc Oxide, IZO). In this case, the cathode 47 transmits light, and the transmittance of the anode 41 is small, so that light emitted from the OLED exits from the side where the cathode 47 is located. At this time, the OLED is a top emission type light emitting device.

In other embodiments of the present application, the material of the anode 41 may be the transparent conductive material described above; the material of the cathode 47 is the above-described metal material. In this case, the anode 41 transmits light, and the cathode 47 has a small light transmittance, so that light emitted from the OLED exits from the side where the anode 41 is located. At this time, the OLED is a bottom emission type light emitting device.

In this way, after a voltage is applied to the anode 41 and the cathode 47 on both sides of the organic light-emitting layer 43, holes are injected from the anode 41, electrons are injected from the cathode 47, and carriers in the anode 41 and the cathode 47 recombine in the organic light-emitting layer 43 to quench, so that the organic light-emitting layer 43 emits light wave radiation. At this time, the OLED emits light, and the display panel 20 having a plurality of OLEDs performs screen display. Wherein. In the same first pixel 22, the materials of the organic light emitting layers 43 of the visible light emitting devices 40 in different display sub-pixels 222 are different, so that the visible light emitting devices 40 in different display sub-pixels 222 emit visible light of different colors, such as red light, green light, or blue light.

In addition, in order to increase the probability that carriers in the anode 41 and the cathode 47 meet in the organic light emitting layer 43 to increase the light emitting efficiency of the OLED, the OLED further includes a hole transport layer (hole transfer layer, HTL) 42, a Hole Blocking Layer (HBL) 45, and an electron transport layer (electron transfer layer, ETL) 46, as shown in fig. 3. Wherein the hole transport layer 42 is located between the organic light emitting layer 43 and the anode 41. The hole blocking layer 45, the electron transport layer 46 are located between the organic light emitting layer 43 and the cathode 47, and are in turn adjacent to the cathode 47. That is, in fig. 3, the lamination order of each film layer in the OLED is anode 41, hole transport layer 42, organic light emitting layer 43, hole blocking layer 45, electron transport layer 46, and cathode 47 in this order.

Example two of visible light emitting device 40

In example two, the visible light emitting device 40 is an OLED, which is different from the OLED of example one in that: in example two, the OLED includes a plurality of organic light emitting layers (431 and 432). As shown in fig. 4, the OLED includes a first organic light emitting layer 431, a second organic light emitting layer 432, and an electron hole pair secondary generation layer 44 between the first organic light emitting layer 431 and the second organic light emitting layer 432. That is, in fig. 4, the layers in the OLED are stacked in this order of the anode 41, the hole transport layer 42, the first organic light emitting layer 431, the electron hole pair secondary generation layer 44, the second organic light emitting layer 432, the hole blocking layer 45, the electron transport layer 46, and the cathode 47. The OLED with the structure is connected with more organic light emitting layers in series, so that the light emitting efficiency is improved, and the brightness is higher under the same current density.

Example three of visible light emitting device 40

In this example, the visible light emitting device 40 is a micro light emitting diode (Micro Light Emitting Diode, micro LED). In this case, the display panel 20 is a micro light emitting diode (Micro Light Emitting Diode, micro LED) display panel.

The micro LED includes, for example, an epitaxial layer, and an N electrode (cathode) and a P electrode (anode) provided on the epitaxial layer. The epitaxial layer includes, for example, an N-type doped phosphor layer, a P-type doped phosphor layer, and an active layer between the N-type doped phosphor layer and the P-type doped phosphor layer. A P-N junction is formed between the N-doped phosphor layer and the P-doped phosphor layer. The N-type doped phosphor layer is electrically connected to the N electrode, and the P-type doped phosphor layer is electrically connected to the P electrode. After a voltage is applied to the N electrode and the P electrode, electrons in the N-type doped phosphor layer are pushed to the P-type doped phosphor layer and are combined with holes in the P-type doped phosphor layer in the active layer, and energy is emitted in the form of photons, so that the micro LED emits light. Wherein. In the same first pixel 22, the active layers of the micro LEDs in different display sub-pixels 222 are of different materials, so that the micro LEDs in different display sub-pixels 222 emit different colors of visible light, such as red, green or blue light.

In addition, to enable the infrared sub-pixels 224 to emit infrared light, in some embodiments of the present application, the display panel 20 further includes a plurality of infrared emitters 50. Each infrared emitter 50 corresponds to one infrared subpixel 224, and each infrared emitter 50 is located within the infrared subpixel 224 to which the infrared emitter 50 corresponds.

The manner in which the infrared emitters 50 are disposed in the display panel 20 is exemplified below.

As shown in fig. 5, the infrared emitter 50 includes a P-type silicon substrate 51, a light emitting layer 52 on one surface of the P-type silicon substrate 51, a top electrode 53 on a side of the light emitting layer 52 away from the P-type silicon substrate 51, and a bottom electrode 54 electrically connected to the P-type silicon substrate 51.

The light emitting layer 52 comprises ytterbium doped silicon oxide. The infrared emitter 50 emits light in the infrared region under a dc bias (i.e., the top electrode 53 is connected to a negative voltage and the bottom electrode 54 is connected to a positive voltage). Specifically, in the electroluminescence spectrum of the infrared emitter 50, the infrared light region has a characteristic luminescence peak of ytterbium (wavelength of 983 nm).

In the infrared emitter 50, the silicon oxide easily forms oxygen vacancies in its lattice structure, and the intrinsic defect concentration is high, so that the injection and transport of carriers are easily realized, and the silicon oxide is a suitable ytterbium-doped base material. In addition, ytterbium-doped silicon oxide is an inorganic material, has stable physical and chemical properties, and does not have the common aging problem in organic materials when being used as an inorganic electroluminescent material. Moreover, in the infrared emitter 50, the substrate is a P-type silicon substrate, which is low in cost and can be integrated with other silicon-based devices (e.g., a low temperature polysilicon thin film transistor or a low temperature polycrystalline oxide thin film transistor, as described below). By forming ytterbium-doped silicon oxide on the P-type silicon substrate, the characteristic of high intrinsic defect concentration of the silicon oxide is utilized, so that energy level transition can be generated on an inner track sheet of ytterbium, and infrared light with characteristic wavelength of ytterbium is excited. Thus, the preparation of the silicon-based infrared emitter is realized.

In other embodiments of the present application, the light emitting layer 52 is not limited to include ytterbium doped silicon oxide, but may also be other ytterbium doped quasicrystal oxides. The quasi-crystal oxide has a three-dimensional rigid structure, and can provide a framework for ytterbium doping. For example, a material having a three-dimensional rigid structure is a material capable of providing a face-centered cubic structure of an regular octahedron or a regular tetrahedron. The quasi-crystal oxide comprises at least one of titanium dioxide and silicon oxide.

In some embodiments of the present application, to ensure proper operation of the device and to minimize operating voltage, the resistivity of the P-type silicon substrate 51 is 0.001 Ω·cm to 0.1 Ω·cm, so that it has high hole injection capability.

In some embodiments of the present application, the top electrode 53 is an N-type semiconductor layer, and the material thereof is at least one selected from N-type low temperature polysilicon (N-LTPS), indium Tin Oxide (ITO), indium Zinc Oxide (IZO), and indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO). To enhance the light emitting effect of the infrared emitter 50, the top electrode 53 is transparent or translucent and has a high infrared light transmittance, so as to avoid the top electrode 53 shielding the emitted infrared light and affecting the light emitting efficiency of the device, for example, ITO, IZO, IGZO.

The manner in which bottom electrode 54 is disposed in infrared emitter 50 is illustrated below.

An example of the arrangement of bottom electrode 54 in infrared emitter 50

As shown in fig. 6, the bottom electrode 54 is located on the surface of the P-type silicon substrate 51 remote from the light emitting layer 52.

In some embodiments, the material of the bottom electrode 54 is selected from at least one of molybdenum, titanium oxide. When the material of the bottom electrode 54 is selected from molybdenum, titanium, and other metals, the bottom electrode 54 of the metal material and the P-type silicon substrate 51 can form good ohmic contact. When the material of the bottom electrode 54 is titanium oxide, the titanium oxide has a better reflectivity to infrared light, and can reflect the infrared light incident thereon, so as to improve the light-emitting efficiency of the infrared light of the infrared emitter 50.

Example two of the arrangement of bottom electrode 54 in infrared emitter 50

As shown in fig. 7, the bottom electrode 54 is formed by conducting a partial P-type silicon substrate 51. Specifically, a large dose of boron or phosphorus (B/P) may be implanted into P-type silicon substrate 51 using Doping (Doping) to become a conductor to act as bottom electrode 54 of infrared emitter 50.

Fig. 8 is a schematic cross-sectional view of a display panel 20 according to some embodiments of the present application. In fig. 8, the visible light emitting device 40 is omitted.

As shown in fig. 8, to drive the visible light emitting device 40 to emit light, the display panel 20 further includes a thin film transistor (Thin Film Transistor, TFT) back plate 60. The TFT back plate 60 includes a substrate 61, a driving circuit layer 62 provided on the substrate 61, a pixel defining layer (Pixel Define Layer, PDL) 63 provided on a side of the driving circuit layer 62 remote from the substrate 61, and a support post 64 provided on the pixel defining layer 63.

The substrate 61 is used as a supporting substrate for supporting the driving circuit layer 62, the pixel defining layer 63, and other layers above it, and the material may be flexible materials such as polyethylene terephthalate (Polyethylene Terephthalate, PET) and Polyimide (PI).

The pixel defining layer 63 is provided with a plurality of openings 632 (one is exemplarily shown in fig. 8). Each opening 632 corresponds to one display sub-pixel 222 and one infrared sub-pixel 224, that is, each visible light emitting device 40 corresponds to one opening 632. Each infrared emitter 50 also corresponds to an opening 632. An opening 632 has a visible light emitting device 40 and an infrared emitter 50 therein.

The support posts 64 are disposed on the pixel defining layer 63, which may space the visible light emitting devices 40 in adjacent two different display sub-pixels 222 such that the emission colors of the respective visible light emitting devices 40 can be independent. In addition, when the visible light emitting device 40 is an OLED, by disposing the support posts 64 on the pixel defining layer 63, the vapor deposition mask plate used for vapor deposition of each functional layer of the OLED light emitting device can be effectively prevented from contacting the display panel 20 during the process of vapor deposition to form the OLED, so as to improve the product yield of the display panel 20.

The driving circuit layer 62 includes, for example, pixel driving circuits 620 (one is exemplarily shown in fig. 9) arranged in an array. Each pixel driving circuit 620 includes a plurality of TFTs and at least one capacitor C.

In some embodiments of the present application, as shown in fig. 9, the pixel driving circuit 620 has a structure of 2T1C, that is, includes two TFTs (a driving TFT T1 and a switching TFT T2) and one capacitor C. V (V) _DD Is responsible for continuously supplying a stable current to the visible light emitting device 40; v (V) _Data The TFT T2 is responsible for controlling the switch of the pixel; v due to the presence of capacitance C _Data The signal is stored, and the driving TFT T1 is kept on while the switching TFT T2 is turned off, controlling the current to stably light the visible light emitting device 40 in a desired manner. In addition, the pixel driving circuit 620 may further include a compensation circuit or the like.

In some embodiments of the present application, the pixel driving circuit 620 is a low temperature polysilicon (Low Temperature Poly Silicon, LTPS) driving circuit or a low temperature poly oxide (Low Temperature Polycrystalline Oxide, LTPO) driving circuit. In the LTPS driving circuit, the driving TFT T1 and the switching TFT T2 are LTPS-TFTs. In the LTPO driving circuit, oxide and polysilicon are selected as the active layer 622 material of the TFT device, for example, the driving TFT T1 is LTPS-TFT, and the switching TFT T2 is IGZO-TFT.

One driving TFT T1 and one switching TFT T2 are exemplarily shown in fig. 8. Each of the display sub-pixels 222 includes a visible light emitting device 40, and a driving TFT T1 and a switching TFT T2 electrically connected to the visible light emitting device 40. When the visible light emitting device 40 is an OELD, it is a top emission type light emitting device, and light emitted from the OELD is emitted to a side away from the substrate 61.

As shown in fig. 8, the driving TFT T1 includes a buffer layer (buffer) 621, an active layer 622, a gate insulating layer 623, a gate 624, an interlayer dielectric layer (Inner Layer Dielectric, ILD) 625, a source 626, a drain 627, and a Planarization (PLN) 628. The switching TFT T2 includes a buffer layer 621, an active layer 622, a first gate insulating layer 6231, second gate insulating layers 6232, 6231, bottom and top gate 6241, 6242, an interlayer dielectric layer 625, a source electrode (not shown), a drain electrode (not shown), and a planarization layer 628.

The respective layer structures of the driving TFT T1 and the switching TFT T2 are described in detail below.

The buffer layer 621 is disposed on the surface of the substrate 61 to prevent impurity ions from affecting the characteristics of the thin film transistor layer disposed on the substrate 61 and also to perform a further water-oxygen barrier function. The buffer layer 621 may be formed of a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, or a plurality of layers thereof.

The active layer 622 is located on the buffer layer 621 and is mainly formed of P-type polysilicon (P-Si). In fig. 8, P-Si in the middle of the active layer 622 of the driving TFT T1 is used to represent the semiconductor switch, and two portions on both sides of the P-Si are conductors to serve as conductors for connecting the source electrode 626 and the drain electrode 627 to the P-Si.

The gate insulating layer 623 covers the active layer 622 to function as insulating isolation between the active layer 622 and the gate 624. A gate 624 is located on the gate insulating layer 623 as a switch of the TFT device.

In fig. 8, the driving TFT T1 includes a gate electrode 624. The switching TFT T2 includes two gates 624, namely, a bottom gate 6241 and a top gate 6242. The gate insulating layer 623 includes a first gate insulating layer 6231 and a second gate insulating layer 6232. The first gate insulating layer 6231 covers the active layer 622 of the driving TFT T1 at a position corresponding to the driving TFT T1 and is located between the gate electrode 624 of the driving TFT T1 and the active layer 622 to insulate the active layer 622 and the gate electrode 624 of the driving TFT T1. The first gate insulating layer 6231 covers the active layer 622 of the switching TFT T2 at a position corresponding to the switching TFT T2 and is located between the bottom gate 6241 and the active layer 622 of the switching TFT T2, so as to insulate the active layer 622 and the gate 624 of the switching TFT T2. The second gate insulating layer 6232 covers the gate electrode 624 of the driving TFT T1 at a position corresponding to the driving TFT T1. The second gate insulating layer 6232 covers the bottom electrode of the switching TFT T2 at a position corresponding to the switching TFT T2 and is located between the bottom gate 6241 and the top gate 6242 of the switching TFT T2, so as to insulate the bottom gate 6241 and the top gate 6242 of the switching TFT T2. The material of the first gate insulating layer 6231 is silicon oxide. The material of the second gate insulating layer 6232 may be silicon oxide, silicon nitride, or a plurality of layers thereof.

An interlayer dielectric layer 625 covers the top gate 6242 and the second gate insulating layer 6232 and serves as an insulating layer between the source 626, drain 627 and gate 624.

A source electrode 626 is formed on the interlayer dielectric layer 625 and connected to the active layer 622. And a drain electrode 627 formed on the interlayer dielectric layer 625 and connected to the active layer 622. In fig. 8, the source electrode 626 and the drain electrode 627 of the driving TFT T1 are electrically connected to the active layer 622 through vias penetrating the first gate insulating layer 6231, the second gate insulating layer 6232 and the interlayer dielectric layer 625, respectively.

The planarization layer 628 covers the source electrode 626, the drain electrode 627, the interlayer dielectric layer 625, and the like, and serves to planarize, insulate, and protect the electrode on the substrate 61, and may be an organic material. In fig. 8, the planarization layer 628 is provided with a via hole 629, and the first electrode 48 of each of the visible light emitting devices 40 (e.g., an anode of an OLED or an anode of a micro LED) is electrically connected to the drain electrode 627 of one of the driving TFTs T1 located thereunder. To supply a voltage to the visible light emitting device 40 through the driving TFT T1, to control light emission of the visible light emitting device 40.

The structure of each layer of the infrared emitter 50 in the display panel 20 is described in detail below.

As shown in fig. 8, the infrared emitter 50 is integrated in the driving circuit layer 62 of the display panel 20. The infrared emitter 50 includes a P-type silicon substrate 51, a light emitting layer 52, a top electrode 53, and a bottom electrode 54.

The P-type silicon substrate 51 is located on the buffer layer 621. The active layer 622 in the driving circuit layer 62 is a P-type polysilicon layer. The portion of the P-type polysilicon layer within the display sub-pixel 222 forms the active layer 622 of the drive TFT T1 and the active layer 622 of the switch TFT T2, while the portion of the P-type polysilicon layer within the infrared sub-pixel 224 forms the P-type silicon substrate 51 of the infrared emitter 50.

The light emitting layer 52 is located on the P-type silicon substrate 51, and the light emitting layer 52 includes ytterbium-doped silicon oxide. The first gate insulating layer 6231 is silicon oxide, the portion of the silicon oxide located in the display sub-pixel 222 forms the first gate insulating layer 6231 of the driving TFT T1 and the first gate insulating layer 6231 of the switching TFT T2, and the portion of the silicon oxide located in the infrared sub-pixel 224 is ytterbium doped to form the light emitting layer 52 of the infrared emitter 50. In other embodiments of the present application, the light emitting layer 52 is not limited to include ytterbium doped silicon oxide, which is other quasicrystal type oxide that is ytterbium doped. The quasi-crystal oxide has a three-dimensional rigid structure, and can provide a framework for ytterbium doping. Specifically, the material having a stereorigid structure is a material capable of providing a face-centered cubic structure of a regular octahedron or a regular tetrahedron, such as titanium dioxide, silicon oxide. When the light emitting layer 52 includes ytterbium doped other quasicrystal oxide, the material of the first gate insulating layer 6231 may be the other quasicrystal oxide, the portion of the other quasicrystal oxide located in the display sub-pixel 222 forms the first gate insulating layer 6231 of the driving TFT T1 and the first gate insulating layer 6231 of the switching TFT T2, and the portion of the other quasicrystal oxide located in the infrared sub-pixel 224 is ytterbium doped to form the light emitting layer 52 of the infrared emitter 50. In addition, when the light-emitting layer 52 includes ytterbium doped other quasicrystal oxide, the material of the first gate insulating layer 6231 may still be silicon oxide, where the silicon oxide is located in the display sub-pixel 222 to form the first gate insulating layer 6231 of the driving TFT T1 and the first gate insulating layer 6231 of the switching TFT T2, and where the silicon oxide is located in the infrared sub-pixel 224 is removed by patterning (e.g. etching), and then the other ytterbium doped quasicrystal oxide is formed in this region to obtain the light-emitting layer 52 of the infrared emitter 50.

The top electrode 53 is located on the light emitting layer 52, which is an N-type semiconductor layer. The second gate insulating layer 6232 and the interlayer dielectric layer 625 have a via hole 629 formed in a region corresponding to the infrared sub-pixel 224, and the top electrode 53 fills the via hole 629 to be connected to the light emitting layer 52. The top electrode 53 is electrically connected to a chip (not shown) via leads 56. The lead 56 may be patterned from the same conductive layer as the source 626 and drain 627.

To avoid diffraction of the infrared light emitted from the infrared emitter 50 and the electrode of the visible light emitting device 40, the projection of the first electrode 48 of the visible light emitting device 40 in each display sub-pixel 222 on the substrate 61 is not overlapped with the projection of the top electrode 53 on the substrate 61 along the thickness direction of the substrate 61. That is, the infrared light emitted from the infrared emitter 50 is not substantially incident on the first electrode 48 of the visible light emitting device 40.

In some embodiments of the present application, bottom electrode 54 of infrared emitter 50 may be conductively doped by Doping (dopping) to implant a large dose of boron or phosphorus (B/P) into the P-type polysilicon layer, which becomes a conductor to act as bottom electrode 54 of infrared emitter 50. While the doping and conductor formation may be completed in the step of preparing the active layer 622 of the driving TFT T1 and/or the switching TFT T2. That is, when the P-type polysilicon layer in the display sub-pixel 222 is conductively formed to form the active layer 622 of the driving TFT T1 and/or the switching TFT T2, the P-type polysilicon layer in the infrared sub-pixel 224 is also conductively formed to form the bottom electrode 54 of the infrared emitter 50.

In other embodiments of the present application, bottom electrode 54 of infrared emitter 50 is located on the surface of P-type silicon substrate 51 that is remote from light emitting layer 52. Specifically, the buffer layer 621 includes a first buffer layer 6211 (the material may be silicon oxide) and a second buffer layer 6212 (the material may be silicon nitride) on the substrate 61. The TFT backplane 60 further includes a light blocking layer 55 between the first buffer layer 6211 and the second buffer layer 6212 to prevent external light from being irradiated onto the active layer 622 of the TFT (e.g., the driving TFT T1 and/or the switching TFT T2) from below the substrate 61 to cause a photo-generated carrier effect, so that the TFT operates stably. The material of the light blocking layer 55 may be selected from at least one of molybdenum, titanium, and titanium oxide. The bottom electrode 54 of the infrared emitter 50 may be formed using the light blocking layer 55 in the driving circuit layer 62. That is, by patterning the second buffer layer 6212 to have openings 6213 (as shown in fig. 6) at positions corresponding to the P-type silicon substrate 51 of the infrared emitter 50, the light blocking layer 55 fills the openings 6213 and extends to be in contact with the P-type silicon substrate 51 to serve as the bottom electrode 54 of the infrared emitter 50.

When the material of the light blocking layer 55 is selected from molybdenum, titanium, and the like, the bottom electrode 54 of the metal material can form good ohmic contact with the P-type silicon substrate 51. When the light blocking layer 55 is made of titanium oxide, the titanium oxide has a preferable reflectivity for infrared light, and can reflect infrared light incident thereon, thereby improving the light emitting efficiency of infrared light from the infrared emitter 50.

In summary, the infrared emitter 50 may be integrated in the driving circuit layer 62 of the display panel 20, and the preparation of the infrared emitter 50 is completed in the process of preparing the driving circuit layer 62 of the display sub-pixel 222 of the display panel 20. Specifically, the P-type silicon substrate 51 of the infrared emitter 50 is prepared using the P-type polysilicon layer of the active layer 622 for preparing the driving TFT T1 and/or the switching TFT T2; the light emitting layer 52 of the infrared emitter 50 is prepared by ytterbium-doping the gate insulating layer 623 of the driving TFT T1 and/or the switching TFT T2; lead 56 of top electrode 53 of infrared emitter 50 is prepared using the conductive layers of source 626 and drain 627 of preparation drive TFT T1 and/or switching TFT T2; the bottom electrode 54 of the infrared emitter 50 is prepared by using the light blocking layer 55 in the driving circuit layer 62, or the bottom electrode 54 of the infrared emitter 50 is prepared by using a step of doping and conducting the active layer 622 of the driving TFT T1 and/or the switching TFT T2. In this manner, fabrication of infrared emitter 50 compatible with silicon-based processes is achieved. Specifically, the infrared emitter 50 in the display panel 20 described above may be used for 3D depth scanning to enable biometric identification (e.g., face recognition).

As shown in fig. 10, to implement 3D depth scanning, the terminal 100 further includes an imaging sensor 71 and a controller 72. A plurality of infrared emitters 50 embedded in the display panel 20 constitute an infrared projector 70. The infrared emitter 50 is used for emitting infrared light to the object 80 to be measured, and the imaging sensor 71 is used for receiving the infrared light reflected back by the object 80 to be measured to obtain depth information of the object 80 to be measured.

In some embodiments of the present application, a Time of Flight (ToF) imaging technique may be employed for 3D depth scanning. In this case, the infrared projector 70, which is composed of a plurality of infrared sub-pixels 224, continuously transmits light pulses to the object 80 to be measured (e.g., a human face). The imaging sensor 71 receives light reflected back from the object 80 to be measured. The controller 72 calculates the flight (round trip) time of the light pulses to determine the distance of the object 80 to be measured for the purpose of 3D depth scanning.

In other embodiments of the present application, structured Light (SL) imaging techniques may be used for 3D depth scanning. In this case, the infrared projector 70 constituted by the plurality of infrared sub-pixels 224 projects structured light toward the surface of the object 80 to be measured (e.g., a human face). The imaging sensor 71 collects the structured light pattern reflected by the object 80 to be measured, and the controller 72 calculates depth information of the object 80 to be measured, so as to achieve the purpose of 3D depth scanning.

As shown in fig. 8 and 11, since the infrared emitter 50 is integrated in the display panel 20 and the projections of the first electrode 48 of the visible light emitting device 40 and the infrared emitter 50 in the thickness direction of the substrate 61 are completely non-overlapping, the infrared light L1 emitted from the infrared emitter 50 does not pass through the first electrode 48 of the visible light emitting device 40 when entering the object 80 to be measured. Thus, the problem of non-imaging due to optical diffraction with the first electrode 48 of the visible light emitting device 40 can be avoided. Moreover, by integrating the infrared emitter 50 into the display panel 20, the screen duty cycle of the front (display surface) of the display panel 20 is further increased, as compared to the way holes, drop screens, or Liu Haibing (Notch) are dug in the display panel 20, improving the effective readable area of the front of the terminal 100 (e.g., a cell phone), resulting in an immersive experience.

As shown in fig. 12, in the conventional terminal with a ToF transmitter, both an infrared transmitting end 2 and an infrared receiving end 3 of the ToF transmitter are located below a display screen 1. Namely, the infrared transmitting end 2 and the infrared receiving end 3 are both positioned at one side away from the display screen 1. When the infrared emitting end 2 projects infrared light toward the object 80 to be measured, the infrared light needs to pass through each film layer on the display panel 20 to reach the object 80 to be measured, that is, the infrared light emitted from the infrared emitting end 2 needs to pass through the display screen 1 twice completely to reach the infrared receiving end 3. As such, serious optical problems can result: firstly, as infrared light passes through each film layer of the display screen 1 twice, the light intensity reaching the infrared receiving end 3 is insufficient, and the imaging of the infrared receiving end 3 is blurred; and secondly, in the process that infrared light passes through each film layer of the display screen 1 twice, the infrared light inevitably passes through layers with patterns, such as metal wires and the like, on the display screen 1. And since the wavelength range of the infrared light is approximately 940nm-1000nm, the gap between the first electrodes (such as the anode of the OLED) of two adjacent visible light emitting devices is about 2 times. Therefore, in the manner that the infrared emitting end 2 and the infrared receiving end 3 are both positioned below the display screen 1, the infrared light at least inevitably generates multiple diffraction superposition with the electrode of the visible light emitting device, so that imaging cannot be performed. In addition, to achieve higher brightness, the instantaneous power of the ToF emitter is extremely high. In the embodiment of the application, ytterbium-doped silicon oxide is adopted as a high-power emission layer, and can be used as a high-power device. In addition, ytterbium-doped silicon oxide is an inorganic material, and has high power and no service life attenuation problem compared with an organic material.

Since silicon is an indirect forbidden band semiconductor, the recombination process is accompanied by phonon diffusion, and the luminous efficiency is low. The non-radiative recombination in silicon is mainly three: SRH (Shockley-Read-Hall) recombination, auger recombination, and free carrier absorption. SRH recombination refers to the non-radiative recombination of electron-hole pairs at deep energy levels in the forbidden band, which are typically introduced by metallic impurities or defects. Auger recombination is a non-radiative recombination process involving three particles, where some electrons and holes recombine to release energy that is absorbed and excited by nearby third carriers to a higher energy state than before. Auger recombination is more pronounced when the carrier concentration is higher. Free carrier absorption is also a non-radiative recombination process, which is severe in heavily doped silicon. At room temperature, the band-edge radiation recombination lifetime in silicon is in the order of milliseconds, the SRH recombination lifetime and the Auger recombination lifetime are in the order of seconds, and the radiation recombination lifetime is far longer than the non-radiation recombination lifetime, so that the radiation recombination efficiency is far lower than the non-radiation recombination, and the luminous internal quantum efficiency of silicon is very low.

The above-mentioned infrared emitter 50 utilizes the characteristic that the silicon oxide easily forms oxygen vacancies in its lattice structure and has higher intrinsic defect concentration by doping ytterbium into the silicon oxide, so that the energy level transition of the inner orbital sheet of ytterbium can be generated, and further infrared light with characteristic wavelength of ytterbium is excited, thereby realizing the preparation of the silicon-based infrared emitter. Moreover, the infrared emitter 50 is integrated in the display panel 20, and does not overlap with the orthographic projection of the first electrode 48 of the visible light emitting device 40 on the substrate 61, so that the light loss of the infrared emitter 50 is reduced and the utilization rate of infrared light is effectively improved, compared with the mode that the infrared emitter is arranged below the display panel, and thus, the problem of the luminous efficiency of the silicon-based infrared emitter can be solved, and the intensity of infrared light received by the imaging sensor 71 is improved.

It should be noted that, in some embodiments of the present application, the display panel 20 further includes a plurality of second pixels (not shown) for displaying. The second pixel includes at least one display sub-pixel 222 therein, but does not include an infrared sub-pixel 224. Also, the number of display sub-pixels 222 in the second pixel is the same as the number of display sub-pixels 222 in the first pixel 22. For example, the first pixel 22 includes three display sub-pixels 222 for respectively emitting red, blue, and green light, and the second pixel also includes three display sub-pixels 222 for respectively emitting red, blue, and green light. That is, infrared emitters 50 are distributed only in a partial area in the display area, so that the effect of infrared subpixels 224 on the resolution of display panel 20 can be reduced.

In other embodiments of the present application, only the first pixels 22 described above are disposed in the entire display area of the display panel 20. That is, the infrared emitter 50 is disposed in each pixel of the display panel 20, so that more infrared light is projected to the object 80 (e.g., human face) to be measured, thereby achieving the purpose of improving the 3D depth scanning accuracy.

It should be noted that, the above-mentioned infrared emitter 50 may be used as a light source or a photosensitive signal detecting element, and may be applied in the fields of illumination, photoelectric detection, etc., instead of being integrated in a display panel.

Some embodiments of the present application also provide methods of making the above-described infrared emitters. The sequence of steps of the preparation method can be changed according to different requirements, and certain steps can be omitted or combined.

As shown in fig. 13, the method for manufacturing the infrared emitter includes the following steps.

Step S11: a quasi-crystalline oxide layer is formed on a P-type silicon substrate.

Step S12: ytterbium doping treatment is carried out on the alignment crystal form oxide layer.

Step S13: a top electrode is formed.

Step S14: a bottom electrode is formed.

The respective steps are specifically described below.

In step S11, the P-type silicon substrate may be low-temperature polysilicon. In order to ensure the normal operation of the device and reduce the operating voltage as much as possible, the resistivity of the P-type silicon substrate is 0.001 to 0.1 ohm cm, so that the P-type silicon substrate has high hole injection capability. In addition, in step S11, the silicon oxide layer may be formed by magnetron sputtering, laser pulse deposition, chemical vapor deposition, or the like.

In one embodiment, the quasicrystal form oxide layer is a silicon oxide layer. A silicon oxide layer is formed by chemical vapor deposition and annealed at 450 ℃ for 60min under an oxygen atmosphere. The oxidation degree of the silicon oxide layer can be better by adopting an oxygen atmosphere, and the crystallinity of the obtained silicon oxide layer film layer can be better by selecting 450 ℃ for annealing.

In step S12, ytterbium is implanted into the silicon oxide layer by ion implantation to obtain ytterbium-doped silicon oxide, thereby forming a light-emitting layer.

In step S13, an N-type semiconductor may be deposited on the ytterbium-doped silicon oxide. The N-type semiconductor is, for example, N-LTPS, IGZO, ITO, IZO, which serves as the top electrode.

In some embodiments of the present application, the bottom electrode formed in step S14 is located on a surface of the P-type silicon substrate remote from the light emitting layer, which may be formed by forming a conductive material on the surface of the P-type silicon substrate remote from the light emitting layer. The conductive material is, for example, at least one selected from molybdenum, titanium, and titanium oxide. The conductive material acts as a bottom electrode.

In other embodiments of the present application, the bottom electrode formed in step S14 is formed by conducting a portion of the P-type silicon substrate. The conductive step may be to implant a large dose of boron/phosphorus (B/P) into a portion of the P-type silicon substrate to partially dope it into a conductor to act as a top electrode.

In other embodiments of the present application, ytterbium doped silicon oxide may be replaced with other materials having a stereorigid structure. For example, a material having a three-dimensional rigid structure is a material capable of providing a face-centered cubic structure of an regular octahedron or a regular tetrahedron.

Some embodiments of the present application also provide a method for manufacturing the display panel. The sequence of steps of the preparation method can be changed according to different requirements, and certain steps can be omitted or combined. The preparation method can finish the preparation of the infrared emitter in the process of preparing the driving circuit layer of the visible light emitting device of the display panel. The driving circuit layer may be an LTPS driving circuit or an LTPO driving circuit. The preparation process of the LTPS driving circuit or the LTPO driving circuit is mature and will not be described again.

As shown in fig. 14, the manufacturing method of the display panel includes the following steps.

Step S21: the same P-type polysilicon layer is used to prepare the active layer of the driving TFT and the P-type silicon substrate of the infrared emitter.

Step S22: a gate insulating layer of a driving TFT and a light emitting layer of an infrared emitter are prepared.

Step S23: a top electrode of the infrared emitter is prepared.

Step S24: a bottom electrode of an infrared emitter is prepared.

The respective steps are specifically described below.

In step S21, patterning is performed on the same P-type polysilicon layer, so that the portion of the P-type polysilicon layer located in the display sub-pixel forms an active layer of the driving TFT, and the portion of the P-type polysilicon layer located in the infrared sub-pixel forms a P-type silicon substrate of the infrared emitter. In the step of patterning the same P-type polysilicon layer, the active layers of the switching TFTs may be formed simultaneously.

In some embodiments of the present application, in step S22, the gate insulating layer of the driving TFT and the light emitting layer of the infrared emitter are prepared using the same quasicrystal type oxide layer. The same quasicrystal form oxide layer may be a silicon oxide layer. The silicon oxide layer covers the P-type polysilicon layer. The silicon oxide layer is patterned to form a gate insulating layer of a portion of the driving TFT and a gate insulating layer of the switching TFT within the display sub-pixel. And the part of the silicon oxide layer, which is positioned in the infrared sub-pixel, forms a light-emitting layer of the infrared emitter by ytterbium-doped treatment on the silicon oxide layer. In other embodiments of the present application, ytterbium doped silicon oxide may be replaced with other materials having a stereorigid structure. For example, a material having a three-dimensional rigid structure is a material capable of providing a face-centered cubic structure of an regular octahedron or a regular tetrahedron.

In other embodiments of the present application, in step S22, the gate insulating layer of the driving TFT and the quasicrystal form oxide layer that prepares the light emitting layer of the infrared emitter are of different materials. For example, the gate insulating layer of the driving TFT is silicon oxide, and the light emitting layer of the infrared emitter is ytterbium-doped titanium oxide. In this case, in step S22, patterning is performed on the silicon oxide layer, so that the silicon oxide layer is located on the gate insulating layer of the partial driving TFT and the gate insulating layer of the switching TFT in the display sub-pixel, and the portion corresponding to the infrared sub-pixel is removed, and ytterbium doped titanium dioxide is formed in this region, to obtain the light emitting layer of the infrared emitter.

In step S23, before forming the top electrode, a gate electrode of the driving TFT and/or the switching TFT and an interlayer dielectric layer are further formed, the gate electrode is located on the gate insulating layer, the interlayer dielectric layer covers the gate electrode, and a through hole is formed in a region of the interlayer dielectric layer corresponding to the infrared sub-pixel. The top electrode of the infrared emitter is positioned on one side of the light-emitting layer far away from the P-type silicon substrate, and is filled with a through hole so as to be electrically connected with the light-emitting layer.

In step S23, after the formation of the top electrode, a source electrode, a drain electrode of the driving TFT, and a wiring connecting the top electrode of the infrared emitter are also prepared using the same conductive layer. Specifically, the same conductive layer may be patterned to form source and drain electrodes of the driving TFT and/or the switching TFT, and a lead connecting the top electrode of the infrared emitter, the source and drain electrodes being electrically connected to the active layer through a via hole penetrating the interlayer dielectric layer and the gate insulating layer. The leads are used for electrically connecting the infrared emitter to a chip.

In some embodiments of the present application, in step S24, the bottom electrode is located on a surface of the P-type silicon substrate remote from the light emitting layer. Specifically, the bottom electrode of the infrared emitter may be prepared using a conductive light blocking layer between the P-type polysilicon layer and the substrate. Before forming the P-type polysilicon layer on the substrate, the method further comprises sequentially forming a first buffer layer (made of silicon oxide, for example), a light blocking layer and a second buffer layer (made of silicon nitride, for example) on the substrate. The light blocking layer is used for preventing external light from being irradiated onto an active layer of a TFT (such as a driving TFT or a switching TFT) from below the substrate to cause a photo-generated carrier effect, so that the TFT works stably. The second buffer layer is patterned to open holes at positions corresponding to the P-type silicon substrate of the infrared emitter (as shown in fig. 6), and the light blocking layer fills the open holes and extends to contact the P-type silicon substrate to serve as a bottom electrode of the infrared emitter. When the light blocking layer is made of molybdenum, titanium and other metals, the bottom electrode of the metal material and the P-type silicon substrate can form good ohmic contact. When the light blocking layer is made of titanium oxide, the titanium oxide has better reflectivity to infrared light, so that the infrared light incident on the light blocking layer can be reflected, and the light emitting efficiency of the infrared light of the infrared emitter is improved.

In other embodiments of the present application, a portion of the P-type silicon substrate is subjected to a conductive process to form a bottom electrode. Wherein the bottom electrode of the infrared emitter can be prepared by doping and conducting the P-type polysilicon layer to prepare the active layer of the driving TFT and/or the switching TFT. That is, when the P-type polysilicon layer in the display sub-pixel is electrically conductive to form the active layer of the driving TFT and/or the switching TFT, the P-type polysilicon layer in the infrared sub-pixel is also electrically conductive to form the bottom electrode of the infrared emitter.

In summary, the infrared emitter may be integrated in the driving circuit layer of the display panel, and the preparation of the infrared emitter is completed in the process of preparing the driving circuit layer of the display sub-pixel of the display panel. Specifically, a P-type silicon substrate of an infrared emitter may be prepared by using a P-type polysilicon layer that prepares an active layer of a driving TFT and/or a switching TFT; preparing a light-emitting layer of the infrared emitter by performing ytterbium doping treatment on the gate insulating layer of the driving TFT and/or the switching TFT; preparing a lead of a top electrode of the infrared emitter by using the conductive layers for preparing a source electrode and a drain electrode of the driving TFT and/or the switching TFT; the bottom electrode of the infrared emitter is prepared by using the light blocking layer in the driving circuit layer, or by using the step of doping and conducting the active layer of the driving TFT and/or the switching TFT. In this way, the fabrication of infrared emitters compatible with silicon-based processes is achieved.

The above embodiments are only for illustrating the technical solution of the present application and not for limiting, and although the present application has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solution of the present application may be modified or equivalently replaced without departing from the spirit and essence of the technical solution of the present application.

Claims

1. A display panel comprising a plurality of first pixels, each of said first pixels comprising at least one display sub-pixel for emitting visible light and at least one infrared sub-pixel for emitting infrared light;

each display sub-pixel comprises a visible light emitting device and a driving TFT electrically connected with the visible light emitting device;

each infrared subpixel comprises an infrared emitter, wherein the infrared emitter comprises a P-type silicon substrate, a light emitting layer positioned on one surface of the P-type silicon substrate, a top electrode positioned on one side of the light emitting layer away from the P-type silicon substrate, and a bottom electrode electrically connected with the P-type silicon substrate; the light-emitting layer is a ytterbium-doped silicon oxide layer;

the display panel comprises a substrate, a P-type polycrystalline silicon layer positioned on the substrate and a silicon oxide layer covering the P-type polycrystalline silicon layer;

A portion of the P-type polysilicon layer located within the display sub-pixel forms an active layer of the driving TFT, and a portion of the P-type polysilicon layer located within the infrared sub-pixel forms the P-type silicon substrate of the infrared emitter; a part of the silicon oxide layer positioned in the display sub-pixel forms a gate insulating layer of the driving TFT, and a part of the silicon oxide layer positioned in the infrared sub-pixel forms the light emitting layer after ytterbium-doped treatment;

the display panel further comprises a conductive layer positioned between the substrate and the P-type polycrystalline silicon layer, wherein the material of the conductive layer is at least one of molybdenum, titanium and titanium oxide; a part of the conductive layer located in the display sub-pixel forms a light blocking layer, and the light blocking layer is located on one side of the active layer away from the gate insulating layer; a portion of the conductive layer located within the infrared subpixel forms the bottom electrode in contact with a surface of the P-type silicon substrate remote from the light emitting layer;

alternatively, the P-type polysilicon layer in the display sub-pixel is also conductively formed to form the bottom electrode when the P-type polysilicon layer in the infrared sub-pixel is conductively formed to form the active layer.

2. The display panel of claim 1, wherein the P-type silicon substrate has a resistivity of 0.001 Ω -cm to 0.1 Ω -cm.

3. The display panel of claim 1, wherein the top electrode material is selected from at least one of N-type low temperature polysilicon, indium tin oxide, indium zinc oxide, indium gallium zinc oxide.

4. A display panel according to any one of claims 1 to 3, wherein the visible light emitting device comprises a first electrode electrically connected to the driving TFT;

the projection of the first electrode on the substrate is not overlapped with the projection of the top electrode on the substrate along the thickness direction of the substrate.

5. A display panel according to any one of claims 1 to 3, wherein the driving TFT further comprises:

a gate electrode on the gate insulating layer;

an interlayer dielectric layer covering the grid electrode; and

and the interlayer dielectric layer is provided with a through hole in a region corresponding to the infrared sub-pixel, and the top electrode fills the through hole to be connected with the light-emitting layer.

6. The display panel of claim 5, wherein the top electrode is electrically connected to a chip via leads;

wherein the lead, the source electrode and the drain electrode are formed by patterning the same conductive layer.

7. The display panel according to any one of claims 1 to 3, 6, wherein the visible light emitting device is an organic light emitting diode or a micro-inorganic light emitting diode.

8. The display panel of claim 7, further comprising a plurality of second pixels, each of the second pixels including at least one of the display sub-pixels but not the infrared sub-pixels, and a number of the display sub-pixels in the second pixels being the same as a number of the display sub-pixels in the first pixels.

9. A terminal comprising the display panel according to any one of claims 1 to 8.

10. The terminal of claim 9, further comprising an imaging sensor for emitting infrared light toward an object to be measured, the imaging sensor for receiving infrared light reflected back by the object to be measured to obtain depth information of the object to be measured.

11. A method for manufacturing a display panel, wherein the display panel comprises a plurality of first pixels, each of which comprises at least one display sub-pixel for emitting visible light and at least one infrared sub-pixel for emitting infrared light; each display sub-pixel comprises a visible light emitting device and a driving TFT electrically connected with the visible light emitting device; each of the infrared subpixels includes an infrared emitter, the infrared emitter including:

a P-type silicon substrate;

the light-emitting layer is positioned on one surface of the P-type silicon substrate;

a bottom electrode electrically connected to the P-type silicon substrate;

wherein the light-emitting layer is a ytterbium-doped silicon oxide layer;

the preparation method comprises the following steps:

preparing an active layer of the driving TFT and the P-type silicon substrate of the infrared emitter by using the same P-type polysilicon layer;

preparing a gate insulating layer of the driving TFT and the light emitting layer of the infrared emitter using the same silicon oxide layer;

preparing the top electrode of the infrared emitter; and

preparing the bottom electrode of the infrared emitter;

Wherein preparing the gate insulating layer of the driving TFT and the light emitting layer of the infrared emitter using the same silicon oxide layer includes:

patterning the silicon oxide layer to form a gate insulating layer of the driving TFT at a portion of the silicon oxide layer located within the display sub-pixel; and

annealing the silicon oxide layer in an oxygen atmosphere, and performing ytterbium doping treatment on the annealed silicon oxide layer to enable the part of the silicon oxide layer, which is positioned in the infrared sub-pixel, to form the light-emitting layer after the ytterbium doping treatment;

the step of preparing the bottom electrode includes: patterning the same conductive layer, wherein the material of the conductive layer is at least one selected from molybdenum, titanium and titanium oxide, so that a light blocking layer is formed on the portion of the conductive layer positioned in the display sub-pixel, and the bottom electrode is formed on the portion of the conductive layer positioned in the infrared sub-pixel; the light blocking layer is positioned on one side of the active layer, which is far away from the gate insulating layer, and the bottom electrode is in contact with the surface of the P-type silicon substrate, which is far away from the light emitting layer;

alternatively, the step of preparing the bottom electrode includes: the P-type polysilicon layer in the infrared sub-pixel is also conductively formed to form the bottom electrode while the P-type polysilicon layer in the display sub-pixel is being conductive to form the active layer.

12. The method of manufacturing a display panel according to claim 11, further comprising forming a gate electrode, an interlayer dielectric layer, a source electrode, and a drain electrode of the driving TFT before manufacturing the top electrode;

the grid electrode is positioned on the grid electrode insulating layer, the interlayer dielectric layer covers the grid electrode, the source electrode and the drain electrode are electrically connected with the active layer, and a through hole is formed in the interlayer dielectric layer corresponding to the region of the infrared sub-pixel; the top electrode fills the via hole to be electrically connected with the light emitting layer.