CN114464631A - Array substrate and display panel - Google Patents

Array substrate and display panel Download PDF

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Publication number
CN114464631A
CN114464631A CN202210137156.9A CN202210137156A CN114464631A CN 114464631 A CN114464631 A CN 114464631A CN 202210137156 A CN202210137156 A CN 202210137156A CN 114464631 A CN114464631 A CN 114464631A
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channel
array substrate
substrate
narrow
active layer
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戴星强
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Guangzhou China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Guangzhou China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

The application discloses an array substrate and a display panel, wherein the array substrate comprises a substrate and an active layer arranged on the substrate, the active layer comprises a channel part and conductive parts arranged on two sides of the channel part, and the mass ratio of narrow-bandgap elements in the channel part is smaller than that of the narrow-bandgap elements in the conductive parts; according to the thin film transistor, the proportion of narrow forbidden band elements in a channel part in an active layer is reduced, the proportion of oxidized narrow forbidden bands in the channel part is reduced, the proportion of oxides formed by the wide forbidden band elements in the channel part is improved, the electron mobility of the active layer is improved, and the stability of the thin film transistor is further ensured.

Description

Array substrate and display panel
Technical Field
The application relates to the technical field of display, in particular to an array substrate and a display panel.
Background
The material of the active layer in the conventional thin film transistor generally includes amorphous silicon, low temperature polysilicon, and oxide. Oxide TFTs are widely used in display industry TFT devices due to their lower leakage current and better mobility.
In the existing oxide TFT, under long-time illumination conditions, the electron mobility of the channel portion is affected, so that the performance of the TFT device is shifted, and the stability of the thin film transistor is further reduced.
Disclosure of Invention
The application provides an array substrate and a display panel, which aim to solve the technical problem of performance drift of the existing oxide TFT.
In order to solve the above-mentioned scheme, the technical scheme that this application provides is as follows:
the application provides an array substrate, it includes:
a substrate;
the active layer is arranged on the substrate and comprises a channel part and conductive parts arranged on two sides of the channel part;
wherein the mass ratio of the narrow-band gap element in the channel portion is smaller than the mass ratio of the narrow-band gap element in the conductive portion.
In the array substrate of the present application, the channel portion includes a first channel close to a side of the substrate and a second channel far from the side of the substrate, and a mass ratio of a narrow-bandgap element in the first channel is greater than a mass ratio of a narrow-bandgap element in the second channel.
In the array substrate of the present application, the mass fraction of the narrow bandgap element in the channel portion is gradually decreased in a direction from the substrate to the active layer.
In the array substrate of the present application, a mass ratio of the narrow-bandgap element in the first channel portion is the same as a mass ratio of the narrow-bandgap element in the conductive portion.
In the array substrate of the present application, in a direction from the substrate to the active layer, a thickness of the channel portion is smaller than a thickness of the conductive portion.
In the array substrate of the present application, a difference in thickness between the conductive portion and the channel portion ranges from 200 angstroms to 300 angstroms.
In the array substrate of the present application, the array substrate further includes a gate layer disposed between the active layer and the substrate;
in a top view direction of the array substrate, an orthographic projection of the channel portion on the gate layer is located in the gate layer.
In the array substrate, the array substrate comprises a source drain layer arranged on the active layer, and the source drain layer comprises a source electrode and a drain electrode;
wherein, in a top view direction of the array substrate, orthographic projections of the source electrode and the drain electrode on the conductive part are positioned in the conductive part, and the source electrode and the drain electrode are in contact with the conductive part.
In the array substrate, the doped element types in the first channel and the second channel are different; the second channel includes elemental fluorine.
The application also provides a display panel, the display panel includes above-mentioned array substrate and is located the luminous component of array substrate one side, the array substrate with luminous component combines as an organic wholely.
Has the advantages that: the application discloses an array substrate and a display panel, wherein the array substrate comprises a substrate and an active layer arranged on the substrate, the active layer comprises a channel part and conductive parts arranged on two sides of the channel part, and the mass ratio of narrow-forbidden band elements in the channel part is smaller than that of the narrow-forbidden band elements in the conductive parts; according to the thin film transistor, the proportion of narrow forbidden band elements in a channel part in an active layer is reduced, the proportion of oxidized narrow forbidden bands in the channel part is reduced, the proportion of oxides formed by the wide forbidden band elements in the channel part is improved, the electron mobility of the active layer is improved, and the stability of the thin film transistor is further ensured.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
FIG. 1 is a cross-sectional view of an array substrate of the present application;
fig. 2 is a graph of Vgs and Ids of a conventional array substrate;
fig. 3 is a graph of Vgs and Ids of the array substrate of the present application;
FIG. 4 is a diagram illustrating a method of fabricating an array substrate according to the present application;
fig. 5A to 5H are process steps of the array substrate of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the existing oxide TFT, under long-time illumination conditions, the electron mobility of the channel portion is affected, so that the performance of the TFT device is shifted, and the stability of the thin film transistor is further reduced. The present application provides an array substrate to solve the above technical problems.
Referring to fig. 1, the present application provides an array substrate 100, which includes a substrate 10 and an active layer 40 disposed on the substrate 10, wherein the active layer 40 may include a channel portion 410 and conductive portions 420 disposed on two sides of the channel portion 410.
In this embodiment, the mass ratio of the narrow gap element in the channel portion 410 may be smaller than the mass ratio of the narrow gap element in the conductive portion 420.
In the present embodiment, the oxide formed by combining the narrow band gap element with oxygen belongs to a narrow band gap oxide, which has poor stability and is liable to cause the performance of the thin film transistor 210 to drift under a working environment of long-time illumination or abnormal temperature, but the present application improves the electron mobility of the active layer 40 by reducing the proportion of the narrow band gap element in the channel portion 410 in the active layer 40, reducing the proportion of the oxidized narrow band gap in the channel portion 410, and improving the proportion of the oxide formed by the wide band gap element in the channel portion 410, thereby ensuring the stability of the thin film transistor 210.
The technical solution of the present application will now be described with reference to specific embodiments.
Referring to fig. 1, the array substrate 100 may include a substrate 10 and a driving circuit layer 200 disposed on the substrate 10, the driving circuit layer 200 may include a plurality of thin film transistors 210, and the thin film transistors 210 may be of an etch-barrier type, a back channel etch type, or a structure divided into a bottom gate thin film transistor, a top gate thin film transistor, and the like according to the positions of a gate and an active layer 40, which is not limited in particular.
In this embodiment, the material of the substrate 10 may be glass, quartz, or polyimide.
In this embodiment, as shown in fig. 1, taking a back channel etching thin film transistor as an example, the thin film transistor 210 may include a gate electrode layer 20 disposed on the substrate 10, a gate insulating layer 30 disposed on the gate electrode layer 20, an active layer 40 disposed on the gate insulating layer 30, a source drain electrode layer 50 disposed on the active layer 40, a passivation layer 60 disposed on the source drain electrode layer 50, and a common electrode layer 70 disposed on the passivation layer 60.
In the present embodiment, the material of the active layer 40 may be a metal oxide, such as Ln-IZO, ITZO, ITGZO, HIZO, IZO (InZnO), ZnO: F, In2O3:Sn、In2O3:Mo、Cd2SnO4、ZnO:Al、TiO2Nb, Cd-Sn-O or other metal oxides, the following examples of this application are illustrated by taking IGZO as an example.
In the conventional display panel, the channel portion 410 of the thin film transistor 210 is under the action of light irradiation, which causes the mobility in the active layer 40 to be affected, and further causes the performance of the thin film transistor 210 to have a certain drift, specifically, referring to the curves shown in fig. 2, different curves represent graphs of Vgs and Ids in the thin film transistor 210 under different light irradiation durations, and as the light irradiation duration increases, the curves of Vgs and Ids shift to the left, that is, the performance curve of the thin film transistor 210 shifts along with the light irradiation duration, which results in poor stability of the thin film transistor 210.
In the array substrate 100 of the present application, the channel portion 410 includes a first channel 411 close to the substrate 10 and a second channel 412 far from the substrate 10, and a mass ratio of a narrow-bandgap element in the first channel 411 is greater than a mass ratio of a narrow-bandgap element in the second channel 412.
In this embodiment, since the oxide doped in the channel portion 410 is composed of an oxide composed of a narrow bandgap element and a wide bandgap element, and the second channel 412 is disposed near the light emitting side, the first channel 411 is located between the substrate 10 and the second channel 412, and when external light enters the display panel, only the second channel 412 is irradiated, and since the mass of the narrow bandgap element in the second channel 412 is small, the oxide in the second channel 412 is mainly composed of a wide bandgap metal oxide, the influence of light on the second channel 412 is small under long-time lighting conditions; the first channel 411 is blocked by the second channel 412, so that the first channel 411 is less affected by light, i.e. the stability of the device of the thin film transistor 210 is ensured.
In this embodiment, please refer to the curves shown in fig. 3, where different curves represent graphs of Vgs and Ids of the thin film transistor 210 under different illumination durations, and as the illumination duration increases, the curves of Vgs and Ids are distributed more intensively than the curves in fig. 2, that is, the performance curve of the thin film transistor 210 has a smaller offset with the illumination duration, so as to improve the stability of the thin film transistor 210.
In this embodiment, taking IGZO as an example, the indium element is a narrow bandgap element, and the gallium element and the zinc element are wide bandgap elements, so that the mass ratio of the indium element in the second channel 412 needs to be reduced.
In this embodiment, an acid solution carrying fluorine-containing ions is generally used to act on the channel portion 410 to precipitate the indium element in the second channel 412, so as to improve the mass ratio of the oxides corresponding to the zinc element and the gallium element in the second channel 412, that is, to reduce the ratio of the narrow-bandgap indium oxide in the second channel 412 and improve the ratio of the wide-bandgap zinc oxide to the gallium oxide.
In this embodiment, the mass concentration of the fluoride ion in the fluoride ion-containing acid solution may be 0.01% to 4%.
In the array substrate 100 of the present application, referring to fig. 1, in a direction from the substrate 10 to the active layer 40, a mass ratio of the narrow band gap element in the channel portion 410 is gradually decreased.
In this embodiment, when the external light irradiates the channel portion 410, the light intensity received by the channel portion 410 closer to the light-emitting side of the display panel is larger, and the light intensity received by the channel portion 410 farther from the light-emitting side of the display panel is smaller, so that according to the different illumination intensities received by different positions in the channel portion 410, the mass ratio of the narrow bandgap elements in the channel portion 410 is set in a gradient manner, and the closer to the light-emitting side of the display panel, the smaller the mass ratio of the narrow bandgap elements in the channel portion 410 is, thereby improving the stability of the thin film transistor 210 under the illumination condition.
In the array substrate 100 of the present application, referring to fig. 1, the mass ratio of the narrow-bandgap element in the first channel 411 portion 410 is the same as the mass ratio of the narrow-bandgap element in the conductive portion 420.
In this embodiment, taking IGZO as an example, the conductive portions 420 located at two sides of the channel portion 410 are mainly composed of indium oxide, gallium oxide and zinc oxide, and the indium element in the second channel 412 in the channel portion 410 is precipitated, but the indium element in the first channel 411 close to the substrate 10 side is not precipitated, so the mass ratio of the indium element in the first channel 411 is the same as the mass ratio of the indium element in the conductive portions 420, that is, the channel portion 410 is composed of the second channel 412 including a wide bandgap oxide and the first channel 411 including a wide and narrow bandgap oxides, the second channel 412 in the upper layer has higher optical stability, the first channel 411 in the lower layer has higher electron mobility, and the combined action of the two has higher electron mobility under the condition of ensuring the stability of the thin film transistor 210.
In the array substrate 100 of the present application, referring to fig. 1, in a direction from the substrate 10 to the active layer 40, the thickness of the channel portion 410 is smaller than that of the conductive portion 420.
In the present embodiment, since the narrow forbidden band element in the channel portion 410 is precipitated by the acid solution containing the fluorine ions, and the acid solution also has a certain etching effect on the channel portion 410, the thickness of the channel portion 410 is smaller than that of the conductive portion 420.
In the present embodiment, since the channel portion 410 serves as a channel for conducting the two-sided conductive portions 420, when the thickness of the channel portion 410 is too small, the sectional area of the channel is reduced, thereby affecting the electron mobility of the active layer 40. Accordingly, the difference in thickness between the conductive portion 420 and the channel portion 410 may range from 200 angstroms to 300 angstroms.
In the present embodiment, since the narrow bandgap element in the channel portion 410 can be deposited by the acid solution containing the fluorine ions, when the fluorine ions react with the material in the channel portion 410, the fluorine ions may remain in the channel portion 410. Since the acid solution containing fluorine ions is only in contact with the surface of the channel portion 410, the fluorine ions are doped in the second channel 412, that is, the species of the elements doped in the first channel 411 and the second channel 412 are different, and the second channel 412 includes fluorine.
In the array substrate 100 of the present application, referring to fig. 1, the array substrate 100 further includes a gate layer 20 disposed between the active layer 40 and the substrate 10; in a top view direction of the array substrate 100, an orthogonal projection of the channel portion 410 on the gate layer 20 is located in the gate layer 20.
In this embodiment, the gate layer 20 may be used as a light shielding member of the channel portion 410, in addition to the switch for conducting the conductive portion 420. External light may also enter the panel through the substrate 10 side and irradiate the first trench 411, so that the area of the gate layer 20 may be larger than that of the trench portion 410 in order to prevent external light from irradiating the first trench 411.
In this embodiment, the material of the gate layer 20 may include metals or alloys of Cr, W, Ti, Ta, Mo, Al, Cu, and the like.
In this embodiment, the common electrode layer 70 may be transparent indium tin oxide or other transparent metal material.
In the array substrate 100 of the present application, referring to fig. 1, the array substrate 100 includes a source drain layer 50 disposed on the active layer 40, and the source drain layer 50 includes a source and a drain; in the top view direction of the array substrate 100, orthographic projections of the source electrode and the drain electrode on the conductive portion 420 are located in the conductive portion 420, and the source electrode and the drain electrode are in contact with the conductive portion 420.
In this embodiment, the material of the source/drain layer 50 may include metals or alloys such as Cr, W, Ti, Ta, Mo, Al, and Cu.
In the present embodiment, the material of the gate insulating layer 30 and the passivation layer 60 may include a compound of nitrogen, silicon, and oxygen.
The present application also provides a display panel, which includes the above array substrate 100 and a light emitting component located at one side of the array substrate 100, and the array substrate 100 and the light emitting component are combined into a whole.
For example, when the display panel is a liquid crystal display panel, the light emitting member may be a backlight module; and when the display panel is a self-luminous display panel, the light emitting member may be an organic light emitting device or a Micro-LED, and the present application is not particularly limited.
Referring to fig. 4, the present application further provides a method for manufacturing a display panel, including:
s10, providing a substrate 10;
referring to fig. 5A, the material of the substrate 10 may be glass, quartz, or polyimide.
S20, forming a gate layer 20 on the substrate 10;
referring to fig. 5B, a first metal layer is first formed on the substrate 10, and patterned to form a gate layer 20, wherein the material of the gate layer 20 may include Cr, W, Ti, Ta, Mo, Al, Cu, and other metals or alloys.
S30, forming a gate insulating layer 30 on the gate layer 20;
referring to fig. 5C, the material of the gate insulating layer 30 may include a compound of nitrogen, silicon and oxygen, and the gate insulating layer 30 is mainly used for protecting the gate layer 20 and insulating the gate layer 20 from the upper conductive material.
S40, forming an active material layer 401 and a second metal layer 501 on the gate insulating layer 30, wherein the active material layer 401 and the second metal layer 501 are patterned to form an active layer 40 and a source/drain layer 50, respectively;
referring to fig. 5D, in the present step, a first photoresist pattern 81 is formed from a photoresist material through a multi-stage mask to perform a first patterning process on the active material layer 401 and the second metal layer 501, then the first photoresist pattern 81 is processed through an ashing process to form a second photoresist pattern 82, so as to form the structure of fig. 5E, finally the second metal layer 501 is patterned through an etching process to form a source/drain layer 50 on the second metal layer 501, and meanwhile, the channel portion 410 of the active layer 40 is subjected to a surface etching process using an acid solution containing fluorine ions, so that the thickness of the channel portion 410 is smaller than the thickness of the conductive portions 420 located at two sides of the channel portion 410, so as to form the structure of fig. 5F.
In this step, the acid solution for etching the second metal layer 501 and the channel portion 410 may be the same.
In this embodiment, the channel portion 410 may include a first channel 411 close to the substrate 10 and a second channel 412 far from the substrate 10, and a mass ratio of a narrow-bandgap element in the first channel 411 is greater than a mass ratio of a narrow-bandgap element in the second channel 412.
In this embodiment, since the oxide doped in the channel portion 410 is composed of an oxide composed of a narrow bandgap element and a wide bandgap element, and the second channel 412 is disposed near the light emitting side, the first channel 411 is located between the substrate 10 and the second channel 412, and when external light enters the display panel, only the second channel 412 is irradiated, and since the mass of the narrow bandgap element in the second channel 412 is small, the oxide in the second channel 412 is mainly composed of a wide bandgap metal oxide, the influence of light on the second channel 412 is small under long-time lighting conditions; the first channel 411 is blocked by the second channel 412, so that the first channel 411 is less affected by light, i.e. the stability of the device of the thin film transistor 210 is ensured.
In the present embodiment, the material of the active layer 40 may be a metal oxide, such as Ln-IZO, ITZO, ITGZO, HIZO, IZO (InZnO), ZnO: F, In2O3:Sn、In2O3:Mo、Cd2SnO4、ZnO:Al、TiO2Nb, Cd-Sn-O or other metal oxides, the following examples of this application are illustrated by taking IGZO as an example.
In this embodiment, taking IGZO as an example, the indium element is a narrow bandgap element, and the gallium element and the zinc element are wide bandgap elements, so that the mass ratio of the indium element in the second channel 412 needs to be reduced.
In this embodiment, the mass concentration of the fluoride ion in the fluoride ion-containing acid solution may be 0.01% to 4%.
In this embodiment, the mass ratio of the narrow-gap element in the first channel 411 portion 410 is the same as the mass ratio of the narrow-gap element in the conductive portion 420.
In the present embodiment, the thickness of the channel portion 410 is smaller than the thickness of the conductive portion 420 in the direction from the substrate 10 to the active layer 40.
In this embodiment, the difference between the thicknesses of the conductive portion 420 and the channel portion 410 may range from 200 angstroms to 300 angstroms.
S50, forming a passivation layer 60 on the source drain layer 50;
referring to fig. 5G, in this step, the passivation layer 60 covers the source/drain layer 50 to insulate the source/drain layer 50 from the upper and lower conductive metals, and the material of the passivation layer 60 may include a compound composed of nitrogen, silicon, and oxygen.
And S60, forming a common electrode layer 70 on the passivation layer 60.
Referring to fig. 5H, in this step, the common electrode layer 70 may be transparent ito or other transparent metal material.
The application also provides a mobile terminal, which comprises a terminal main body and the display panel, wherein the terminal main body and the display panel are combined into a whole. The terminal body may be a device such as a circuit board bound to a display panel, a cover plate covering the display panel, or the like. The mobile terminal can comprise mobile phones, televisions, notebook computers and other electronic equipment.
The application discloses an array substrate and a display panel, wherein the array substrate comprises a substrate and an active layer arranged on the substrate, the active layer comprises a channel part and conductive parts arranged on two sides of the channel part, and the mass ratio of narrow-forbidden band elements in the channel part is smaller than that of the narrow-forbidden band elements in the conductive parts; according to the thin film transistor, the proportion of narrow forbidden band elements in a channel part in an active layer is reduced, the proportion of oxidized narrow forbidden bands in the channel part is reduced, the proportion of oxides formed by the wide forbidden band elements in the channel part is improved, the electron mobility of the active layer is improved, and the stability of the thin film transistor is further ensured.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to the related descriptions of other embodiments.
The array substrate and the display panel provided by the embodiments of the present application are described in detail above, and the principles and embodiments of the present application are explained herein by applying specific examples, and the description of the embodiments is only used to help understand the technical solutions and core ideas of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims (10)

1. An array substrate, comprising:
a substrate;
the active layer is arranged on the substrate and comprises a channel part and conductive parts arranged on two sides of the channel part;
wherein the mass ratio of the narrow-band-gap element in the channel portion is smaller than the mass ratio of the narrow-band-gap element in the conductive portion.
2. The array substrate of claim 1, wherein the channel portion comprises a first channel near a side of the substrate and a second channel far from the side of the substrate, and a mass ratio of the narrow-bandgap element in the first channel is larger than a mass ratio of the narrow-bandgap element in the second channel.
3. The array substrate of claim 2, wherein the mass fraction of the narrow-bandgap element in the channel portion is gradually decreased in a direction from the substrate to the active layer.
4. The array substrate of claim 2, wherein a mass ratio of the narrow-bandgap element in the first channel portion is the same as a mass ratio of the narrow-bandgap element in the conductive portion.
5. The array substrate of claim 1, wherein the first channel and the second channel are doped with different element species;
wherein the second channel comprises elemental fluorine.
6. The array substrate of claim 1, wherein the thickness of the channel portion is less than the thickness of the conductive portion in a direction from the substrate to the active layer.
7. The array substrate of claim 1, wherein the difference in thickness between the conductive portion and the channel portion is in a range of 200 angstroms to 300 angstroms.
8. The array substrate of claim 1, further comprising a gate layer disposed between the active layer and the substrate;
in a top view direction of the array substrate, an orthographic projection of the channel portion on the gate layer is located in the gate layer.
9. The array substrate of claim 8, wherein the array substrate comprises a source drain layer disposed on the active layer, the source drain layer comprising a source and a drain;
wherein, in a top view direction of the array substrate, orthographic projections of the source electrode and the drain electrode on the conductive part are positioned in the conductive part, and the source electrode and the drain electrode are in contact with the conductive part.
10. A display panel comprising the array substrate according to any one of claims 1 to 9 and a light emitting member on one side of the array substrate, wherein the array substrate and the light emitting member are combined into one body.
CN202210137156.9A 2022-02-15 2022-02-15 Array substrate and display panel Pending CN114464631A (en)

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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210137156.9A CN114464631A (en) 2022-02-15 2022-02-15 Array substrate and display panel

Publications (1)

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