CN114449194B - Parallel two-step single-slope analog-to-digital conversion circuit and working method thereof - Google Patents

Parallel two-step single-slope analog-to-digital conversion circuit and working method thereof Download PDF

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CN114449194B
CN114449194B CN202210103272.9A CN202210103272A CN114449194B CN 114449194 B CN114449194 B CN 114449194B CN 202210103272 A CN202210103272 A CN 202210103272A CN 114449194 B CN114449194 B CN 114449194B
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slope
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CN114449194A (en
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郭仲杰
王杨乐
许睿明
程新齐
卢沪
刘楠
杨佳乐
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Xian University of Technology
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/772—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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Abstract

The invention discloses a parallel two-step single-slope analog-to-digital conversion circuit and a working method thereof, wherein the parallel two-step single-slope analog-to-digital conversion circuit comprises comparators CMP1 and CMP2, a switched capacitor control network, holding capacitors C1 and C2, a first correction circuit and a second correction circuit; the first correction circuit comprises a capacitor C3, a switch S4 and two switches S5, wherein the negative end input of the comparator CMP1 is connected with the upper polar plate of the capacitor C3 and the switch S4, and the switch S4 is connected with V IN The lower polar plate of the capacitor C3 is connected with two paths of switches S5, and two paths of the switches S5 are connected with V REF The method comprises the steps of carrying out a first treatment on the surface of the The second correction circuit comprises a capacitor C4, a switch S6 and two switches S7, wherein the negative end input of the comparator CMP2 is connected with the upper polar plate of the capacitor C4 and the switch S6, and the switch S6 is connected with V IN A signal. The lower polar plate of the capacitor is connected with two switches S7, both switches are connected with V REF -1/2LSB. And the influence of non-ideal factors on an output result in the actual quantization process is eliminated.

Description

Parallel two-step single-slope analog-to-digital conversion circuit and working method thereof
Technical Field
The invention belongs to the field of analog-digital conversion, and relates to a parallel two-step single-slope analog-digital conversion circuit and a working method thereof.
Background
Since CMOS image sensors have low power consumption and high imaging speed, a great deal of attention is paid. With the wide development of image sensors, the conventional single-slope analog-to-digital conversion circuit cannot meet the requirements, and the two-step single-slope analog-to-digital conversion circuit has become the main stream of research at present, but voltage offset occurs in the coarse-fine slope conversion process due to non-ideal factors of the sampling circuit, so that the performance of the two-step ADC is directly affected. The precision of the traditional sampling circuit of the prior two-step ADC can not meet the requirement of high precision.
For a two-step monoclinic analog-digital converter, parasitic capacitance exists on the upper polar plate and the lower polar plate, and non-ideal factors exist on the sampling switch, which can cause the offset of the charge quantity stored on the sampling capacitor in the thickness quantization switching process. This offset directly results in a partial voltage value in the quantization range that cannot be quantized effectively, thus directly resulting in a reduction in conversion accuracy, which directly affects the performance of the ADC.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, and provides a parallel two-step single-slope analog-to-digital conversion circuit and a working method thereof, so that the size of a sampling circuit of a slope signal and an input signal is completely consistent with the working time sequence, and the influence of non-ideal factors on an output result in the actual quantization process is eliminated.
In order to achieve the purpose, the invention is realized by adopting the following technical scheme:
a parallel two-step single-slope analog-to-digital conversion circuit comprises a comparator CMP1, a comparator CMP2, a switched capacitor control network, a holding capacitor C1, a holding capacitor C2, a first correction circuit and a second correction circuit;
the switch capacitor network comprises two paths of coarse slope control switches S1, two paths of fine slope control switches S2 and two paths of digital control switches S3, wherein a first path of the coarse slope control switch S1 is connected with a coarse slope signal RAMP_C and the positive end input of a comparator CMP2 and the upper polar plate of a holding capacitor C2, and a second path of the coarse slope control switch S1 is connected with the coarse slope signal RAMP_C and the positive end input of the comparator CMP1 and the upper polar plate of the holding capacitor C1; the first path of the fine slope control switch S2 is connected with a fine slope signal RAMP_F and a lower polar plate of a holding capacitor C2, and the second path of the fine slope control switch S2 is connected with a fine slopeRAMP signal ramp_f and the lower plate of holding capacitor C1; the first path of the digital control switch S3 is connected with the reference voltage V REF And the lower polar plate of the holding capacitor C1, the second path of the digital control switch S3 is connected with the reference voltage V REF -1/2LSB and the lower plate of holding capacitance C2;
the first correction circuit comprises a capacitor C3, a switch S4 and two switches S5, wherein the negative end input of the comparator CMP1 is connected with the upper polar plate of the capacitor C3 and the switch S4, and the switch S4 is connected with V IN The lower polar plate of the capacitor C3 is connected with two paths of switches S5, and two paths of the switches S5 are connected with V REF ；
The second correction circuit comprises a capacitor C4, a switch S6 and two switches S7, wherein the negative end input of the comparator CMP2 is connected with the upper polar plate of the capacitor C4 and the switch S6, and the switch S6 is connected with V IN A signal. The lower polar plate of the capacitor is connected with two switches S7, both switches are connected with V REF -1/2LSB。
Preferably, the output terminals of the comparator CMP1 and the comparator CMP2 are each connected to a D flip-flop input terminal.
Further, the output ends of the two D triggers are connected with a counter.
Further, the output end of the D trigger connected with the comparator CMP2 is connected with the input end of a logic control circuit, and the output end of the logic control circuit is connected with the second path of the digital control switch S3.
The working method based on the parallel two-step single-slope analog-to-digital conversion circuit comprises the steps of parallel coarse quantization and fine quantization, wherein in the coarse-fine slope conversion process, sampling capacitors C1 and C2 and sampling capacitors C3 and C4 can sample a slope signal and an input signal at the same time, so that the input signal contains errors generated by the slope signal, and the relative difference value of the slope voltage and the input signal voltage is the same.
Preferably, the operation timings of the switch S4, the switch S6 and the coarse ramp control switch S1 are identical, and the operation timings of the switch S5, the switch S7 and the digital control switch S3 are identical.
Preferably, the course of the coarse quantization is: the coarse ramp control switch S1 is turned on to start coarse quantization, steps are performed in the coarse quantization range until the interval of the signal is found, after the interval of the signal is found,the comparators CMP1 and CMP2 are turned over, coarse quantization is completed, and the coarse slope control switch S1 is turned off; at this time, the upper plates of the holding capacitors C1 and C2 store the step voltage values of the slopes of the turning moments of the comparators CMP1 and CMP2, and the lower plates of the holding capacitors C1 and C2 are respectively fixed at the reference voltage V by the digital control switch S3 REF -1/2LSB and V REF The holding capacitances C1 and C2 store voltage information at the inverting timings of the comparators CMP1 and CMP 2.
Further, the process of fine quantization is as follows: the fine ramp control switch S2 is turned on, a fine ramp signal is connected to the lower plates of the holding capacitances C1 and C2, the upper plates of the holding capacitances C1 and C2 start to descend from the stored voltage information, the start of fine quantization starts from the interval point where coarse quantization is found, and when the comparators CMP1 and CMP2 are simultaneously turned over, the time information of the comparators CMP1 and CMP2 corresponding to the normal fine quantization ramp is adopted.
Compared with the prior art, the invention has the following beneficial effects:
the invention can convert the absolute charge offset of the slope signal and the input signal into the relative charge offset by correcting the switched capacitor sampling circuit, designs the input signal from the angle of ensuring the relative difference value of the slope voltage and the input signal voltage, and samples the input signal at the same time, so that the input signal contains the error generated by the slope signal. In order to ensure that the slope error is the same as the input signal error, the size of a sampling circuit of the slope signal and the input signal is completely consistent with the working time sequence, the influence of nonideal factors of the sampling circuit is reduced, the correction effect is better when the coarse slope voltage and the input signal voltage are closer, the correction effect cannot be attenuated along with the improvement of ADC precision, and finally, the influence of the nonideal factors on an output result in the actual quantization process is eliminated.
Drawings
FIG. 1 is a schematic diagram of a parallel two-step single-slope analog-to-digital conversion circuit according to the present invention;
fig. 2 is a graph showing the effect of parasitic capacitance on quantization according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention; all other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that the words "front", "rear", "left", "right", "upper" and "lower" used in the following description refer to directions in the drawings, and the words "inner" and "outer" refer to directions toward or away from, respectively, the geometric center of a particular component.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
As shown in fig. 1, the parallel two-step single-slope analog-to-digital conversion circuit of the present invention includes a comparator CMP1 and a comparator CMP2, a switched capacitor control network, a digital logic control circuit, two ramp signals, a ramp correction circuit, two D flip-flops, and a counter; the positive end of the comparator CMP1 and the positive end of the comparator CMP2 are connected with the switched capacitor control network, the negative end of the comparator CMP1 and the comparator CMP2 are connected with the correction circuit, the output of the comparator CMP1 and the comparator CMP2 is connected with the D trigger, and the output of the comparator CMP1 and the comparator and the logic control circuit are connected. Specifically, the output end of the D trigger connected with the comparator CMP2 is connected with the input end of a logic control circuit, and the output end of the logic control circuit is connected with the second path of the digital control switch S3.
The switch capacitor network comprises two paths of coarse slope control switches S1, two paths of fine slope control switches S2 and two paths of digital control switches S3, wherein a first path of the coarse slope control switch S1 is connected with a coarse slope signal RAMP_C and an upper polar plate of a positive end input and a holding capacitor C2 of a comparator CMP2, and a second path of the coarse slope control switch S1 is connected with the coarse slope signal and the positive end input of the comparator CMP1 and the upper polar plate of the holding capacitor C1; thin and fineThe first path of the slope control switch S2 is connected with a fine slope signal RAMP_F and a lower polar plate of the holding capacitor C2, and the second path of the fine slope control switch S2 is connected with the fine slope signal RAMP_F and the lower polar plate of the holding capacitor C1; the first path of the digital control switch S3 is connected with the reference voltage V REF And the lower polar plate of the holding capacitor C1, the second path of the digital control switch S3 is connected with the reference voltage V REF -1/2LSB and the lower plate of holding capacitance C2.
The first correction circuit comprises a capacitor C3, a switch S4 and two switches S5, wherein the negative end input of the comparator CMP1 is connected with the upper polar plate of the capacitor C3 and the switch S4, and the switch S4 is connected with V IN The lower polar plate of the capacitor C3 is connected with two paths of switches S5, and two paths of the switches S5 are connected with V REF 。
The second correction circuit comprises a capacitor C4, a switch S6 and two switches S7, wherein the negative end input of the comparator CMP2 is connected with the upper polar plate of the capacitor C4 and the switch S6, and the switch S6 is connected with V IN A signal. The lower polar plate of the capacitor is connected with two switches S7, both switches are connected with V REF -1/2LSB。
Coarse quantization and fine quantization of the two-step single-slope analog-to-digital conversion circuit are processed in parallel. The coarse quantized and fine quantized ramp signals start to act at the same time. The switch S1 is opened to start coarse quantization. And (5) stepping in the coarse quantization range until the interval where the signal is located is found. After the interval of the signal is found, the comparators CMP1 and CMP2 are turned over, the coarse quantization is completed, and S1 is turned off. The upper electrode plates of the two holding capacitors store the step voltage value of the slope of the comparator at the overturning moment, and the lower electrode plates of the two holding capacitors are respectively fixed at the reference voltage V by the switch S3 REF -1/2LSB and V REF And (3) upper part. The voltage information at the moment of the comparator flip is stored on the capacitor.
The fine quantization process is as follows: the fine ramp control switch S2 is turned on. The fine ramp signal is connected to the lower plate of the holding capacitance. Due to the law of conservation of charge. The upper plate of the holding capacitance will start to drop from the previously stored voltage information. The start of the fine quantization is equivalent to the start of the interval point searched for by the coarse quantization. When two comparators are turned over simultaneously, the system defaults to adopt the time information of the comparator corresponding to the normal fine quantization slope, and the condition of signal loss can not occur.
In order to ensure that the ramp error is identical to the input signal error, the sampling circuit dimensions of the ramp signal and the input signal are completely consistent with the working time sequence, and the method is specifically expressed as follows: the operation time sequences of the switch S4, the switch S6 and the coarse slope control switch S1 are consistent, and the operation time sequences of the switch S5, the switch S7 and the digital control switch S3 are consistent.
In the whole quantization process, the specific correction process is as follows: the coarse slope control switch S1, the fine slope control switch S2 and the digital control switch S3 are controlled by a logic control circuit, and after the comparator is overturned, the comparator is controlled by a clock edge to read out, so that the switches are controlled. Prior to the start of the quantization period, the coarse ramp control switch S1 and the digital control switch S3 are turned on, and in particular implementations a down-plate sampling technique is employed to eliminate part of the clock feedthrough and switch charge injection effects. After the switch is opened, the coarse quantized ramp signal and the fine quantized ramp signal start to act at the same moment, the coarse ramp signal steps by delta V in the coarse quantization range, and the voltage values of the polar plates on the sampling capacitors C1 and C2 change along with the coarse ramp signal. When the coarse ramp signal is greater than the input signal V IN At this time, the comparators CMP1 and CMP2 are turned over, the coarse quantization is completed, and the coarse ramp control switch S1 and the digital control switch S3 are turned off. After the coarse quantization is finished, the fine slope control switch S2 is turned on, RAMP_F is connected to the lower polar plates of the sampling capacitors C1 and C2, and the RAMP_F is in the range of DeltaV and is stepped by LSB. Then the voltage value of the polar plates on the sampling capacitors C1 and C2 changes along with RAMP_F, and the input signal is finely quantized. When the comparator is flipped again, the entire quantization period is completed. In the whole quantization process, the working time sequences of the switch S4, the switch S6 and the coarse slope control switch S1 are consistent, and the working time sequences of the switch S5, the switch S7 and the digital control switch S3 are consistent, so that the sampling capacitors C1 and C2 at the positive end of the comparator and the sampling capacitors C3 and C4 at the negative end of the comparator can sample the slope signal and the input signal at the same time, and the input signal contains errors generated by the slope signal. In the course of thickness slope conversion, the relative difference between the slope voltage and the input signal voltage is ensured, the influence of nonideal factors of the sampling circuit is greatly reduced, and finally the output of the converted digital result after correction is realized.
In an ideal state, the existing quantization method can realize effective quantization of any voltage value in the ADC quantization range. However, in practical situations, due to parasitic capacitance of the upper and lower plates and non-ideal factors of the sampling switch, the amount of charge stored in the sampling capacitor is offset in the thickness quantization switching process. The offset can directly cause that a part of voltage values in a quantization range cannot be effectively quantized, and the performance of the ADC is directly affected, taking a sampling capacitor C1 as an example, in practical cases, after coarse quantization is finished, a coarse slope control switch S1 and a digital control switch S3 are disconnected, and the offset of the actual stored charge of the sampling capacitor C1 is as follows:
Figure BDA0003492942760000061
CP in the above structure B Is parasitic capacitance of the lower polar plate, W, L are width and length of MOS tube, VDD is switching tube starting voltage, V TH For threshold voltage, V RAMP_C Is a coarse ramp voltage. At the beginning of the fine quantization, the fine ramp control switch S2 is turned on, and at this time, the sampling capacitance C1 actually stores the offset of the charge as follows:
Figure BDA0003492942760000062
wherein CP T Is parasitic capacitance of upper polar plate, V RAMP_F Is a fine ramp voltage.
As can be seen from equations (1) (2), the charge offset on the capacitor is related to the coarse RAMP signal ramp_c and the fine RAMP signal ramp_f. Ramp_c is a major factor affecting the charge offset because of the small voltage range of ramp_f. For different input signals, the switching points of the thick and thin slopes are different, the generated slope errors are different, and the errors cannot be eliminated through digital correlated double sampling, lower polar plate sampling and other technologies.
This problem exists in all two-step ADCs. According to the above analysis, the key to this problem is that the difference between the ramp voltage stored on the storage capacitor and the input signal voltage changes during the coarse-fine ramp transition. In order to solve the above-mentioned problem of limiting the application of the two-step conversion method, a correction method as shown in fig. 2 is proposed herein, wherein the correction method is designed from the angle of ensuring the relative difference between the ramp voltage and the voltage of the input signal, and the ramp signal and the input signal are sampled simultaneously, so that the input signal contains the error generated by the ramp signal. In order to ensure that the ramp error is identical to the input signal error, the sampling circuit dimensions of the ramp signal and the input signal are completely consistent with the working time sequence, and the relative charge offset of the ramp signal and the input signal is as follows:
Figure BDA0003492942760000071
according to the correction method proposed herein, the absolute charge offset of the ramp signal and the input signal is converted into a relative charge offset as shown in equation (3). Now assume V RAMP_C ＝V IN Analyzing the correction result of the correction method, wherein the formula (4) shows the digital code change value from the switching of the thickness slope to the end of quantization under ideal conditions:
Figure BDA0003492942760000072
wherein V is RAMP_START Is the ramp voltage after switching.
Equation (5) is a digital code change value taking into account non-ideal factors of the sampling circuit:
Figure BDA0003492942760000073
the formula (6) is a digital code change value after a correction method is adopted:
Figure BDA0003492942760000074
according to formulas (3), (4), (5) and (6), the error correction method ensures the relative difference between the ramp voltage and the input signal voltage, reduces the influence of nonideal factors of the sampling circuit, and has better correction effect when the coarse ramp voltage and the input signal voltage are closer, so that the correction effect of the correction method cannot be attenuated with the improvement of ADC precision.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
It is to be understood that the above description is intended to be illustrative, and not restrictive. Many embodiments and many applications other than the examples provided will be apparent to those of skill in the art upon reading the above description. The scope of the present teachings should, therefore, be determined not with reference to the above description, but instead should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. The disclosures of all articles and references, including patent applications and publications, are incorporated herein by reference for the purpose of completeness. The omission of any aspect of the subject matter disclosed herein in the preceding claims is not intended to forego such subject matter, nor should the applicant be deemed to have such subject matter not considered to be part of the disclosed subject matter.

Claims (8)

1. The parallel two-step single-slope analog-to-digital conversion circuit is characterized by comprising a comparator CMP1, a comparator CMP2, a switch capacitance control network, a holding capacitance C1, a holding capacitance C2, a first correction circuit and a second correction circuit;
the switched capacitor network comprises two paths of coarse slope controlThe device comprises a switch S1, two paths of fine slope control switches S2 and two paths of digital control switches S3, wherein a first path of the coarse slope control switch S1 is connected with a coarse slope signal RAMP_C and an upper polar plate of a positive end input and holding capacitor C2 of a comparator CMP2, and a second path of the coarse slope control switch S1 is connected with the coarse slope signal RAMP_C and the positive end input and holding capacitor C1 of the comparator CMP 1; the first path of the fine slope control switch S2 is connected with a fine slope signal RAMP_F and a lower polar plate of the holding capacitor C2, and the second path of the fine slope control switch S2 is connected with the fine slope signal RAMP_F and the lower polar plate of the holding capacitor C1; the first path of the digital control switch S3 is connected with the reference voltage V REF And the lower polar plate of the holding capacitor C1, the second path of the digital control switch S3 is connected with the reference voltage V REF -1/2LSB and the lower plate of holding capacitance C2;
the first correction circuit comprises a capacitor C3, a switch S4 and two switches S5, wherein the negative end input of the comparator CMP1 is connected with the upper polar plate of the capacitor C3 and the switch S4, and the switch S4 is connected with V IN The lower polar plate of the capacitor C3 is connected with two paths of switches S5, and two paths of the switches S5 are connected with V REF ；
The second correction circuit comprises a capacitor C4, a switch S6 and two switches S7, wherein the negative end input of the comparator CMP2 is connected with the upper polar plate of the capacitor C4 and the switch S6, and the switch S6 is connected with V IN A signal; the lower polar plate of the capacitor is connected with two switches S7, both switches are connected with V REF -1/2LSB。
2. The parallel two-step single-slope analog-to-digital conversion circuit according to claim 1, wherein the output terminals of the comparator CMP1 and the comparator CMP2 are each connected to a D flip-flop input terminal.
3. The parallel two-step single-slope analog-to-digital conversion circuit of claim 2, wherein the outputs of both D flip-flops are connected to a counter.
4. The parallel two-step single-slope analog-to-digital conversion circuit according to claim 2, wherein the output end of the D flip-flop connected with the comparator CMP2 is connected with the input end of the logic control circuit, and the output end of the logic control circuit is connected with the second path of the digital control switch S3.
5. A method of operating a parallel two-step single slope analog to digital conversion circuit according to any of claims 1 to 4, wherein in the parallel coarse quantization and fine quantization processes, the sampling capacitors C1 and C2 and the sampling capacitors C3 and C4 sample the ramp signal and the input signal simultaneously during the coarse-fine ramp conversion process, so that the input signal contains an error generated by the ramp signal, and the relative difference between the ramp voltage and the input signal voltage is the same.
6. The method of claim 5, wherein the switch S4, the switch S6 and the coarse ramp control switch S1 are operated at the same time, and the switch S5, the switch S7 and the digital control switch S3 are operated at the same time.
7. The method of claim 5, wherein the coarse quantization is performed by: turning on a coarse slope control switch S1 to start coarse quantization, stepping in a coarse quantization range until a section where a signal is located is found, turning over comparators CMP1 and CMP2 after the section where the signal is located is found, and turning off the coarse slope control switch S1 after the coarse quantization is completed; at this time, the upper plates of the holding capacitors C1 and C2 store the step voltage values of the slopes of the turning moments of the comparators CMP1 and CMP2, and the lower plates of the holding capacitors C1 and C2 are respectively fixed at the reference voltage V by the digital control switch S3 REF -1/2LSB and V REF The holding capacitances C1 and C2 store voltage information at the inverting timings of the comparators CMP1 and CMP 2.
8. The method of claim 7, wherein the process of fine quantization is: the fine ramp control switch S2 is turned on, a fine ramp signal is connected to the lower plates of the holding capacitances C1 and C2, the upper plates of the holding capacitances C1 and C2 start to descend from the stored voltage information, the start of fine quantization starts from the interval point where coarse quantization is found, and when the comparators CMP1 and CMP2 are simultaneously turned over, the time information of the comparators CMP1 and CMP2 corresponding to the normal fine quantization ramp is adopted.
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