CN114449194B - A parallel two-step single-slope analog-to-digital conversion circuit and its working method - Google Patents

Abstract

The invention discloses a parallel two-step single-slope analog-to-digital conversion circuit and its working method, including comparators CMP1 and CMP2, a switch capacitor control network, holding capacitors C1 and C2, a first correction circuit and a second correction circuit; A correction circuit includes a capacitor C3, a switch S4 and two switches S5, the negative input of the comparator CMP1 is connected to the upper plate of the capacitor C3 and the switch S4, the switch S4 is connected to the V _IN signal, and the lower plate of the capacitor C3 is connected to the two switches S5, two circuits of the switch S5 are connected to V _REF ; the second correction circuit includes a capacitor C4, a switch S6 and two switches S7, the negative terminal input of the comparator CMP2 is connected to the upper plate of the capacitor C4 and the switch S6, and the switch S6 is connected to V _IN signal. The lower plate of the capacitor is connected to two switches S7, both of which are connected to V _REF -1/2LSB. The influence of non-ideal factors on the output results in the actual quantization process is eliminated.

Description

A parallel two-step single-slope analog-to-digital conversion circuit and its working method

technical field

The invention belongs to the field of analog-to-digital conversion, and relates to a parallel two-step single-slope analog-to-digital conversion circuit and a working method thereof.

Background technique

CMOS image sensors have gained a lot of attention due to their low power consumption and fast imaging speed. With the extensive development of image sensors, the traditional single-slope analog-to-digital conversion circuit can no longer meet the requirements. At present, the two-step single-slope analog-to-digital conversion circuit has become the mainstream of research, but due to the non-ideal factors of the sampling circuit, it will lead to thick and thin slopes. A voltage offset occurs during conversion that directly affects the performance of the two-step ADC. At present, the accuracy of the traditional sampling circuit of the two-step ADC can no longer meet the demand for high precision.

For the two-step single-slope analog-to-digital converter, the parasitic capacitance of the upper and lower plates and the non-ideal factors of the sampling switch will cause the amount of charge stored on the sampling capacitor to shift during the coarse-fine quantization switching process. This offset will directly result in partial voltage values within the quantization range being unable to be effectively quantized, thereby directly leading to a decrease in conversion accuracy and directly affecting the performance of the ADC.

Contents of the invention

The purpose of the present invention is to overcome the above-mentioned shortcoming of the prior art, provide a kind of parallel two-step single-slope analog-to-digital conversion circuit and its working method, make the sampling circuit size of the slope signal and the input signal completely consistent with the working sequence, eliminate the actual The impact of non-ideal factors in the quantization process on the output results.

In order to achieve the above object, the present invention adopts the following technical solutions to achieve:

A parallel two-step single-slope analog-to-digital conversion circuit, including a comparator CMP1, a comparator CMP2, a switched capacitor control network, a holding capacitor C1, a holding capacitor C2, a first correction circuit, and a second correction circuit;

The switched capacitor network includes two coarse ramp control switches S1, two fine ramp control switches S2, and two digital control switches S3. The first path of the coarse ramp control switch S1 is connected to the rough ramp signal RAMP_C and the positive input of the comparator CMP2 and The upper plate of the holding capacitor C2, the second path of the thick ramp control switch S1 is connected to the rough ramp signal RAMP_C and the positive terminal input of the comparator CMP1 and the upper plate of the holding capacitor C1; the first path of the fine ramp control switch S2 is connected to a fine ramp Signal RAMP_F and the lower plate of the holding capacitor C2, the second channel of the fine ramp control switch S2 is connected to the lower plate of the fine ramp signal RAMP_F and the holding capacitor C1; the first channel of the digital control switch S3 is connected to the reference voltage V _REF and the holding capacitor C1 The lower plate, the second channel of the digital control switch S3 is connected to the lower plate of the reference voltage V _REF -1/2LSB and the holding capacitor C2;

The first correction circuit includes a capacitor C3, a switch S4 and two switches S5, the negative input of the comparator CMP1 is connected to the upper plate of the capacitor C3 and the switch S4, the switch S4 is connected to the V _IN signal, and the lower plate of the capacitor C3 is connected to two circuits Switch S5, both of the switches S5 are connected to V _REF ;

The second correction circuit includes a capacitor C4, a switch S6 and two switches S7. The negative input of the comparator CMP2 is connected to the upper plate of the capacitor C4 and the switch S6, and the switch S6 is connected to the V _IN signal. The lower plate of the capacitor is connected to two switches S7, both of which are connected to V _REF -1/2LSB.

Preferably, the output terminals of the comparator CMP1 and the comparator CMP2 are each connected to an input terminal of a D flip-flop.

Further, the output terminals of the two D flip-flops are connected to the counter.

Further, the output end of the D flip-flop connected to the comparator CMP2 is connected to the input end of the logic control circuit, and the output end of the logic control circuit is connected to the second channel of the digital control switch S3.

A working method based on any one of the above-mentioned parallel two-step single-slope analog-to-digital conversion circuits, the process of parallel coarse quantization and fine quantization, during the coarse and fine slope conversion process, sampling capacitors C1 and C2 and sampling capacitors C3 and C4 The ramp signal and the input signal are sampled at the same time, so that the input signal contains the error generated by the ramp signal, so that the relative difference between the ramp voltage and the input signal voltage is the same.

Preferably, the working timing of the switch S4 and the switch S6 is consistent with that of the coarse ramp control switch S1 , and the working timing of the switch S5 and switch S7 is consistent with that of the digital control switch S3 .

Preferably, the process of coarse quantization is: turn on the coarse slope control switch S1 to start coarse quantization, step in the coarse quantization range until the interval where the signal is found, and after finding the interval where the signal is located, the comparators CMP1 and CMP2 Turn over, the coarse quantization is completed, and the coarse ramp control switch S1 is turned off; at this time, the upper plates of the holding capacitors C1 and C2 store the step voltage value of the ramp when the comparators CMP1 and CMP2 flip, and the lower plates of the holding capacitors C1 and C2 are The digital control switch S3 is fixed on the reference voltage V _REF -1/2LSB and V _REF respectively, and the holding capacitors C1 and C2 store the voltage information at the inversion time of the comparators CMP1 and CMP2 .

Further, the refinement process is as follows: the fine ramp control switch S2 is turned on, the fine ramp signal is connected to the lower plates of the holding capacitors C1 and C2, and the upper plates of the holding capacitors C1 and C2 start to drop from the stored voltage information , the start of fine quantization starts from the interval point found by coarse quantization. When the comparators CMP1 and CMP2 flip at the same time, the time information of the comparators CMP1 and CMP2 corresponding to the normal fine quantization slope is used.

Compared with the prior art, the present invention has the following beneficial effects:

The present invention can convert the absolute charge offset between the slope signal and the input signal into a relative charge offset by correcting the switched capacitor sampling circuit, and design it from the perspective of ensuring the relative difference between the slope voltage and the input signal voltage, and the input signal simultaneously Sampling is performed so that the input signal contains the error introduced by the ramp signal. In order to ensure that the slope error is the same as the input signal error, the size of the sampling circuit of the slope signal and the input signal is exactly the same as the working sequence, which reduces the influence of the non-ideal factors of the sampling circuit, and the closer the rough slope voltage and the input signal voltage are, the better the correction effect is. The correction effect will not attenuate with the improvement of ADC precision, and finally eliminate the influence of non-ideal factors on the output result in the actual quantization process.

Description of drawings

1 is a schematic diagram of a parallel two-step single-slope analog-to-digital conversion circuit of the present invention;

FIG. 2 shows the influence of parasitic capacitance on quantization in the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them; based on The embodiments of the present invention and all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

It should be noted that the words "front", "rear", "left", "right", "upper" and "lower" used in the following description refer to the directions in the drawings, and the words "inner" and "outer ” refer to directions towards or away from the geometric center of a particular part, respectively.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field of the invention. The terms used herein in the description of the present invention are for the purpose of describing specific embodiments only, and are not intended to limit the present invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

As shown in Figure 1, it is a parallel two-step single-slope analog-to-digital conversion circuit according to the present invention, including a comparator CMP1 and a comparator CMP2, a switched capacitor control network, a digital logic control circuit, two slope signals, and a slope correction circuit , two-way D flip-flops and counters; the positive terminals of the comparators CMP1 and CMP2 are connected to the switched capacitor control network, the negative terminals are input to the correction circuit, the outputs of the comparators CMP1 and CMP2 are connected to the D flip-flops, and the outputs are connected to the counter and logic Control circuit. Specifically, the output end of the D flip-flop connected to the comparator CMP2 is connected to the input end of the logic control circuit, and the output end of the logic control circuit is connected to the second channel of the digital control switch S3.

The switched capacitor network includes two coarse ramp control switches S1, two fine ramp control switches S2, and two digital control switches S3. The first path of the coarse ramp control switch S1 is connected to the rough ramp signal RAMP_C and the positive input of the comparator CMP2 and The upper plate of the holding capacitor C2, the second path of the coarse ramp control switch S1 is connected with the coarse ramp signal and the positive terminal input of the comparator CMP1 and the upper plate of the holding capacitor C1; the first path of the fine ramp control switch S2 is connected with the fine ramp signal RAMP_F and the lower plate of the holding capacitor C2, the second channel of the fine ramp control switch S2 is connected to the fine ramp signal RAMP_F and the lower plate of the holding capacitor C1; the first channel of the digital control switch S3 is connected to the reference voltage V _REF and the lower plate of the holding capacitor C1 The polar plate, the second channel of the digital control switch S3 is connected to the lower plate of the reference voltage V _REF -1/2LSB and the holding capacitor C2.

The first correction circuit includes a capacitor C3, a switch S4 and two switches S5, the negative input of the comparator CMP1 is connected to the upper plate of the capacitor C3 and the switch S4, the switch S4 is connected to the V _IN signal, and the lower plate of the capacitor C3 is connected to two circuits The switch S5, both of the two circuits of the switch S5 are connected to V _REF .

The second correction circuit includes a capacitor C4, a switch S6 and two switches S7. The negative input of the comparator CMP2 is connected to the upper plate of the capacitor C4 and the switch S6, and the switch S6 is connected to the V _IN signal. The lower plate of the capacitor is connected to two switches S7, both of which are connected to V _REF -1/2LSB.

Coarse quantization and fine quantization of the two-step single-slope analog-to-digital conversion circuit are processed in parallel. The ramp signals of coarse quantization and fine quantization start to work at the same time. Turn on switch S1 to start coarse quantization. Make steps in the coarse quantization range until you find the interval where the signal is located. After finding the interval where the signal is in, the comparators CMP1 and CMP2 are reversed, the coarse quantization is completed, and S1 is turned off. At this time, the upper plates of the two holding capacitors store the step voltage value of the slope at the moment when the comparator reverses, because the lower plates of the two holding capacitors are respectively fixed at the reference voltage V _REF -1/2LSB and V _REF by the switch S3 superior. Therefore, the capacitor stores the voltage information at the moment when the comparator flips.

The fine-grained process is as follows: the fine-slope control switch S2 is turned on. The thin ramp signal is connected to the lower plate of the holding capacitor. Due to the law of conservation of charge. The upper plate of the holding capacitor will drop from the previously stored voltage information. It is equivalent to the start of fine quantization, starting from the interval point found by coarse quantization. When the two comparators are flipped at the same time, the system will default to the time information of the comparator corresponding to the normal refinement ramp, and there will be no signal loss.

In order to ensure that the ramp error is the same as the input signal error, the sampling circuit size of the ramp signal and the input signal are exactly the same as the working sequence. The specific performance is: the working sequence of the switch S4, the switch S6 and the thick ramp control switch S1 are consistent, the switch S5, the switch S7 It is consistent with the working sequence of the digital control switch S3.

In the whole quantization process, the specific correction process is as follows: the rough slope control switch S1, the fine slope control switch S2 and the digital control switch S3 are controlled by the logic control circuit. After the comparator is reversed, the readout is controlled by the clock edge, and then the switch is controlled . Before the start of the quantization period, the coarse ramp control switch S1 and the digital control switch S3 are turned on. In the specific implementation, the lower plate sampling technology is used to eliminate the influence of part of the clock feedthrough and switch charge injection. After the switch is turned on, the ramp signals of coarse quantization and fine quantization start to act at the same time. The rough ramp signal is stepped by ΔV within the coarse quantization range, and the voltage values of the plates on the sampling capacitors C1 and C2 follow the rough ramp signal. When the coarse ramp signal is greater than the input signal V _IN , the comparators CMP1 and CMP2 are reversed, the coarse quantization is completed, and the coarse ramp control switch S1 and the digital control switch S3 are turned off. After the coarse quantization is finished, the fine slope control switch S2 is turned on, and RAMP_F is connected to the lower plates of sampling capacitors C1 and C2, and RAMP_F is within the range of ΔV, stepping by LSB. Afterwards, the plate voltage values on the sampling capacitors C1 and C2 follow the change of RAMP_F to refine the input signal. When the comparator toggles again, the entire quantization cycle is complete. During the whole quantization process, since the working timing of switch S4, switch S6 is consistent with that of coarse slope control switch S1, and the working timing of switch S5, switch S7 is consistent with that of digital control switch S3, the sampling capacitors C1 and C2 at the positive end of the comparator are compared with The sampling capacitors C3 and C4 at the negative end of the device will simultaneously sample the ramp signal and the input signal, so that the input signal contains the error generated by the ramp signal. During the conversion process of thick and thin slopes, the relative difference between the slope voltage and the input signal voltage is guaranteed, which greatly reduces the influence of non-ideal factors in the sampling circuit, and finally realizes the output of the converted digital result after correction.

In an ideal state, the existing quantization method can effectively quantify any voltage value in the quantization range of the ADC. However, in actual situations, due to the parasitic capacitance of the upper and lower plates and the non-ideal factors of the sampling switch, the amount of charge stored on the sampling capacitor will shift during the coarse and fine quantization switching process. This offset will directly cause some voltage values within the quantization range to be unable to be effectively quantized, which will directly affect the performance of the ADC. Take the sampling capacitor C1 as an example. The control switch S3 is turned off, and the actual charge offset of the sampling capacitor C1 is:

In the above structure, CP _B is the parasitic capacitance of the lower plate, W and L are the width and length of the MOS tube respectively, VDD is the turn-on voltage of the switch tube, V _TH is the threshold voltage, and V _{RAMP_C} is the rough ramp voltage. At the beginning of fine quantization, the fine slope control switch S2 is turned on, and the offset of the actual charge stored in the sampling capacitor C1 is:

Among them, C _T is the parasitic capacitance of the upper plate, and V _{RAMP_F} is the fine ramp voltage.

According to formulas (1) and (2), we can see that the charge offset on the capacitor is related to the coarse ramp signal RAMP_C and the fine ramp signal RAMP_F. Since the voltage range of RAMP_F is small, RAMP_C is the main factor affecting the charge offset. For different input signals, the switching points of thick and thin slopes are different, resulting in different slope errors, and this error cannot be eliminated by digital correlation double sampling, lower plate sampling and other technologies.

This problem exists in all two-step ADCs. According to the above analysis, the key to this problem lies in the change of the difference between the ramp voltage stored on the storage capacitor and the input signal voltage during the coarse and fine ramp conversion. Aiming at the problem of limiting the application of the two-step conversion method in the above analysis, this paper proposes a correction method as shown in Figure 2, which is designed from the perspective of ensuring the relative difference between the slope voltage and the input signal voltage, and samples the slope signal and the input signal at the same time , so that the input signal contains the error generated by the ramp signal. In order to ensure that the ramp error is the same as the input signal error, the sampling circuit size of the ramp signal and the input signal are completely consistent with the working timing. At this time, the relative charge offset between the ramp signal and the input signal is:

According to formula (3), the correction method proposed in this paper converts the absolute charge offset between the ramp signal and the input signal into a relative charge offset. Now assuming V _{RAMP_C} =V _IN , analyze the correction result of the correction method, the formula (4) reflects the change value of the digital code after the thick and thin ramp is switched to the end of quantization under ideal conditions:

Among them, V _{RAMP_START} is the ramp voltage after switching.

Formula (5) is the digital code change value after considering the non-ideal factors of the sampling circuit:

Formula (6) is the digital code change value after adopting the correction method:

According to the formulas (3)(4)(5)(6), it can be concluded that the error correction method ensures the relative difference between the ramp voltage and the input signal voltage, reduces the influence of non-ideal factors in the sampling circuit, and the coarse ramp voltage is consistent with the input signal voltage. The closer the signal voltage is to the better the correction effect is, so the correction effect of this correction method will not attenuate with the improvement of ADC accuracy.

It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is a relationship between these entities or operations. There is no such actual relationship or order between them. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or device.

It should be understood that the foregoing description is for purposes of illustration and not limitation. Many embodiments and many applications beyond the examples provided will be apparent to those of skill in the art from reading the above description. The scope of the present teachings, therefore, should be determined not with reference to the above description, but should be determined with reference to the preceding claims, along with the full scope of equivalents to which such claims are entitled. The disclosures of all articles and references, including patent applications and publications, are hereby incorporated by reference for completeness. The omission from the preceding claims of any aspect of the subject matter disclosed herein is not intended to be a disclaimer of such subject matter, nor should it be considered that the applicant did not consider the subject matter to be part of the disclosed inventive subject matter.

Claims (8)

1. A parallel two-step single-slope analog-to-digital conversion circuit, characterized in that it includes comparator CMP1, comparator CMP2, switched capacitor control network, holding capacitor C1, holding capacitor C2, the first correction circuit and the second correction circuit ; The switched capacitor network includes two coarse ramp control switches S1, two fine ramp control switches S2, and two digital control switches S3. The first path of the coarse ramp control switch S1 is connected to the rough ramp signal RAMP_C and the positive input of the comparator CMP2 and The upper plate of the holding capacitor C2, the second path of the thick ramp control switch S1 is connected to the rough ramp signal RAMP_C and the positive terminal input of the comparator CMP1 and the upper plate of the holding capacitor C1; the first path of the fine ramp control switch S2 is connected to a fine ramp Signal RAMP_F and the lower plate of the holding capacitor C2, the second channel of the fine ramp control switch S2 is connected to the lower plate of the fine ramp signal RAMP_F and the holding capacitor C1; the first channel of the digital control switch S3 is connected to the reference voltage V _REF and the holding capacitor C1 The lower plate, the second channel of the digital control switch S3 is connected to the lower plate of the reference voltage V _REF -1/2LSB and the holding capacitor C2; The first correction circuit includes a capacitor C3, a switch S4 and two switches S5, the negative input of the comparator CMP1 is connected to the upper plate of the capacitor C3 and the switch S4, the switch S4 is connected to the V _IN signal, and the lower plate of the capacitor C3 is connected to two circuits Switch S5, both of the switches S5 are connected to V _REF ; The second correction circuit includes a capacitor C4, a switch S6 and two switches S7, the negative terminal input of the comparator CMP2 is connected to the upper plate of the capacitor C4 and the switch S6, and the switch S6 is connected to the V _IN signal; the lower plate of the capacitor is connected to the two switches S7, both switches are connected to V _REF -1/2LSB. 2. The parallel two-step single-slope analog-to-digital conversion circuit according to claim 1, wherein the output terminals of the comparator CMP1 and the comparator CMP2 are each connected to an input terminal of a D flip-flop. 3. The parallel two-step single-slope analog-to-digital conversion circuit according to claim 2, wherein the output terminals of the two D flip-flops are connected to the counter. 4. parallel two-step type single-slope analog-to-digital conversion circuit according to claim 2, is characterized in that, the D flip-flop output end that is connected with comparator CMP2 is connected with logic control circuit input end, logic control circuit output end and digital The control switch S3 is connected in the second way. 5. A working method based on the parallel two-step single-slope analog-to-digital conversion circuit described in any one of claims 1-4, characterized in that, the process of parallel coarse quantization and fine quantization, in the thick and thin slope conversion process, sampling Capacitors C1 and C2 and sampling capacitors C3 and C4 will sample the ramp signal and the input signal at the same time, so that the input signal contains the error generated by the ramp signal, so that the relative difference between the ramp voltage and the input signal voltage is the same. 6. The working method of the parallel two-step single-slope analog-to-digital conversion circuit according to claim 5, wherein the operating sequence of the switch S4, the switch S6 and the thick slope control switch S1 are consistent, and the switch S5, the switch S7 and the digital The working sequence of the control switch S3 is consistent. 7. The working method of the parallel two-step single-slope analog-to-digital conversion circuit according to claim 5 is characterized in that, the process of coarse quantization is: open the thick slope control switch S1 to start coarse quantization, and do step in the coarse quantization range After finding the interval where the signal is located, the comparators CMP1 and CMP2 are turned over, the coarse quantization is completed, and the coarse ramp control switch S1 is turned off; at this time, the upper plates of the capacitors C1 and C2 are stored The step voltage value of the slope at the moment when the comparators CMP1 and CMP2 reverse, the lower plates of the holding capacitors C1 and C2 are respectively fixed on the reference voltage V _REF -1/2LSB and V _REF by the digital control switch S3, and the holding capacitors C1 and C2 C2 stores the voltage information at the moment when the comparators CMP1 and CMP2 flip. 8. The working method of the parallel two-step single-slope analog-to-digital conversion circuit according to claim 7, characterized in that, the fine-grained process is as follows: the fine-slope control switch S2 is opened, and the fine-slope signal is connected to the holding capacitor C1 And on the lower plates of C2, the upper plates of the holding capacitors C1 and C2 start to drop from the stored voltage information, and the start of fine quantization starts from the interval point that the coarse quantization is looking for, when the comparators CMP1 and CMP2 flip at the same time , using the time information of the comparators CMP1 and CMP2 corresponding to the normal refinement ramp.

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