CN114448386B

CN114448386B - Time delay device

Info

Publication number: CN114448386B
Application number: CN202210120719.3A
Authority: CN
Inventors: 郭斌; 陈佩
Original assignee: Wuxi Jingyuan Microelectronics Co Ltd
Current assignee: Wuxi Jingyuan Microelectronics Co Ltd
Priority date: 2022-02-09
Filing date: 2022-02-09
Publication date: 2023-03-24
Anticipated expiration: 2042-02-09
Also published as: CN114448386A

Abstract

The invention provides a time delay device, comprising: the circuit comprises a current source, a capacitor, a first NMOS tube, a second NMOS tube, a first switch, a first phase inverter, a second phase inverter and a third phase inverter. According to the invention, the capacitor is charged by using the current source, and the first NMOS tube and the second NMOS tube enter the sub-threshold region, so that the charging current at two ends of the capacitor is the sub-threshold region current to prolong the charging time of the capacitor (prolong the time from the voltage charging of the capacitor to the overturning voltage of the first inverter), thereby obtaining the delay signal with longer delay time. The invention charges the capacitor by using the sub-threshold region small current to generate longer time delay, avoids the condition that a large-area capacitor or a resistor with large resistance is used in the traditional circuit, and reduces the occupied design area of a chip.

Description

Time delay device

Technical Field

The invention relates to the technical field of delay circuits, in particular to a delay device.

Background

At present, the common delay circuits are generally a constant-current charging delay device (circuit), an RC charging delay device (circuit) and a digital counting delay device (circuit).

Referring to fig. 1, fig. 1 is a circuit structure diagram of a conventional constant current charging delay device, the constant current charging delay device includes: the delay circuit comprises a current source I2, a capacitor C2, a first inverter X4, a second inverter X5, a first switch K3 and a second switch K4 controlled by external input signals, wherein the working process of the delay device mainly comprises the following steps: when an external input signal controls the second switch K4 to be switched on and the first switch K3 to be switched off, the capacitor C2 is charged through the current source I2; when the input upper turning point of the first inverter X4 is charged, the output end of the first inverter X4 is turned to be at a low level, namely the output end of the first inverter X4 and the ground end have the same potential; the output end of the second inverter X5 is inverted to a high level, that is, the output end of the second inverter X5 and the power supply voltage are at the same potential, and it can be seen that the delay of the constant-current charging delay device is mainly reflected in the time when the current source I2 charges the capacitor C2 to the upper inversion point of the first inverter X4.

However, in order to realize a large delay, the constant-current charging delay device needs to select a small current source I2 and a large capacitor C2, which are difficult to manufacture, and in addition, the large capacitor occupies a large design area.

Referring to fig. 2, fig. 2 is a circuit diagram of a conventional RC charging delay device, the RC charging delay device includes: the delay circuit comprises a current limiting resistor R1, a capacitor C3, a first switch K5 and a second switch K6 controlled by external input signals, and a first inverter X6 and a second inverter X7, wherein the working process of the delay device mainly comprises the following steps: when an external input signal controls the second switch K6 to be closed and the first switch K5 to be opened, the capacitor C3 is charged through the current limiting resistor R1; when the input of the first inverter X6 is charged to the upper turning point, the output end of the first inverter X6 is turned to low level, namely the output end of the first inverter X6 and the ground end have the same potential; the output end of the second inverter X7 is inverted to a high level, that is, the output end of the second inverter X5 and the power supply voltage are at the same potential, and as can be seen, the delay of the RC charging delay device is mainly embodied in the time when the current-limiting resistor R1 charges the capacitor C3 to the upper inversion point of the second inverter X7.

However, the RC charging delay device needs to select a large charging current limiting resistor R1 and a large capacitor C2 for a large time delay, and occupies a large chip design area.

Referring to fig. 3, fig. 3 is a circuit structure diagram of a conventional digital counting delay device, and the digital counting delay device includes: the delay device comprises an oscillator M1, a first D trigger D1, a second D trigger D2, a third D trigger D3, a first digital logic AND gate X8 and a second digital logic AND gate X9, wherein the working process of the delay device mainly comprises the following steps: firstly, an oscillator M1 works to generate square waves with fixed frequency f; when an external input signal enters from IN, the external input signal enters SET of a first D trigger D1, a second D trigger D2 and a third D trigger D3, and a frequency divider formed by the first D trigger D1, the second D trigger D2 and the third D trigger D3 starts to work; the Q end output frequency of the first D trigger D1 is 1/2f of the square wave frequency of the oscillator; the Q end output frequency of the second D trigger D2 is 1/4f of the square wave frequency of the oscillator; the Q end output frequency of the third D trigger D3 is 1/8f of the square wave frequency of the oscillator; then three square waves are input into three input ends of a first digital logic AND gate X8, and when the three input ends are high level, high level is output; then the output signal of the first digital logic and gate X8 and the external input signal are input to two input terminals of the second digital logic and gate X9; thereby forming a delay to the external input signal.

However, in order to obtain a long delay time, the above digital counting delay apparatus needs an oscillator module, a plurality of D flip-flops and logic gates, the generated delay is mainly determined by the frequency of the oscillator and the number of D flip-flops, the structure of the oscillator is relatively complex, the occupied chip design area is too large, and the occupied chip design area of the plurality of D flip-flops and logic gates is also large.

Disclosure of Invention

The application provides a time delay device, can solve traditional time delay circuit in electric capacity, current-limiting resistor, oscillator or trigger etc. at least one kind of components and parts occupy the too big problem of whole chip overall design area.

In one aspect, an embodiment of the present application provides a delay apparatus, including: the power supply circuit comprises a current source, a capacitor, a first NMOS tube, a second NMOS tube, a first switch, a first phase inverter, a second phase inverter and a third phase inverter;

one end of the current source is connected with a power supply, the other end of the current source is respectively connected with the anode of the capacitor, the drain electrode of the second NMOS tube, the first end of the first switch and the input end of the first reverser, the cathode of the capacitor is respectively connected with the drain electrode and the grid electrode of the first NMOS tube and the grid electrode of the second NMOS tube, the source electrode of the first NMOS tube, the source electrode of the second NMOS tube and the second end of the first switch are all grounded, and the first phase inverter, the second phase inverter and the third phase inverter are sequentially connected in series;

wherein, the first switch is controlled to be switched on or off according to an external initial signal; when the first switch is turned off, the current source charges the capacitor, the first NMOS tube and the second NMOS tube are conducted and enter a subthreshold region to prolong the charging time of the capacitor; when the first switch is conducted, the capacitor discharges, wherein during the charging and discharging of the capacitor, a positive level signal of the capacitor is processed by the first NMOS transistor, the second NMOS transistor and the first switch, and a delay signal is output to a rear stage through the first inverter, the second inverter and the third inverter.

Optionally, in the delay apparatus, the delay apparatus further includes: the power supply comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second switch and a fourth phase inverter, wherein the source electrode of the first PMOS tube is connected with the power supply, the drain electrode of the first PMOS tube is connected with the first end of the second switch, the second end of the second switch is connected with the drain electrode of the second NMOS tube, the input end of the fourth phase inverter is connected with the output end of the second phase inverter, and the grid electrode of the first PMOS tube is connected with the output end of the fourth phase inverter.

Optionally, in the time delay device, the first switch is a third NMOS transistor, a third end of the third NMOS transistor receives an external initial signal, wherein a first end of the third NMOS transistor is a drain, a second end of the third NMOS transistor is a source, and a third end of the third NMOS transistor is a gate.

Optionally, in the delay device, the second switch is a second PMOS transistor, a third end of the second PMOS transistor receives an external initial signal, a first end of the second PMOS transistor is a source electrode, a second end of the second PMOS transistor is a drain electrode, and a third end of the second PMOS transistor is a gate electrode.

Optionally, in the delay device, the first inverter, the second inverter, the third inverter, and the fourth inverter are the same.

The technical scheme at least comprises the following advantages:

the current source is utilized for charging the capacitor, the first NMOS tube and the second NMOS tube enter the subthreshold region, so that the charging current at two ends of the capacitor is the subthreshold region current, the charging time of the capacitor is prolonged (the voltage of the capacitor is prolonged to the time of the overturning voltage of the first reverser), and a delay signal with long delay time is obtained.

This application utilizes sub-threshold region undercurrent right the condenser charges in order to produce the time delay of longer time, has avoided using the condition of large tracts of land electric capacity or the resistance of big resistance among the traditional circuit, has reduced the design area who occupies the chip, has improved the adaptability of being applied to integrated circuit.

Drawings

Fig. 1 is a circuit configuration diagram of a conventional constant current charging delay device;

fig. 2 is a circuit configuration diagram of a conventional RC charging delay device;

fig. 3 is a circuit configuration diagram of a conventional digital counting delay device;

FIG. 4 is a circuit configuration diagram of a delay device according to an embodiment of the present invention;

FIG. 5 is a circuit configuration diagram of a delay device detailing a first switch and a second switch in an embodiment of the present invention;

fig. 6 is a waveform diagram of an external initial signal IN, a level signal of the positive terminal a of the capacitor, and an output delay signal OUT of the delay device according to the embodiment of the present invention.

Detailed Description

The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.

Referring to fig. 4, fig. 4 is a circuit structure diagram of a delay apparatus according to an embodiment of the present invention, where the delay apparatus includes: the circuit comprises a current source I1, a capacitor C1, a first NMOS tube N1, a second NMOS tube N2, a first switch K1, a first phase inverter X1, a second phase inverter X2 and a third phase inverter X3. Wherein, the one end and the power of current source I1 are connected, the other end of current source I1 respectively with condenser C1's positive pole, second NMOS pipe N2's drain electrode, first switch K1's first end and first reverser X1's input is connected, condenser C1's negative pole respectively with first NMOS pipe N1's drain electrode and grid and second NMOS pipe N2's grid are connected, first NMOS pipe N1's source electrode, second NMOS pipe N2's source electrode with first switch K1's second end all ground connection, first phase inverter X1 second phase inverter X2 with third phase inverter X3 connects gradually in series.

Further, the delay device further includes: the power supply circuit comprises a first PMOS tube P1, a second switch K2 and a fourth phase inverter X4, wherein the source electrode of the first PMOS tube P1 is connected with the power supply, the drain electrode of the first PMOS tube P1 is connected with the first end of the second switch K2, the second end of the second switch K2 is connected with the drain electrode of the second NMOS tube N2, the input end of the fourth phase inverter X4 is connected with the output end of the second phase inverter X2, and the grid electrode of the first PMOS tube P1 is connected with the output end of the fourth phase inverter X4.

In this embodiment, the first inverter X1, the second inverter X2, and the fourth inverter X4 are all the same.

In this embodiment, the first switch K1 and the second switch K2 are controlled to be turned on or off according to an external initial signal. When the first switch K1 is turned off, the current source I1 charges the capacitor C1, and the first NMOS transistor N1 and the second NMOS transistor N2 are turned on and enter a sub-threshold region to prolong the charging time of the capacitor C1.

Further, when an external initial signal controls the second switch K2 to be turned on and the first switch K1 to be turned off, the current source I1 charges the capacitor C1, during the charging period of the capacitor C1, the gate of the first PMOS transistor P1 receives a high level signal, and the first PMOS transistor P1 is turned off; when the capacitor C1 is charged to the upper inversion voltage of the first inverter X1, a level inversion occurs on the delay signal output to the subsequent circuit. The gate of the first PMOS transistor P1 receives a low level signal, the first PMOS transistor P1 is turned on, at this time, the level signal of the positive electrode (point a) of the capacitor C1 is at a high level, and the level signal of the positive electrode (point a) of the capacitor C1 is always at the high level before the external initial signal controls the second switch K2 to be turned off next time and the first switch K1 is turned on.

Further, when the external initial signal controls the second switch K2 to turn off and the first switch K1 to turn on next time, the capacitor C1 discharges, the level signal of the positive electrode (point a) of the capacitor C1 changes to a low level, and the delay signal undergoes level inversion once again.

In this embodiment, during the charging and discharging period of the capacitor C1, the positive level signal of the capacitor C1 is processed by the first NMOS transistor N1, the second NMOS transistor N2 and the first switch K1 to generate an intermediate signal (a waveform diagram of a point a potential), and the intermediate signal can output an actually required delay signal with a long delay to a subsequent circuit through the first inverter X1, the second inverter X2 and the third inverter X3.

It can be seen that, this application utilizes the current source give the condenser charges, first NMOS pipe with the second NMOS pipe gets into sub-threshold region, makes the charging current at condenser both ends is sub-threshold region electric current, thereby prolongs the charge time of condenser (extension the voltage of condenser charges to the time of the upset voltage of first reverser), thereby obtains the longer time delay signal of time delay.

Referring to fig. 5, fig. 5 is a circuit structure diagram of a delay device for refining a first switch and a second switch according to an embodiment of the present invention, preferably, the first switch K1 is a third NMOS transistor N3, a third terminal of the third NMOS transistor N3 receives an external initial signal, wherein a first terminal of the third NMOS transistor N3 is a drain, a second terminal of the third NMOS transistor N3 is a source, and a third terminal of the third NMOS transistor N3 is a gate.

Preferably, the second switch K2 is a second PMOS transistor P2, a third end of the second PMOS transistor P2 receives an external initial signal, wherein a first end of the second PMOS transistor P2 is a source electrode, a second end of the second PMOS transistor P2 is a drain electrode, and a third end of the second PMOS transistor P2 is a gate electrode.

Specifically, referring to fig. 6, fig. 6 is a waveform diagram of an external initial signal IN, a level signal of a positive terminal a of the capacitor, and an output delay signal OUT of the delay device according to the embodiment of the present invention, and the operation process of the delay device according to the embodiment of the present invention is described IN detail with reference to fig. 5 and 6.

First, an external initial signal IN controls the first switch K1 to be turned on, the second switch K2 to be turned off, the voltage across the capacitor C1 is pulled to the ground potential, the potentials at the point a and the point C are both low ("0"), the delay signal OUT output by the third inverter X3 may be considered as a high state initially, the potential of the voltage output to the gate of the first PMOS transistor P1 through the fourth inverter X4 is a high ("1"), and the first PMOS transistor P1 is IN a closed state.

Then, an external initial signal IN controls the first switch K1 to turn off, the second switch K2 to turn on, and start to enter a time period t1, the current source I1 starts to charge the capacitor C1, and when the voltage on the capacitor C1 does not rise to the value of the turn-on voltage of the first NMOS transistor N1 and the second NMOS transistor N2, the charging current on the capacitor C1 is determined by the current source I1. The level signal (potential at point C) output by the second inverter X2 is still at low level, the gate potential of the first PMOS transistor P1 is still at high level ("1"), and the first PMOS transistor P1 is in off state; at this time, the delay signal OUT output from the third inverter X3 is still at a high level.

In this embodiment, assuming that the current of the current source I1 is I1, and the turn-on voltages of the first NMOS transistor N1 and the second NMOS transistor N2 are Vth, the voltage difference across the capacitor C1 is Vth. When the voltage on the capacitor C1 rises to the voltage value of the turn-on voltage Vth of the first NMOS transistor N1 and the second NMOS transistor N2, a time period t2 starts to be entered, the first NMOS transistor N1 and the second NMOS transistor N2 are turned on, and the first NMOS transistor N1 and the second NMOS transistor N2 enter a sub-threshold region.

In this embodiment, the width-to-length ratio of the first NMOS transistor N1 is an inverse ratio, which is much smaller than 1, and the width-to-length ratio of the first NMOS transistor N1 is 1/m of the width-to-length ratio of the second NMOS transistor N2; the drain current Idsn1 flowing through the first NMOS transistor N1 is 1/m of the drain current Idsn2 of the second NMOS transistor N2; since Idsn1+ m × Idsn1= I1, the current actually charged on the capacitor C1 is 1/(m + 1) of the current source I1, and it is seen that the charging current is greatly reduced.

When the charging voltage (gate-source voltage Vgs of the NMOS transistor) on the capacitor C1 is small, at this time, the first NMOS transistor N1 and the second NMOS transistor N2 enter a sub-threshold region. As the charging voltage (the gate-source voltage of the NMOS transistor) on the capacitor C1 is small, the drain current Idsn1 of the first NMOS transistor N1 and the drain current Idsn2 of the second NMOS transistor N2 can be small at the same W/L (width-to-length ratio). Since the gate-source voltage Vgsn1 of the first NMOS transistor N1 and the gate-source voltage Vgsn2 of the second NMOS transistor are identical, the ratio of the drain current Idsn1 of the first NMOS transistor N1 and the drain current Idsn2 of the second NMOS transistor N2 is the ratio of the width-to-length ratio W/L of the first NMOS transistor N1 and the width-to-length ratio W/L of the second NMOS transistor, so that the drain current flowing through the first NMOS transistor N1 is 1/m of the drain current of the second NMOS transistor N2, so the drain current Idsn1 of the first NMOS transistor N1 is 1/(1 m) of the current source current i1, so that the delay time is extended to (1 m) times of the original (1 m), and since both the first NMOS transistor N1 and the second NMOS transistor N2 operate in the sub-threshold region, the lower limit of the current can be reduced to a level, so that the delay time can reach a magnitude, as shown in t2 of fig. 6.

When the charging voltage (the gate-source voltage of the NMOS transistor) on the capacitor C1 is large, the first NMOS transistor N1 and the second NMOS transistor N2 enter a saturation region, and as can be seen from the large charging voltage (the gate-source voltage of the NMOS transistor) on the capacitor C1, the drain current Idsn1 of the first NMOS transistor N1 and the drain current Idsn2 of the second NMOS transistor N2 cannot be made small under the same W/L (width-to-length ratio).

Further, during the period that the external initial signal IN controls the first switch K1 to be turned off and the second switch K2 to be turned on, when the charging voltage (voltage at the point a) on the capacitor C1 rises to the input up-conversion point of the first inverter X1, the time period starts to enter t3, the potential at the point C is inverted to a high level, the delay signal OUT output by the third inverter X3 is inverted to a low level, so that the gate voltage of the first PMOS transistor P1 receives a low level ("0") output by the fourth inverter X4, which is equivalent to the gate ground terminal of the first PMOS transistor P1, the first PMOS transistor P1 is turned on and enters a saturation region, at this time, the level signal at the positive electrode (point a) of the capacitor C1 is at a high level, and the level signal at the positive electrode (point a) of the capacitor C1 is always maintained at a high level until the external initial signal next time controls the second switch K2 to be turned off and the first switch K1 to be turned on; at this time, the current actually charged to the capacitor C1 is 1/(1 + m) of the sum of the current I1 of the current source I1 and the drain current Idsp1 of the first PMOS transistor P1, the charging current of the capacitor C1 becomes large, and the potential at the point a rises faster due to the positive feedback, as shown by t3 in fig. 6. Wherein, the total delay of the initial signal IN input from the outside is t1+ t2; t3 is the time for accelerating the inversion, and the self-excitation problem caused by the back-and-forth shaking near the inversion point is prevented.

Finally, after a time period t4, an external initial signal IN controls the first switch K1 to be turned on and the second switch K2 to be turned off, the capacitor C1 discharges, a level signal of the positive electrode (point a) of the capacitor C1 is inverted to a low level, and a delay signal OUT output by the third inverter X3 is inverted to a high level.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention are intended to be covered by the present invention.

Claims

1. A time delay apparatus, comprising: the circuit comprises a current source, a capacitor, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a first switch, a first phase inverter, a second phase inverter and a third phase inverter;

one end of the current source is connected with a power supply, the other end of the current source is respectively connected with the anode of the capacitor, the drain electrode of the second NMOS tube, the first end of the first switch and the input end of the first phase inverter, the cathode of the capacitor is respectively connected with the drain electrode and the grid electrode of the first NMOS tube and the grid electrode of the second NMOS tube, the source electrode of the first NMOS tube, the source electrode of the second NMOS tube and the second end of the first switch are all grounded, and the first phase inverter, the second phase inverter and the third phase inverter are sequentially connected in series;

wherein, the first switch is controlled to be switched on or off according to an external initial signal; when the first switch is turned off, the current source charges the capacitor, the first NMOS tube and the second NMOS tube are conducted and enter a subthreshold region to prolong the charging time of the capacitor; when the first switch is conducted, the capacitor discharges, wherein during the charging and discharging of the capacitor, a positive level signal of the capacitor is processed by the first NMOS transistor, the second NMOS transistor and the first switch, and a delay signal is output to a rear stage through the first inverter, the second inverter and the third inverter;

the delay device further comprises: the power supply comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second switch and a fourth phase inverter, wherein the source electrode of the first PMOS tube is connected with the power supply, the drain electrode of the first PMOS tube is connected with the first end of the second switch, the second end of the second switch is connected with the drain electrode of the second NMOS tube, the input end of the fourth phase inverter is connected with the output end of the second phase inverter, and the grid electrode of the first PMOS tube is connected with the output end of the fourth phase inverter.

2. The delay device of claim 1, wherein the first switch is a third NMOS transistor, and a third terminal of the third NMOS transistor receives an external initial signal, wherein a first terminal of the third NMOS transistor is a drain, a second terminal of the third NMOS transistor is a source, and a third terminal of the third NMOS transistor is a gate.

3. The delay device of claim 1, wherein the second switch is a second PMOS transistor, and a third terminal of the second PMOS transistor receives an external initial signal, wherein a first terminal of the second PMOS transistor is a source, a second terminal of the second PMOS transistor is a drain, and a third terminal of the second PMOS transistor is a gate.

4. The delay device of claim 1, wherein the first inverter, the second inverter, a third inverter, and the fourth inverter are all the same.