CN107395012B - Charge pump circuit and control method thereof - Google Patents
Charge pump circuit and control method thereof Download PDFInfo
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- CN107395012B CN107395012B CN201710664194.9A CN201710664194A CN107395012B CN 107395012 B CN107395012 B CN 107395012B CN 201710664194 A CN201710664194 A CN 201710664194A CN 107395012 B CN107395012 B CN 107395012B
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- capacitor
- charge pump
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- charge
- pump circuit
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/14—Arrangements for reducing ripples from dc input or output
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses a charge pump circuit and a control method thereof, wherein the charge pump circuit comprises a charge-discharge circuit and a ripple suppression circuit, and the charge-discharge circuit receives an input signal and outputs a first voltage signal through a plurality of charge-discharge processes; the ripple suppression circuit receives the first voltage signal, is used for reducing ripple in the first voltage signal, and obtains an output signal of the charge pump. The invention adopts the ripple suppression circuit to replace the large capacitor in the prior art, can form a two-stage filtering structure, and simultaneously avoids the problem that the body diode is directly connected.
Description
Technical Field
The present disclosure relates to power electronics, and particularly to a charge pump circuit and a control method thereof.
Background
The charge pump is in fact a voltage converter for outputting the required dc voltage. Charge pumps are mostly used in systems that require a battery, such as in portable electronic devices. Portable electronic devices are evolving rapidly, and there is also a growing need for charge pumps. Fig. 1 is a schematic diagram of a charge pump circuit in the prior art, and fig. 1 includes 4 switching transistors M1, M2, M3, M4 and capacitors C1, C2, C3, where the switching transistors M1, M2, M3, M4 are exemplified by NMOS transistors. M1, M2, M3, M4 are connected in a loop structure two by two, the common node of M1 and M3 is connected with a power supply VDD, the voltage at the common node of M1 and M2 is V01, the voltage at the common node of M3 and M4 is V02, the common node of M2 and M4 is connected with one end of a capacitor C3, and the voltage at the common node is a charge pump output voltage Vout; the on-off of M1 and M4 is controlled by a pulse signal ctrl, and the on-off of M2 and M3 is controlled by a pulse signal
And (5) controlling. One end of the capacitor C1 is connected with the V01, and the other end of the capacitor C is input with a pulse signal clk; one end of the capacitor C2 is connected with V02, and the other end is input with pulse signal +.>
Pulse signal clk and
complementary, i.e. clk is high, +.>
A low level, where the high level is set to VDD and the low level is set to 0; pulse signals ctrl and->
Complementary, i.e. ctrl is high, +.>
At low level, pulse signals ctrl and +.>
The input voltage of the grid electrode of the NMOS tube is low enough to enable the switch tube to be turned on, and is set to be VDD; pulse signals ctrl and->
The input voltage to the gate of the NMOS transistor is high enough to turn on the switching transistor, here set to 2VDD. Pulse signal clk, and>
and pulse signals ctrl,/and>
the pulse widths are equal and are generated synchronously.
Referring to fig. 2, a waveform diagram of input and output voltages of a charge pump in the prior art is shown, when the input end of the charge pump inputs a voltage VDD, and VDD is higher than the sum of two diode turn-on voltages, body diodes of four MOS transistors of the charge pump have a through problem, so that the output voltage Vout of the charge pump is not zero. When the input pulse signal ctrl changes from low level to high level,
when the voltage level is changed from the high level to the low level, M1 and M4 are turned on, M2 and M3 are turned off, the pulse signal clk input at one end of the capacitor C1 is changed from VDD to 0, and the pulse signal +.>
From 0 to VDD, the voltage V01 is charged by M1 to VDD, the voltage V02 is instantaneously raised by VDD through the coupling of the capacitor C2, the charge in C2 flows to the capacitor C3 through M4, and the output voltage Vout rises; when ctrl becomes low, < +.>
When the voltage goes high, M1 and M4 are turned off, M2 and M3 are turned on, the clk signal inputted from one end of C1 goes from 0 to VDD, the voltage V01 is instantaneously raised to 2VDD by the coupling of the capacitor C1, the charge in C1 flows to C3, and the output voltage Vout rises. After a number of pulse periods, the output voltage Vout approaches 2×vdd.
In the prior art, a body diode of a MOS tube adopted by the charge pump can generate a through problem, so that the early rising speed of the output voltage of the charge pump is uncontrollable, and the charge pump cannot linearly rise from 0. In addition, in order to reduce the influence of output ripple of the charge pump, a high-voltage large capacitor C3 is connected in the charge pump, the C3 is large in size, and the production cost of the charge pump is additionally increased.
Disclosure of Invention
In view of the above, the present invention is to provide a charge pump circuit and a control method thereof, which are used for solving the problems of uncontrollable early-stage output voltage rising speed and high production cost of the charge pump in the prior art.
To achieve the above object, the present invention provides a charge pump circuit comprising:
and the charge-discharge circuit receives the input signal and outputs a first voltage signal which is multiple times of the input signal through a plurality of charge-discharge processes.
And the ripple suppression circuit is used for receiving the first voltage signal, reducing ripple in the first voltage signal and obtaining an output signal of the charge pump.
Optionally, the charge-discharge circuit includes four switching tubes, a first capacitor and a second capacitor, the four switching tubes are two by two to form a symmetrical loop structure, each two connected switching tubes are provided with a node, two symmetrical nodes are respectively connected with one end of the first capacitor and one end of the second capacitor, and the other two symmetrical nodes are respectively an input end and an output end of the charge-discharge circuit.
Optionally, the on-off of the four switching tubes of the charge-discharge circuit is controlled by pulse signals, and the pulse signals for controlling the on-off of every two adjacent switching tubes are complementary or identical; the other ends of the first capacitor and the second capacitor of the charge-discharge circuit respectively receive complementary pulse signals; the pulse width of the pulse signal for controlling the on-off of the switching tube is equal to and synchronous with the pulse width of the pulse signal received by the first capacitor and the second capacitor.
Optionally, the charge pump circuit further includes an auxiliary switching tube with a body diode, the auxiliary switching tube is connected to the output end of the converter, and the body diode of the auxiliary switching tube is turned off in a forward direction.
Optionally, the ripple suppression circuit includes two resistors and a third capacitor, the two resistors are connected, and a common node of the two resistors is connected to one end of the third capacitor.
Optionally, the output end of the charge pump circuit is connected with the control end of the first switching tube, and the two resistors, the third capacitor and the parasitic capacitor of the first switching tube of the ripple suppression circuit form a two-stage filtering structure.
Optionally, the first capacitor and the second capacitor store energy by charging, and discharge energy to the third capacitor alternately, and through the charging and discharging process, the ripple of the first voltage signal is reduced through a two-stage filtering structure formed by the ripple suppression circuit and the parasitic capacitance of the first switch tube.
Optionally, the charge pump circuit is a plurality of cascade circuits, and the output end of the last charge pump is used as the input end of the next charge pump.
The invention also provides a control method of the charge pump, which comprises the following steps of:
receiving an input signal and outputting a first voltage signal through a plurality of charge-discharge processes; and reducing ripple waves in the first voltage signal in a two-stage filtering mode, obtaining an output signal of the charge pump, and forming a two-stage filtering structure by two resistors of the ripple suppression circuit, a third capacitor and a parasitic capacitor of the first switch tube.
Compared with the prior art, the technical scheme of the invention has the following advantages: receiving an input signal and outputting a first voltage signal through a plurality of charge-discharge processes; and reducing ripple waves in the first voltage signal in a two-stage filtering mode, and obtaining an output signal of the charge pump. When the charge pump is electrified, the switching tube in the charge and discharge circuit is free from the problem of straight-through, the output voltage of the charge pump can be linearly increased from 0, and the rising speed of the output voltage in the starting process is always controllable. In addition, the invention adopts a ripple suppression circuit to replace a capacitor C3 in the prior art so as to reduce the output ripple of the charge pump. The ripple suppression circuit adopts much smaller capacitance than the filter capacitor C3 adopted in the prior art, so that on-chip integration can be realized, the application cost and area of the system are reduced, the reliability is improved, and the production cost of the charge pump is reduced.
Drawings
FIG. 1 is a schematic diagram of a prior art charge pump circuit;
FIG. 2 is a waveform diagram of an input/output voltage of a prior art charge pump circuit;
FIG. 3 is a schematic diagram of a circuit configuration of a charge pump circuit according to the present invention;
FIG. 4 is a schematic diagram of another circuit configuration of the charge pump circuit of the present invention;
FIG. 5 is a diagram of a pulse signal waveform for controlling the operation of a charge pump circuit according to the present invention;
FIG. 6 is a waveform diagram of the input/output voltage of the charge pump circuit of the present invention;
Detailed Description
The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but the present invention is not limited to these embodiments only. The invention is intended to cover any alternatives, modifications, equivalents, and variations that fall within the spirit and scope of the invention.
In the following description of preferred embodiments of the invention, specific details are set forth in order to provide a thorough understanding of the invention, and the invention will be fully understood to those skilled in the art without such details.
The invention is more particularly described by way of example in the following paragraphs with reference to the drawings. It should be noted that the drawings are in a simplified form and are not to scale precisely, but rather are merely intended to facilitate and clearly illustrate the embodiments of the present invention.
Referring to fig. 3, a circuit structure of the charge pump of the present invention is illustrated, and includes a charge-discharge circuit U01, a ripple suppression circuit U02, an auxiliary switching tube M5, and a first switching tube M01, where the auxiliary switching tube M5 is a PMOS tube and the first switching tube M01 is an NMOS tube. The charge-discharge circuit U01 includes 4 switching tubes M1, M2, M3, M4 and capacitors C1, C2, where the four switching tubes are exemplified by NMOS tubes. M1, M2, M3 and M4 are connected in a loop structure in pairs, the public node of M1 and M3 is connected with a power Vin, the voltage at the public node of M1 and M2 is V01, the voltage at the public node of M3 and M4 is V02, and the public node of M2 and M4 is the output end of a charge-discharge circuit U01; the on-off of M1 and M4 is controlled by a pulse signal ctrl, and the on-off of M2 and M3 is controlled by a pulse signal
And (5) controlling. One end of the capacitor C1 is connected with the V01, and the other end of the capacitor C is input with a pulse signal clk; one end of the capacitor C2 is connected with V02, and the other end is input with pulse signal +.>
And the drain electrode of the auxiliary switching tube M5 is connected with the output end of the charging and discharging circuit U01. The ripple suppression circuit U02 is connected with the source electrode of the auxiliary switching tube M5, the ripple suppression circuit comprises a resistor R1, a resistor R2 and a capacitor C301, one end of the resistor R1 is connected with one end of the resistor R2, the common node of the resistor R1 is connected with the capacitor C301, the output voltage Vout at the other end of the resistor R2 is the output voltage of the charge circuit, the other end of the resistor R2 is connected with the grid electrode of the M01, the resistor R1 is connected with a third capacitor, and the parasitic capacitance of the resistor R2 and the first switching tube M01 form a two-section filter structure.
The first switching tube M01 can realize different functions according to different application scenes, and a control end of the first switching tube M01 receives the voltage output by the charge pump circuit, so that the switching state of the first switching tube M01 is controlled.
Referring to FIG. 4, the charge of the present invention is illustratedThe other circuit structure of the pump is shown in fig. 4 and 3, wherein the switching transistors M1 and M3 are exemplified by NMOS transistors, the switching transistors M2 and M4 are exemplified by PMOS transistors, the switching transistors M1 and M2 are controlled by the pulse signal ctrl, and the switching transistors M2 and M4 are complementarily pulsed
And (5) controlling. The charge pump operation illustrated in fig. 4 and 3 is identical.
Referring to FIG. 5, a waveform diagram of a pulse signal, pulse signal clk and pulse signal clk are shown for controlling the operation of the charge pump according to the present invention
Complementary, i.e. clk is high, +.>
A low level, where the high level is set to VDD and the low level is set to 0; pulse signals ctrl and->
Complementary, i.e. ctrl is high, +.>
At low level, pulse signals ctrl and +.>
The input voltage of the grid electrode of the MOS tube is high, namely, the input voltage of the grid electrode of the MOS tube is enough to turn on or off the switching tube, and the input voltage is set to be 2VDD; pulse signals ctrl and->
The input voltage of the MOS transistor gate is low enough to turn on or off the switch transistor, and is set to be VDD. Pulse signal clk, and>
and pulse signals ctrl,/and>
the pulse widths are equal and synchronous.
Referring to fig. 6, a waveform diagram of the input and output voltages of the charge pump according to the present invention is shown, when the input voltage VDD is inputted to the input end of the charge pump, the body diode of the auxiliary switching tube M5 is turned off in the forward direction, the 4 MOS tubes of the charge and discharge circuit will not have a through problem, and the output voltage of the charge pump will not be outputted in advance. When the input pulse signal ctrl changes from low level to high level,
when the voltage level is changed from the high level to the low level, M1 and M4 are turned on, M2 and M3 are turned off, the pulse signal clk input at one end of the capacitor C1 is changed from VDD to 0, and the pulse signal +.>
From 0 to VDD, the voltage V01 is charged through the capacitor C1 to VDD, the voltage V02 is instantaneously pulled up to VDD through the coupling of the capacitor C2, the charge in the capacitor C2 flows to the capacitor C301 through the capacitor M4, and the output voltage Vout rises; when ctrl changes from high level to low level, +.>
When the voltage is changed from low level to high level, M1 and M4 are opened, M2 and M3 are closed, clk signal input at one end of C1 is changed from 0 to VDD, voltage V01 is pulled up to 2VDD instantly due to coupling of capacitor C1, charge in C1 flows to C301, output voltage Vout rises, and after a plurality of pulse periods, output voltage Vout approaches 2 x VDD. When there are N charge pumps cascaded, the output end of the last charge pump circuit is used as the input end of the next charge pump circuit, and the final output voltage Vout of the N charge pumps is close to (1+n) ×vdd.
When the charge pump is electrified, the switching tube in the converter is free from the straight-through problem, the output voltage of the charge pump can be linearly increased from 0, and the rising speed of the output voltage in the starting process is always controllable. In addition, the invention adopts a ripple suppression circuit to replace a capacitor C3 in the prior art so as to reduce the output ripple of the charge pump. The ripple suppression circuit adopts much smaller capacitance than the filter capacitor C3 adopted in the prior art, so that on-chip integration can be realized, the application cost and area of the system are reduced, the reliability is improved, and the application cost of the chip is reduced.
Although the embodiments have been described and illustrated separately above, and with respect to a partially common technique, it will be apparent to those skilled in the art that alternate and integration may be made between embodiments, with reference to one embodiment not explicitly described, and reference may be made to another embodiment described.
The above-described embodiments do not limit the scope of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the above embodiments should be included in the scope of the present invention.
Claims (7)
1. A charge pump circuit, comprising:
the charge-discharge circuit receives an input signal and outputs a first voltage signal through a plurality of charge-discharge processes;
the ripple suppression circuit is used for receiving the first voltage signal, reducing ripple in the first voltage signal and obtaining an output signal of the charge pump;
the ripple suppression circuit comprises two resistors and a third capacitor, wherein the two resistors are connected, and a common node of the two resistors is connected with one end of the third capacitor;
the output end of the charge pump circuit is connected with the control end of the first switching tube, and the two resistors, the third capacitor and the parasitic capacitor of the first switching tube of the ripple suppression circuit form a two-stage filter structure.
2. The charge pump circuit of claim 1, wherein: the charging and discharging circuit comprises four switching tubes, a first capacitor and a second capacitor, the four switching tubes are connected in pairs to form a symmetrical loop structure, each two connected switching tubes are provided with a node, two symmetrical nodes are respectively connected with one end of the first capacitor and one end of the second capacitor, and the other two symmetrical nodes are respectively an input end and an output end of the charging and discharging circuit.
3. The charge pump circuit of claim 2, wherein: the on-off of the four switching tubes of the charge-discharge circuit is controlled by pulse signals, and the pulse signals for controlling the on-off of every two adjacent switching tubes are complementary or identical; the other ends of the first capacitor and the second capacitor of the charge-discharge circuit respectively receive complementary pulse signals; the pulse width of the pulse signal for controlling the on-off of the switching tube is equal to and synchronous with the pulse width of the pulse signal received by the first capacitor and the second capacitor.
4. A charge pump circuit according to any one of claims 1-3, characterized in that: the charge pump circuit also comprises an auxiliary switching tube with a body diode, the auxiliary switching tube is connected with the output end of the charge-discharge circuit, and the body diode of the auxiliary switching tube is cut off in the forward direction.
5. The charge pump circuit of claim 2, wherein: the first capacitor and the second capacitor store energy through charging, discharge energy to the third capacitor alternately, and reduce ripple of the first voltage signal through a two-stage filtering structure formed by the ripple suppression circuit and the parasitic capacitance of the first switch tube.
6. A charge pump circuit according to any one of claims 1-3, characterized in that: the charge pump circuit is a plurality of cascade circuits, and the output end of the last charge pump circuit is used as the input end of the next charge pump circuit.
7. A control method of a charge pump circuit based on any one of claims 1-6, comprising the steps of:
receiving an input signal and outputting a first voltage signal through a plurality of charge-discharge processes; the ripple wave in the first voltage signal is reduced in a two-stage filtering mode, an output signal of the charge pump is obtained, and two resistors of the ripple wave suppression circuit, the third capacitor and the parasitic capacitor of the first switch tube form a two-stage filtering structure.
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| CN201710664194.9A CN107395012B (en) | 2017-08-04 | 2017-08-04 | Charge pump circuit and control method thereof |
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| CN201710664194.9A CN107395012B (en) | 2017-08-04 | 2017-08-04 | Charge pump circuit and control method thereof |
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| CN107395012B true CN107395012B (en) | 2023-05-16 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101488710A (en) * | 2008-10-22 | 2009-07-22 | 成都国腾电子技术股份有限公司 | A charge pump circuit |
| CN104953820A (en) * | 2015-06-29 | 2015-09-30 | 上海芯望电子技术有限公司 | Open-loop charge pump circuit capable of reducing output voltage ripples |
| CN105553259A (en) * | 2016-01-28 | 2016-05-04 | 杰华特微电子（杭州）有限公司 | Self power supply control circuit, control method and switching circuit |
| CN207234670U (en) * | 2017-08-04 | 2018-04-13 | 杰华特微电子（杭州）有限公司 | A kind of charge pump circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100840695B1 (en) * | 2006-10-27 | 2008-06-24 | 삼성전자주식회사 | Phase locked loop without a charge pump and integrated circuit having the same |
| US9196367B2 (en) * | 2014-04-02 | 2015-11-24 | Ememory Technology Inc. | Non-volatile memory apparatus and erasing method thereof |
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- 2017-08-04 CN CN201710664194.9A patent/CN107395012B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101488710A (en) * | 2008-10-22 | 2009-07-22 | 成都国腾电子技术股份有限公司 | A charge pump circuit |
| CN104953820A (en) * | 2015-06-29 | 2015-09-30 | 上海芯望电子技术有限公司 | Open-loop charge pump circuit capable of reducing output voltage ripples |
| CN105553259A (en) * | 2016-01-28 | 2016-05-04 | 杰华特微电子（杭州）有限公司 | Self power supply control circuit, control method and switching circuit |
| CN207234670U (en) * | 2017-08-04 | 2018-04-13 | 杰华特微电子（杭州）有限公司 | A kind of charge pump circuit |
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