CN101488710A - A charge pump circuit - Google Patents
A charge pump circuit Download PDFInfo
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- CN101488710A CN101488710A CNA2008100463440A CN200810046344A CN101488710A CN 101488710 A CN101488710 A CN 101488710A CN A2008100463440 A CNA2008100463440 A CN A2008100463440A CN 200810046344 A CN200810046344 A CN 200810046344A CN 101488710 A CN101488710 A CN 101488710A
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Abstract
The invention discloses a charge pump circuit which comprises an input high swing amplitude cascode current mirror, an output high swing amplitude cascode current mirror and a suppression charge shared circuit, wherein, a pull-up and a pull-down circuits are formed by a pull-up output cascode current mirror and a pull-down output cascode current mirror in the output high swing amplitude cascode current mirror as well as the suppression charge shared circuit, a pull-up switch pipe and a pull-down switch pipe. The cascode current mirror structure is adopted by output, so that the resistance of the output current mirror is increased, the influence of the change of the output voltage on the electric current is reduced, and the noise of a switching tube is avoided affecting the output voltage. Meanwhile, the sharing effect and the coupling effect of the charge can be inhibited.
Description
Technical field
The present invention relates to electronic technology field, especially the charge pump circuit of phase-locked loop use.
Background technology
Traditional a lot of digital data transmission; processing and Digital Analog Hybrid Circuits all need accurate clock signal; phase-locked loop is a kind of just to be used for producing according to reference clock the circuit of accurate clock signal widely, and frequency synthesizer and frequency multiplier and clock recovery circuitry etc. all are to utilize phase-locked loop to come the example of control frequency.
Fig. 1 is a typical phase-locked loop loop, has wherein comprised phase discriminator 101, charge pump 102, loop filter 104, voltage controlled oscillator 106 and frequency divider 107.Wherein phase discriminator 101 is used for comparison input reference clock signal fref and from the value of frequency divider 107 clock signal fb, draw signal UP or pulldown signal DN according in one of the phase difference output between two input signals, when fb lags behind the phase place of reference clock, the pulse UP of phase discriminator 101 outputs raising output frequency, when the output signal fb from frequency divider was ahead of the reference clock phase place, phase discriminator 101 outputs were used to reduce the pulsed D N of output frequency.And being input to charge pump circuit 102, charge pump 102 is according to drawing and drop-down detection signal UP and DN the electric charge in release or the accumulation filter capacity in phase discriminator 101 outputs.Loop filter 104 converts the output pulse signal of charge pump the output of to DC simulation control signal.At last, voltage controlled oscillator 106 stabilizing clock that produces correspondent frequency according to the size of analog control voltage is sent into another input of phase discriminator 101 after through frequency divider 107 frequency divisions.
Phase discriminator, charge pump in the phase-locked loop that loop filter and frequency divider are formed, by the frequency division multiple of design frequency divider, can obtain the relevant random frequency multiplication rate of incoming frequency.
Fig. 2 is the existing charge pump circuit, and power vd D is connected to the source electrode of pmos pipe 11, and the drain electrode of pmos pipe 11 is connected to constant-current source 13, and the drain electrode of nmos pipe 14 is connected to constant-current source 12, and nmos manages 14 source grounds.Constant-current source 12 and 13 intersection point meet lpf.Because there is parasitic capacitance c11 in pmos pipe 11 at node e, the grid input pulse of pmos pipe 21 is by low uprising the time, and e point current potential can be by filter output voltage to supply voltage VDD.Same, when opening and turn-offing for second nmos switching tube 14, the voltage that f is ordered changes between no-voltage and filter output voltage, parasitic capacitance c11 and c22 are with iunjected charge, the filtered device electric capacity of electric charge c1 shares simultaneously, and because the existence of parasitic capacitance c23, pulse signal up will be coupled to output.Coupling effect and electric charge are shared can cause very big systematic error.
Though can utilize unity gain amplifier to fix current potential between node e or f and output node, because the use of amplifier can increase the area of domain and bring problem of unstable.Also very high to the requirement of amplifier simultaneously, such as quick response etc.
Among Fig. 3, adopt the constant-current source of the current mirror of cascodes to increase output resistance, reduced the influence of the electric current that voltage fluctuation brings.But since parasitic capacitance C1, the existence of C2, when switch turn-offed, c1 still can be charged as VDD to node A, and c2 can be VSS to the Node B discharge, and capacitance charge is shared effect and is still existed.
Summary of the invention
The purpose of this invention is to provide a kind of high-performance, have and suppress the low spuious charge pump circuit that electric charge is shared effect.
Charge pump circuit of the present invention comprises the high swing amplitude cascode current mirror of input, exports high swing amplitude cascode current mirror, suppresses electric charge and shares circuit; Wherein export in the high swing amplitude cascode current mirror on draw the output common-source common-gate current mirror, on draw and suppress electric charge and share circuit, go up the drag switch pipe and form pull-up circuit, pull-up circuit provides pull-up current to improve charge pump output voltage; Drop-down output common-source common-gate current mirror, drop-down inhibition electric charge are shared circuit and the pipe that pulls down switch has been formed pull-down circuit jointly, pull-down circuit provides pull-down current to reduce charge pump output voltage, draw the inhibition electric charge to share circuit wherein and comprise a first control circuit, drop-down inhibition electric charge is shared circuit and is comprised a first control circuit.
In order further to improve performance, draw the inhibition electric charge to share circuit on this charge pump circuit and further comprise a second control circuit, drop-down inhibition electric charge is shared circuit and is further comprised a second control circuit.
Because the common-source common-gate current mirror structure is adopted in output, increased the resistance of current mirror output, the noise that the variation that has reduced output voltage has also completely cut off switching tube for the influence of electric current has suppressed electric charge simultaneously and has shared effect and coupling effect for output voltage influence.
Description of drawings
The present invention will illustrate by example and with reference to the mode of accompanying drawing, wherein:
Fig. 1 is general PLL block diagram;
Fig. 2 is the circuit diagram of traditional charge pump;
Fig. 3 is another kind of conventional charge pump circuit figure;
Fig. 4 is the schematic diagram of charge pump of the present invention;
Fig. 5 is that charge pump circuit of the present invention is at the different output current wave figure of output voltage
Embodiment
Charge pump circuit according to the present invention comprises the high swing amplitude cascode current mirror of input, export high swing amplitude cascode current mirror, suppress electric charge and share circuit, wherein export in the high swing amplitude cascode current mirror on draw output common-source common-gate current mirror and drop-down output common-source common-gate current mirror and suppress that electric charge is shared circuit, gone up the drag switch pipe, the pipe that pulls down switch formed jointly and drawn and pull-down circuit.Pull-up circuit provides pull-up current to improve charge pump output voltage.Pull-down circuit provides pull-down current to reduce charge pump output voltage.Export high swing amplitude cascode current mirror and improve output resistance, more matching current and make output current be reduced to minimum the susceptibility of output voltage.Electric charge is shared the inhibition circuit and is comprised first control circuit and second control circuit, can both reduce electric charge and share the influence that effect is brought charge pump circuit.
The 4th, the first embodiment schematic diagram in accordance with the principles of the present invention.Comprise high swing amplitude cascode current mirror 55 of input and the high swing amplitude cascode current mirror 54 of output, suppress electric charge and share circuit 113 and 213.Wherein pull-up circuit is made up of mos pipe 101,121,102,108 and 107, pull-down circuit is made up of mos pipe 222,201,202,208 and 207, pull-up circuit has one to suppress the first control circuit 113 that electric charge is shared circuit, pull-down circuit has one to suppress the first control circuit 213 that electric charge is shared circuit, circuit 113 is made up of nmos pipe 108 and 107, and circuit 213 is made up of pmos pipe 208 and 207.102 drain electrodes of last drag switch pipe connect by pmos pipe 101 and 121 forms on draw and export common-source common-gate current mirror 63, last drag switch pipe 102 source electrodes connect power supply.Pipe 202 drain electrodes that pull down switch connect by nmos the pipe 222 and 201 drop-down output common-source common-gate current mirrors of forming 64, and pipe 202 source grounds pull down switch.The drain electrode of the source electrode of pmos pipe 121 and nmos pipe 222 meets output Vo together.
When input UP pulse signal all is in high level, the DN pulse signal all is in low level the time, and switch mos pipe 102,202 all is in cut-off state, and last pull-down circuit all is turned off, so does not have the current direction low pass filter.At this moment, on draw the i.e. pipe of pmos among the figure 101 and 121 of output common-source common-gate current mirror 63 because the effect nmos of circuit 113 manages 107 conductings, cooperate nmos pipe 108 that pmos switching tube 102 and pmos are managed 101 crossed node D voltages and pull into electronegative potential.For the i.e. pipe of nmos among the figure 201 and 222 of drop-down output common-source common-gate current mirror, pmos manages 208 conductings and nmos pipe 207 is moved nmos switching tube 202 and the current potential of the E of intersection point place of nmos pipe 201 to high potential together.
When input up pulse signal is in low level the time, for pull-up circuit, 102 conductings of pmos switching tube, ended by 108,107 circuit of forming 113 this moment, and D point current potential becomes supply voltage.From by to the transfer process of conducting, this pipe trench road is set up needed electric charge and is ended the electric charge of being emitted by 108 and replenish, and exerts an influence and can not export branch road to current mirror at pmos switching tube 102.Same, for pull-down circuit, 202 conductings of nmos switching tube, the pmos pipe 208,207 in the circuit 213 ends, and E point current potential changes to electronegative potential.Nmos switching tube 202 is from ending the electric charge of being emitted by pmos pipe 207 and replenish by setting up the needed electric charge of raceway groove when conducting change, and this will reduce greatly because the systematic error that shared charge effect brought of parasitic capacitance generation.The coupling effect of drawing pulse signal and drop-down pulse signal to order on simultaneously, the use of pmos pipe 207 and nmos pipe 108 all can reduce for node D and E.And then reduce the influence of pulse signal to bias voltage.Thereby influence output current, make the shake of output current diminish, reduce the spuious of PLL output signal.
Fig. 5 is the second embodiment of the present invention.
Spuious in order further to reduce to export, suppress the shake of output current, present embodiment has increased the second control circuit that suppresses the shared circuit of electric charge, second control circuit comprises 109 and 209, wherein 109 comprise pmos pipe 108 and 107,209 comprise nmos pipe 208,207, share the first control circuit 104 of circuit by nmos the pipe 104 and 105 inhibition electric charges of forming, share the first control circuit 204 of circuit by pmos the pipe 205 and 206 inhibition electric charges of forming, the grid of the pmos of two series connection pipe 108 and 107 is connected in the common-source common-gate current mirror 101 and 121 grid, and 108 source electrode connects the up signal through the output after the two-stage reverse 38 simultaneously.107 grounded drains.And cascade nmos pipe 208 and 207 grid are connected the grid of common-source common-gate current mirror 222 and 201 respectively, and 208 drain electrode meets power supply vdd, and 207 source electrode connects the dn signal through the output after the two-stage anti-phase 39.
When the up signal is electronegative potential, sharing second control circuit 109 by pmos pipe 108, the 107 inhibition electric charges of forming ends, when the up signal is become when high by low, 108,107 all conducting balance out variation that E order on draw in the output common-source common-gate current mirror 63 two pmos to manage the coupling effect of 101 and 121 grid upper offset voltages.Same, for sharing second control circuit 209 by nmos pipe 207, the 208 inhibition electric charges of being formed, when the dn signal ends for high potential the time, when dn signal during by high step-down, the variation that D order of the coupling effect bias voltage on 201 and 222 grids is managed in to(for) two nmos in the common-source common-gate current mirror 201 is offset in two nmos pipe 207 and 208 equal conductings.
As above say: the present invention is using under the less situation of device count, the common-source common-gate current mirror structure is adopted in output, as 511 among 54 among Fig. 4 and Fig. 5, increased the resistance of current mirror output, the noise that the variation that has reduced output voltage has also completely cut off switching tube for the influence of electric current has suppressed electric charge simultaneously and has shared effect and coupling effect for output voltage influence.
Disclosed arbitrary feature in this specification (comprising any accessory claim, summary and accompanying drawing) is unless special narration all can be replaced by other equivalences or the alternative features with similar purpose.That is, unless special narration, each feature is an example in a series of equivalences or the similar characteristics.
The present invention is not limited to aforesaid embodiment.The present invention expands to any new feature or any new combination that discloses in this manual, and the arbitrary new method that discloses or step or any new combination of process.
Although the present invention's mode in conjunction with the preferred embodiments is described, it will be appreciated by those skilled in the art that under the prerequisite of the spirit and scope that do not deviate from this law, can change the present invention by using known equivalent way.The front description related to the preferred embodiment will be understood that to be exemplary description rather than to limit the scope of the invention, and scope of the present invention is limited by the accompanying claims.
Claims (7)
1, a kind of charge pump circuit comprises the high swing amplitude cascode current mirror of input, exports high swing amplitude cascode current mirror, suppresses electric charge and shares circuit; Wherein export in the high swing amplitude cascode current mirror on draw the output common-source common-gate current mirror, on draw and suppress electric charge and share circuit, go up the drag switch pipe and form pull-up circuit, pull-up circuit provides pull-up current to improve charge pump output voltage; Drop-down output common-source common-gate current mirror, drop-down inhibition electric charge are shared circuit and the pipe that pulls down switch has been formed pull-down circuit jointly, pull-down circuit provides pull-down current to reduce charge pump output voltage, draw the inhibition electric charge to share circuit wherein and comprise a first control circuit, drop-down inhibition electric charge is shared circuit and is comprised a first control circuit.
2, charge pump circuit as claimed in claim 1 is characterized in that: on draw and suppress electric charge and share circuit and further comprise a second control circuit, drop-down inhibition electric charge is shared circuit and is further comprised a second control circuit.
3, a kind of charge pump circuit, comprise high swing amplitude cascode current mirror 55 of input and the high swing amplitude cascode current mirror 54 of output, suppress electric charge and share circuit 113 and 213, wherein pull-up circuit is by mos pipe 101,121,102,108 and 107 form, pull-down circuit is by mos pipe 222,201,202,208 and 207 form, pull-up circuit has one to suppress the first control circuit 113 that electric charge is shared circuit, pull-down circuit has one to suppress the first control circuit 213 that electric charge is shared circuit, circuit 113 is by nmos pipe 108,107 form, circuit 213 is by pmos pipe 208,207 form, 102 drain electrodes of last drag switch pipe connect by pmos pipe 101 and 121 forms on draw and export common-source common-gate current mirror 63, last drag switch pipe 102 source electrodes connect power supply, pipe 202 drain electrodes that pull down switch connect the drop-down output common-source common-gate current mirror of being made up of nmos pipe 222,201 64, and pipe 202 source grounds pull down switch.The drain electrode of the source electrode of pmos pipe 121 and nmos pipe 222 meets output Vo together.
4, charge pump circuit as claimed in claim 3 is characterized in that: when input up pulse signal is in high level, the dn pulse signal is in low level the time, and switch mos pipe 102,202 all is in cut-off state, and last pull-down circuit all is turned off.
5, charge pump circuit as claimed in claim 3, it is characterized in that: when input up pulse signal is in low level the time, for pull-up circuit, 102 conductings of pmos switching tube, ended by 108,107 circuit of forming 113 this moment, and D point current potential becomes supply voltage; For pull-down circuit, 202 conductings of Nmos switching tube, the Pmos pipe 208,207 in the circuit 213 ends, and E point current potential changes to electronegative potential.
6, a kind of charge pump circuit is characterized in that: second control circuit comprises 109 and 209, and wherein 109 comprise that pmos pipe 108 and 107,209 comprises nmos pipe 208 and 207; By the first control circuit 104 of the shared circuit of nmos the pipe 104 and 105 inhibition electric charges of forming, share the first control circuit 204 of circuit by pmos the pipe 205 and 206 inhibition electric charges of forming; The grid of the pmos of two series connection pipe 108 and 107 is connected in the common-source common-gate current mirror 101 and 121 grid, and 108 source electrode connects the up signal through the output after the two-stage reverse 38,107 grounded drains simultaneously; And cascade nmos pipe 208 and 207 grid are connected the grid of common-source common-gate current mirror 222 and 201 respectively, and 208 drain electrode meets power supply vdd, and 207 source electrode connects the dn signal through the output after the two-stage anti-phase 39.
7, charge pump circuit as claimed in claim 6, it is characterized in that: when the up signal is electronegative potential, sharing second control circuit 109 by pmos pipe 108, the 107 inhibition electric charges of forming ends, when the up signal is become when high by low, 108,107 all conducting balance out variation that E order on draw in the output common-source common-gate current mirror 63 two pmos to manage the coupling effect of 101 and 121 grid upper offset voltages; For sharing second control circuit 209 by nmos pipe 207, the 208 inhibition electric charges of being formed, when the dn signal ends for high potential the time, when dn signal during by high step-down, the variation that D order of the coupling effect bias voltage on 201 and 222 grids is managed in to(for) two nmos in the common-source common-gate current mirror 201 is offset in two nmos pipe 207 and 208 equal conductings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100463440A CN101488710B (en) | 2008-10-22 | 2008-10-22 | A charge pump circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100463440A CN101488710B (en) | 2008-10-22 | 2008-10-22 | A charge pump circuit |
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| Publication Number | Publication Date |
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| CN101488710A true CN101488710A (en) | 2009-07-22 |
| CN101488710B CN101488710B (en) | 2012-06-13 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2008100463440A Expired - Fee Related CN101488710B (en) | 2008-10-22 | 2008-10-22 | A charge pump circuit |
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Cited By (11)
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| WO2011050214A1 (en) * | 2009-10-21 | 2011-04-28 | Qualcomm Incorporated | Rf buffer circuit with dynamic biasing |
| CN102664520A (en) * | 2012-05-10 | 2012-09-12 | 东南大学 | Phase-locked loop charge pump circuit with low current mismatch |
| CN102684670A (en) * | 2012-05-29 | 2012-09-19 | 上海山景集成电路技术有限公司 | High speed signal output circuit with zero reverse current |
| CN102006063B (en) * | 2009-09-02 | 2013-02-06 | 中国科学院微电子研究所 | Autotracking switch type charge pump for phase lock loop |
| TWI396955B (en) * | 2009-10-13 | 2013-05-21 | Nanya Technology Corp | Pump system can dynamically increase its current capability and method thereof |
| CN103346784A (en) * | 2013-06-18 | 2013-10-09 | 成都嘉纳海威科技有限责任公司 | Matching type charge pump circuit for phase-locked loop |
| CN103887966A (en) * | 2014-03-24 | 2014-06-25 | 华为技术有限公司 | Charge pump implementation circuit |
| CN104716828A (en) * | 2015-03-23 | 2015-06-17 | 东南大学 | High-swing charge pump circuit for nonautomatic extinguishment type superregenerative receiver |
| CN107395012A (en) * | 2017-08-04 | 2017-11-24 | 杰华特微电子（杭州）有限公司 | A kind of charge pump circuit and its control method |
| CN107872153A (en) * | 2016-11-29 | 2018-04-03 | 珠海市杰理科技股份有限公司 | A kind of charge pump circuit |
| CN113557667A (en) * | 2019-05-23 | 2021-10-26 | 华为技术有限公司 | Phase-locked loop |
Family Cites Families (3)
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| JP3959886B2 (en) * | 1999-03-24 | 2007-08-15 | 松下電工株式会社 | lighting equipment |
| KR100900864B1 (en) * | 2003-12-11 | 2009-06-04 | 모사이드 테크놀로지스, 인코포레이티드 | High output impedance charge pump for PLL/DLL |
| CN101222226A (en) * | 2007-01-10 | 2008-07-16 | 中国科学院微电子研究所 | Self-calibration charge pump circuit used for phase-locked loop and its self-calibration feedback loop |
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- 2008-10-22 CN CN2008100463440A patent/CN101488710B/en not_active Expired - Fee Related
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| CN102006063B (en) * | 2009-09-02 | 2013-02-06 | 中国科学院微电子研究所 | Autotracking switch type charge pump for phase lock loop |
| TWI396955B (en) * | 2009-10-13 | 2013-05-21 | Nanya Technology Corp | Pump system can dynamically increase its current capability and method thereof |
| KR101435550B1 (en) | 2009-10-21 | 2014-09-02 | 퀄컴 인코포레이티드 | Rf buffer circuit with dynamic biasing |
| CN102577123A (en) * | 2009-10-21 | 2012-07-11 | 高通股份有限公司 | RF buffer circuit with dynamic biasing |
| US8415991B2 (en) | 2009-10-21 | 2013-04-09 | Qualcomm Incorporated | RF buffer circuit with dynamic biasing |
| US8149023B2 (en) | 2009-10-21 | 2012-04-03 | Qualcomm Incorporated | RF buffer circuit with dynamic biasing |
| WO2011050214A1 (en) * | 2009-10-21 | 2011-04-28 | Qualcomm Incorporated | Rf buffer circuit with dynamic biasing |
| CN102577123B (en) * | 2009-10-21 | 2016-03-16 | 高通股份有限公司 | There is the RF buffer circuits of dynamic bias |
| CN102664520A (en) * | 2012-05-10 | 2012-09-12 | 东南大学 | Phase-locked loop charge pump circuit with low current mismatch |
| CN102684670A (en) * | 2012-05-29 | 2012-09-19 | 上海山景集成电路技术有限公司 | High speed signal output circuit with zero reverse current |
| CN102684670B (en) * | 2012-05-29 | 2015-08-05 | 上海山景集成电路股份有限公司 | The signal high speed output circuit of zero reverse irrigated current |
| CN103346784A (en) * | 2013-06-18 | 2013-10-09 | 成都嘉纳海威科技有限责任公司 | Matching type charge pump circuit for phase-locked loop |
| CN103346784B (en) * | 2013-06-18 | 2016-04-13 | 成都嘉纳海威科技有限责任公司 | A kind of matching type charge pump circuit for phase-locked loop |
| CN103887966B (en) * | 2014-03-24 | 2017-06-20 | 华为技术有限公司 | Charge pump realizes circuit |
| CN103887966A (en) * | 2014-03-24 | 2014-06-25 | 华为技术有限公司 | Charge pump implementation circuit |
| CN104716828A (en) * | 2015-03-23 | 2015-06-17 | 东南大学 | High-swing charge pump circuit for nonautomatic extinguishment type superregenerative receiver |
| CN104716828B (en) * | 2015-03-23 | 2017-03-22 | 东南大学 | High-swing charge pump circuit for nonautomatic extinguishment type superregenerative receiver |
| CN107872153A (en) * | 2016-11-29 | 2018-04-03 | 珠海市杰理科技股份有限公司 | A kind of charge pump circuit |
| CN107395012A (en) * | 2017-08-04 | 2017-11-24 | 杰华特微电子（杭州）有限公司 | A kind of charge pump circuit and its control method |
| CN107395012B (en) * | 2017-08-04 | 2023-05-16 | 杰华特微电子股份有限公司 | Charge pump circuit and control method thereof |
| CN113557667A (en) * | 2019-05-23 | 2021-10-26 | 华为技术有限公司 | Phase-locked loop |
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