CN114443395A

CN114443395A - Dual-card testing device, method and equipment and readable storage medium

Info

Publication number: CN114443395A
Application number: CN202210071142.1A
Authority: CN
Inventors: 赖振楠; 王嗣钧; 余正涛
Original assignee: Hosin Global Electronics Co Ltd
Current assignee: Hosin Global Electronics Co Ltd
Priority date: 2022-01-20
Filing date: 2022-01-20
Publication date: 2022-05-06

Abstract

The application provides a double-card testing device, method, equipment and readable storage medium, wherein the device comprises a host, a control chip and a testing board; the host is used for sending a test instruction, storing test data and writing the data into the test mother card and the test daughter card of the test board from the host and/or reading the data from the test mother card and the test daughter card of the test board; the test board is used for bearing the test mother card, the test daughter card and the control chip; the control chip is used for controlling the same test data in the host to be written into the test mother card and the test daughter card at the same time, reading the data from the test mother card and the test daughter card and inputting the data into the comparison circuit for comparison processing to obtain a test result. According to the test data input method and device, the test data are written into the test mother card and the test daughter card respectively, and meanwhile the data written into the test mother card and the test daughter card are read and input into the comparison circuit to be compared, so that the test result is obtained quickly, the test efficiency is effectively improved, and the test flow is shortened.

Description

Dual-card testing device, method and equipment and readable storage medium

Technical Field

The application relates to the technical field of storage equipment, in particular to a double-card testing device, method, equipment and a readable storage medium.

Background

With the development of information processing technology, the demand for memory devices is increasing, and some small memory devices (such as memory cards) are widely used due to their advantages of portability, high data storage capacity and easy access. Based on the increase of the requirement of the memory card, the importance of the memory card testing process is relatively increased before the mass production stage of the memory card, and the efficiency and the compatibility of the memory card are further ensured. Therefore, how to complete the memory card test with low cost and high efficiency is an important issue for system manufacturers and designers.

In the conventional memory card test, a tester is required to manually process the test step by step so as to ensure the operation of the memory card. For example, each memory card is manually inserted or removed by a tester. Further, in the actual testing process, various testing devices are required to ensure the performance and compatibility of the memory card. It can be seen that the conventional memory card testing procedure is not only time-consuming but also expensive. Therefore, there is a need for a memory card testing apparatus that can save cost and be automatically executed, does not need to rely on manpower and can improve testing efficiency, thereby providing a memory card testing process that has cost considerations, is reliable, and is easy to implement.

In the prior art, the principle of testing a memory card is to write the same data into a plurality of memory cards, read the data back, and verify the coincidence degree of the read data and the written data, so as to operate the memory card. In the process of designing and implementing the application, the inventor of the application finds that the prior art has some defects, when the storage device to be tested is a storage card, if the capacity of the storage card is overlarge, the required data volume to be tested is very large, so that the time of the whole testing process is overlong; in addition, the data to be tested needs to be written into a plurality of storage devices to be tested from the host 11, including the processes of writing-reading-data comparison, and rewriting-erasing block-reading-data comparison, and such testing processes need to be repeated many times, so that the stability of the storage data of the testing devices is ensured, the testing process is time-consuming and also needs a large amount of resources, the testing cost is greatly increased, and the testing efficiency is low.

The foregoing description is provided for general background information and is not admitted to be prior art.

Disclosure of Invention

In view of the above technical problems, the present application provides a dual-card testing device, method, device and readable storage medium, which can quickly test a test card and improve the testing efficiency of a memory card.

In order to solve the technical problem, the application provides a dual-card testing device, which comprises a host, a control chip and a testing board, wherein the testing board comprises a testing mother card and a testing daughter card; the control chip comprises a comparison circuit;

the host is used for sending a test instruction and storing test data, and writing the data into the test mother card and the test daughter card of the test board from the host and/or reading the data from the test mother card and the test daughter card of the test board;

the test board is used for bearing the test mother card, the test daughter card and the control chip;

the control chip is used for controlling the same test data in the host to be written into the test mother card and the test daughter card at the same time, reading the data from the test mother card and the test daughter card and inputting the data into the comparison circuit for comparison processing, so as to obtain a test result of the test daughter card.

Optionally, the reading the data from the test mother card and the test daughter card and inputting the data into the comparison circuit for comparison processing to obtain the test result of the test daughter card includes:

the read data written into the same test mother card and the same data written into the same test daughter card by the host are subjected to byte-by-byte exclusive OR operation through the comparison circuit to generate an exclusive OR operation accumulation result;

and comparing and analyzing according to the XOR operation accumulation result to obtain a test result corresponding to the test daughter card.

Optionally, the comparison circuit includes a plurality of groups of byte xor operation logic circuits connected in series, and each group of byte xor operation logic circuits includes two nor gates and an and gate.

Optionally, the comparing and analyzing according to the accumulated result of the exclusive or operation to obtain a test result corresponding to the test daughter card includes:

comparing the XOR operation accumulation results one by one through the control chip;

and when any byte value in the XOR operation accumulation result is 1 through comparison, at least one of the test mother card and the test daughter card is judged to be a unqualified card.

Optionally, after determining that at least one of the test mother card and the test daughter card is a failed card, the method further includes:

and comparing the same test data with the data read by the test mother card and the data read by the test daughter card again through the control chip to obtain test results corresponding to the test mother card and the test daughter card respectively.

Optionally, before the writing the same test data into the test mother card and the test daughter card of the test board, respectively, the method further includes:

and writing the same test data into a data cache region in the control chip through the host, wherein the data cache region comprises a write data cache region and a read data cache region.

Correspondingly, the application also provides a double-card testing method, which is executed in a double-card testing device, wherein the double-card testing device comprises a host, a control chip and a testing board, and the control chip comprises a comparison circuit; the double-card test method comprises the following steps:

sending a test instruction and storing test data through the host computer, and writing the data into the test mother card and the test daughter card of the test board from the host computer and/or reading the data from the test mother card and the test daughter card of the test board;

and the control chip controls the same test data in the host to be written into the test mother card and the test daughter card at the same time, reads the data from the test mother card and the test daughter card and inputs the data into the comparison circuit for comparison processing to obtain a test result of the test daughter card.

The application also provides computer equipment, which comprises a memory and a processor, wherein the memory stores a computer program, and the processor realizes the steps of the double-card testing method when executing the computer program.

The present application also proposes a computer-readable storage medium having stored thereon a computer program which, when being executed by a processor, carries out the steps of the dual card testing method of any one of the preceding claims.

The embodiment of the application has the following beneficial effects:

as described above, the dual card testing apparatus, the method, the device and the readable storage medium provided by the present application include a host, a control chip and a testing board, where the testing board includes a testing mother card and a testing daughter card; the control chip comprises a comparison circuit; the host is used for sending a test instruction and storing test data, and writing the data into the test mother card and the test daughter card of the test board from the host and/or reading the data from the test mother card and the test daughter card of the test board; the test board is used for bearing the test mother card, the test daughter card and the control chip; the control chip is used for controlling the same test data in the host to be written into the test mother card and the test daughter card at the same time, reading the data from the test mother card and the test daughter card and inputting the data into the comparison circuit for comparison processing, so as to obtain the test result of the test daughter card. This application is when writing into same test data to test mother card and test daughter card through the host computer, read the same data of writing in test mother card and test daughter card through control chip, and input to comparison circuit and compare the processing to test mother card and test daughter card, thereby realize the test of writing in simultaneously and reading simultaneously to test mother card and test daughter card, effectively obtain the test result of test card fast, thereby need not the test card and read completely and write in after the test and just can obtain the test result completely, greatly improve the efficiency of software testing of storage card, shorten whole test flow, reduce test time and cost.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly described below, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

FIG. 1 is a schematic structural diagram of a dual-card testing device according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram illustrating an embodiment of a dual card testing apparatus;

FIG. 3 is a diagram of an 8-bit XOR circuit according to an embodiment of the present application;

FIG. 4 is a logic diagram of an 8-bit XOR circuit provided by an embodiment of the present application;

FIG. 5 is a schematic structural diagram of an SRAM provided in an embodiment of the present application;

FIG. 6 is a schematic flowchart of a dual-card testing method according to an embodiment of the present disclosure;

fig. 7 is a block diagram schematically illustrating a structure of a computer device according to an embodiment of the present disclosure.

The implementation, functional features and advantages of the objectives of the present application will be further explained with reference to the accompanying drawings. With the above figures, there are shown specific embodiments of the present application, which will be described in more detail below. These drawings and written description are not intended to limit the scope of the inventive concepts in any manner, but rather to illustrate the inventive concepts to those skilled in the art by reference to specific embodiments.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the recitation of an element by the phrase "comprising an … …" does not exclude the presence of additional like elements in the process, method, article, or apparatus that comprises the element, and further, where similarly-named elements, features, or elements in different embodiments of the disclosure may have the same meaning, or may have different meanings, that particular meaning should be determined by their interpretation in the embodiment or further by context with the embodiment.

It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope herein. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context. Also, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used in this specification, specify the presence of stated features, steps, operations, elements, components, items, species, and/or groups, but do not preclude the presence, or addition of one or more other features, steps, operations, elements, components, species, and/or groups thereof. The terms "or," "and/or," "including at least one of the following," and the like, as used herein, are to be construed as inclusive or mean any one or any combination. For example, "includes at least one of: A. b, C "means" any of the following: a; b; c; a and B; a and C; b and C; a and B and C ", again for example," A, B or C "or" A, B and/or C "means" any of the following: a; b; c; a and B; a and C; b and C; a and B and C'. An exception to this definition will occur only when a combination of elements, functions, steps or operations are inherently mutually exclusive in some way.

It should be understood that, although the steps in the flowcharts in the embodiments of the present application are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and may be performed in other orders unless explicitly stated herein. Moreover, at least some of the steps in the figures may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, in different orders, and may be performed alternately or at least partially with respect to other steps or sub-steps of other steps.

The words "if", as used herein, may be interpreted as "at … …" or "at … …" or "in response to a determination" or "in response to a detection", depending on the context. Similarly, the phrases "if determined" or "if detected (a stated condition or event)" may be interpreted as "when determined" or "in response to a determination" or "when detected (a stated condition or event)" or "in response to a detection (a stated condition or event)", depending on the context.

It should be noted that step numbers such as S10 and S20 are used herein for the purpose of more clearly and briefly describing the corresponding contents, and do not constitute a substantial limitation on the sequence, and those skilled in the art may perform S20 first and then perform S10 in the specific implementation, which should be within the scope of the present application.

It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

In the following description, suffixes such as "module", "component", or "unit" used to indicate elements are used only for facilitating the description of the present application, and have no particular meaning in themselves. Thus, "module", "component" or "unit" may be used mixedly.

Firstly, the application scenario that can be provided by the application is introduced, for example, a device, a method, equipment and a readable storage medium for testing a dual card are provided, when test data are written into a test mother card and a test daughter card respectively, the same data written into the test mother card and the test daughter card are read by a control chip and input to a comparison circuit for comparison processing, so that a test result of the test card is obtained quickly, and the test efficiency is improved effectively.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a dual-card testing device according to an embodiment of the present disclosure. The dual-card testing device comprises a host 11, a control chip 12 and a testing board 13, wherein the testing board 13 comprises a testing mother card and a testing daughter card (hereinafter referred to as mother card/card 1 and daughter card/card 2); the control chip 12 comprises a comparison circuit;

the host 11 is used for sending test instructions and storing test data, and writing the test data from the host 11 into the mother card and daughter card of the test board 13 and/or reading the data from the mother card and daughter card of the test board 13.

Specifically, the host 11 may be any type of computer system with respect to the host 11. For example. The host 11 may be various electronic systems such as a notebook computer, a desktop computer, a smart phone, a tablet computer, an industrial computer, a game console, and a digital camera. In this embodiment, the host 11 is configured to send a test command and store test data, and the control chip 12 is configured to receive and analyze the test command, so as to write the same test data from the host 11 to the mother card and the daughter card in the test board of the dual-card test apparatus simultaneously according to the test command. For example, test data divided into several batches is written into the mother card and the daughter card simultaneously within a preset cycle time.

The test board 13 is used for carrying a mother card, a daughter card and a control chip 12.

Specifically, the test board 13 is mainly used for carrying a mother card, a daughter card and a control chip, and a card slot is formed in the test board, so that the mother card and the daughter card to be tested are inserted into the card slot of the test board. The test board may be, for example, a USB hub connection reader. One end of the USB concentrator is a USB interface, and the USB interface is connected with the host 11; the other end includes a plurality of independent USB interfaces that can be connected to a plurality of corresponding card readers to connect the mother card, daughter card and control chip 12.

The control chip 12 is used for controlling the test data in the host 11 to be written into the mother card and the daughter card at the same time, reading the test data from the mother card and the daughter card, and inputting the test data into the comparison circuit for comparison processing, so as to obtain a test result of the daughter card.

Optionally, in some embodiments, the reading host 11 writes test data written into the mother card and the daughter card and inputs the test data into the comparison circuit for comparison processing to obtain a test result of the daughter card, which may specifically include:

the read test data written into the mother card and the daughter card by the host 11 are subjected to byte-by-byte exclusive OR operation through the comparison circuit to generate an exclusive OR operation accumulation result;

and comparing and analyzing according to the XOR operation accumulation result to obtain a test result corresponding to the daughter card.

Specifically, the control chip 12 is mainly used for controlling the test data in the host 11 to be written into the mother card and the daughter card of the test board 13, reading the test data from the mother card and the daughter card at the same time, and inputting the test data into the comparison circuit in the control chip 12 for xor operation, so as to obtain the test result corresponding to each test card. The comparison circuit is specifically an exclusive-or circuit, since the data is composed of a plurality of bytes, the comparison circuit is actually a byte exclusive-or accumulation circuit, since the data is continuous, when the byte exclusive-or operation is performed byte by byte, the comparison circuit is actually an accumulation logic, and the accumulation hardware can be a register.

In a specific embodiment, as shown in fig. 2, the dual card testing apparatus includes a host 11, a control chip 12 and a testing board 13, first, the host 11 is connected to the control chip 12 through a PCIe/USB interface, and writes test data into the mother card/card 1 and the daughter card/card 2 after passing through an SRAM buffer of the control chip 12, and simultaneously, reads the test data written in by the host through the comparison circuits of the control chip 12, performs xor operation on the test data, the test data being read by the card 1 and the test data being read by the card 2, accumulates the xor operation result into a first register, and reads the xor operation result of the first register through the control chip 12 for comparison and identification, thereby obtaining the test results of the card 1 and the card 2, and if one byte xor operation result is "1", it indicates that the test result of at least one card is NG. In the actual test process, the host 11 sends out an instruction for writing data into each card, the control chip 12 executes the instruction, and the control chip 12 controls the data of the host 11 to be cached in the cache region SRAM first. The control chip 12 is a control chip 12 of the testing device, the control chip 12 is welded to a PCB, one end of the PCB is provided with an interface connected with the host 11, and the other end of the PCB is provided with a card slot inserted with a plurality of memory cards for realizing the card connection to the testing board.

Optionally, in some embodiments, the comparing and analyzing according to the accumulated result of the exclusive or operation to obtain the test result corresponding to the daughter card may specifically include:

comparing the accumulated result of the exclusive-or operation one by one byte through the control chip 12;

and when any byte value in the XOR operation accumulation result is 1 through comparison, at least one of the mother card and the daughter card is judged to be a disqualified card.

Specifically, in the test process, since the same data is written into the mother card and the daughter card, the control chip 12 controls to read data from the two cards at the same time, and puts the data read from each card into the comparison circuit for exclusive or operation. The test data in the two cards are expressed in binary '0' and '1', the data are subjected to exclusive-or operation by an exclusive-or circuit, if the two cards are OK, the data read from the two cards are subjected to exclusive-or operation, and the result of the exclusive-or operation is '0'; if one of the two cards is NG, then the result of the XOR operation is "1".

In a specific embodiment, since the data is read from the memory card by the control chip 12, the data is read in a byte-by-byte manner; therefore, the data comparison, i.e. the exclusive or operation, is byte-by-byte comparison, is the same as the data read-write principle of the memory card, and is also the read-write of one byte by one byte or the read-write of one bit by one, and can be set according to the actual requirement. Therefore, if the result of one byte exclusive-or operation is "1", it indicates that the test result of at least one card is NG, and the test result of the memory card is obtained.

Optionally, in some embodiments, the comparison circuit comprises a plurality of sets of byte xor operation logic circuits connected in series, each set of byte xor operation logic circuits comprising two nor gates and one and gate.

Specifically, as shown in fig. 3 and 4, the logic principle of the xor circuit is that the xor of a and B is equivalent to the exclusive or of a and B, i.e. the xor circuit and the logic circuit are 8-bit exclusive or circuit

The corresponding logic circuit consists of two NOR gates and an AND gate. For 8-bit binary comparison, 8 groups of logic circuits are connected in series. Corresponding to a single cmos exclusive-or gate circuit, 8 groups of logic circuits are connected in series. And the corresponding single cmos exclusive-or gate circuit consists of a stage of NOR gate and a stage of NOR gate. For inputs A and B, first pass through a NOR gate to obtain (A + B) -, and then pass through an AND NOR gate to obtain an XOR output of A and B.

The specific truth table is shown in the following table 1, so that when the XOR operation result of only two test cards is '0', the reading results of the two cards are judged to be consistent; when a byte XOR result of "1" occurs, it indicates that at least one card has a test result of NG.

A	B	NOR gate output	And nor gate output
				0	0	1	0
0	1	0	1
				1	0	0	1
1	1	0	0

TABLE 1

For example, the exclusive or circuit operation with 8 bits is performed, for example, the binary data with 32 bits of the mother card read by the comparison circuit is 10011100001100010101111010111, and the binary data with 32 bits of hexadecimal is 9c 315 e b 7; the 32-bit binary data of the daughter card is 10011100001100110101110010110111, and the 32-bit hexadecimal data of the daughter card is 9c 335 c b 7; and after the XOR accumulation operation, the XOR comparison result is 00000000000000100000001000000000 (binary system) or 00020200 (16 system), and if the 4 th bit and the 6 th bit are found to have errors through comparison, at least one test card is determined to be NG.

In a specific embodiment, external data is firstly input into a BULK FIFO of an SRAM for waiting processing, then the FIFO data is stored in a USB or other operation again as required according to the read-write requirements of the SRAM (the FIFO data is compiled and encoded, the operation is completed and then returned to the SRAM, and the USB or other operation is stored again as required.

Optionally, in some embodiments, after determining that at least one of the mother card and the daughter card is a failed card, the method may further include:

the same test data is compared with the data read by the mother card and the data read by the daughter card again through the control chip 12, and the test results corresponding to the mother card and the daughter card are obtained respectively.

Specifically, when it is determined that NG occurs in at least one of the test cards, secondary comparison processing needs to be performed on the mother card and the daughter card, the test data is compared with the data read by the mother card and the data read by the daughter card again, the comparison principle is the same as that of the previous comparison process of the mother card and the daughter card, and the test data in the write data buffer in the SRAM of the static random access memory is separately compared with the data read by the mother card and the data read by the daughter card in the read data buffer, so that the test result of NG for which test card or NG for both cards is accurately obtained, and the accuracy of the memory card test is further improved.

Optionally, in some embodiments, before writing the same test data into the mother card and the daughter card of the test board 13, the method may further include:

the test data is written to a data buffer including a write data buffer and a read data buffer in the control chip 12 by the host 11.

Specifically, when a test is started, the host 11 writes test data into the control chip 12, the control chip 12 segments the test data sent by the host 11, and the segmented W1, W2, W3 and W4 are written into a write data buffer in the SRAM, and then the W1, W2, W3 and W4 of the write data buffer are written into the mother card and the daughter card at the same time, so that data is written into each test card at the same time.

As shown in fig. 5, the SRAM includes a write data buffer and a read data buffer, where the write data buffer is used to buffer test data written by the host into the test card, and the read data buffer is used to buffer test data written by the mother card and the daughter card into the test card.

In the prior art, when the storage device to be tested is a memory card, if the capacity of the memory card is too large, the required data volume to be tested is very large, which results in that the time of the whole testing process is too long; in addition, the data to be tested needs to be written into a plurality of storage devices to be tested from the host 11, including the processes of writing-reading-data comparison, and rewriting-erasing block-reading-data comparison, and such testing processes need to be repeated many times, so that the stability of the storage data of the testing devices is ensured, the testing process is time-consuming and also needs a large amount of resources, the testing cost is greatly increased, and the testing efficiency is low. In addition, in the prior art, different test data are written into different test storage terminals respectively through different periods, so that the writing efficiency and the reading efficiency are extremely low.

In order to solve the above technical problems, an embodiment of the present invention provides a dual card testing apparatus, which includes a host 11, a control chip 12 and a testing board 14, wherein the testing board 13 includes a mother card and a daughter card; the control chip 12 comprises a comparison circuit, and the host 11 is used for sending a test instruction and writing test data into a mother card and a daughter card of the test board 13 respectively; the test board 13 is used for bearing the mother card, the daughter card and the control chip 12; the control chip 12 is used for reading the test data written into the mother card and the daughter card by the host 11 and inputting the test data into the comparison circuit for comparison processing to obtain the test result of the daughter card. It can be seen that this embodiment is at first through the host computer when writing in same test data to mother card and daughter card, read the test data of writing in mother card and daughter card through control chip, and input to compare the circuit and carry out the comparison processing to mother card and daughter card, thereby realize the test of writing in simultaneously and reading simultaneously to mother card and daughter card, effectively obtain the test result of test card fast, thereby need not the test card and can obtain the test result after reading completely and writing in the test completely, greatly improve the efficiency of test of storage card, shorten whole test flow, reduce test time and cost.

Correspondingly, as shown in fig. 6, an embodiment of the present application further provides a dual-card testing method, which is executed in a dual-card testing apparatus, where the dual-card testing apparatus includes a host, a control chip and a testing board, and the control chip includes a comparison circuit; the double-card test method comprises the following steps:

and S10, sending a test instruction through the host, and writing the same test data into the test mother card and the test daughter card of the test board respectively.

And S20, mounting the test mother card, the test daughter card and the control chip through the test board.

And S30, reading the same data written into the test mother card and the test daughter card by the host through the control chip, and inputting the same data into the comparison circuit for comparison to obtain a test result of the test daughter card.

Optionally, in some embodiments, step S30 may specifically include:

s31, simultaneously writing the read host into the same data of the test mother card and the test daughter card through a comparison circuit, and performing byte-by-byte XOR operation to generate an XOR operation accumulation result;

and S32, comparing and analyzing according to the XOR operation accumulation result to obtain a test result corresponding to the test daughter card.

Optionally, in some embodiments, step S32 may specifically include:

s321, comparing the XOR operation accumulation results one by one through a control chip;

s322, when any byte value in the XOR operation accumulation result is 1 through comparison, at least one of the test mother card and the test daughter card is judged to be a disqualified card.

Optionally, in some embodiments, after step S322, the method for testing a dual card may further include:

and S323, comparing the same test data with the data read by the test mother card and the data read by the test daughter card again through the control chip to obtain test results corresponding to the test mother card and the test daughter card respectively.

Optionally, in some embodiments, step S10 may further include:

the same test data is written into a data cache region in the control chip through the host, wherein the data cache region comprises a write data cache region and a read data cache region.

The dual-card testing method provided by the embodiment of the application is executed in a dual-card testing device, the dual-card testing device comprises a host, a control chip and a testing board, and the control chip comprises a comparison circuit; the double-card test method comprises the following steps: sending a test instruction through a host computer, and respectively writing the same test data into a mother card and a daughter card of the test board; the test board is used for bearing the mother card, the daughter card and the control chip; the test data written into the mother card and the daughter card by the host is read by the control chip and input into the comparison circuit for comparison processing, and the test result of the test daughter card is obtained. According to the embodiment of the application, test data are written into the mother card and the daughter card through the host computer, the test data written into the mother card and the daughter card are read through the control chip, the comparison circuit is input to compare the mother card and the daughter card, the test of writing into and reading out simultaneously of the mother card and the daughter card is realized, the test result of the test card is obtained quickly and effectively, the test card is not required to be completely read and written into the test and then can obtain the test result, the test efficiency of the storage card is greatly improved, the whole test flow is shortened, and the test time and the cost are reduced.

Referring to fig. 7, a computer device, which may be a server and whose internal structure may be as shown in fig. 7, is also provided in the embodiment of the present application. The computer device includes a processor, a memory, a network interface, and a database connected by a system bus. Wherein the computer designed processor is used to provide computational and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used for storing data such as a double-card test method and the like. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program when executed by a processor to implement a dual card testing method, comprising: sending a test instruction through a host computer, and respectively writing the same test data into a mother card and a daughter card of the test board; the test board is used for bearing the mother card, the daughter card and the control chip; and reading test data written into the mother card and the test daughter card by the host through the control chip, and inputting the test data into the comparison circuit for comparison to obtain a test result of the daughter card.

An embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored, and the computer program, when executed by a processor, implements a dual card testing method, including the steps of: sending a test instruction through a host computer, and respectively writing the same test data into a mother card and a daughter card of the test board; the test board is used for bearing the mother card, the daughter card and the control chip; and reading test data written into the mother card and the daughter card by the host through the control chip, and inputting the test data into the comparison circuit for comparison to obtain a test result of the daughter card.

According to the executed double-card testing method, the same test data is written into the mother card and the daughter card through the host, the test data written into the mother card and the daughter card is read through the control chip, and the test data is input into the comparison circuit to compare the mother card and the daughter card, so that the test of simultaneous writing and simultaneous reading of the mother card and the daughter card is realized, the test result of the test card is quickly and effectively obtained, the test result can be obtained after the test card is completely read and completely written without the test card, the testing efficiency of the storage card is greatly improved, the whole testing process is shortened, and the testing time and the testing cost are reduced.

It is to be understood that the foregoing scenarios are only examples, and do not constitute a limitation on application scenarios of the technical solutions provided in the embodiments of the present application, and the technical solutions of the present application may also be applied to other scenarios. For example, as can be known by those skilled in the art, with the evolution of system architecture and the emergence of new service scenarios, the technical solution provided in the embodiments of the present application is also applicable to similar technical problems.

The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.

The steps in the method of the embodiment of the application can be sequentially adjusted, combined and deleted according to actual needs.

The units in the device in the embodiment of the application can be merged, divided and deleted according to actual needs.

In the present application, the same or similar term concepts, technical solutions and/or application scenario descriptions will be generally described only in detail at the first occurrence, and when the description is repeated later, the detailed description will not be repeated in general for brevity, and when understanding the technical solutions and the like of the present application, reference may be made to the related detailed description before the description for the same or similar term concepts, technical solutions and/or application scenario descriptions and the like which are not described in detail later.

In the present application, each embodiment is described with emphasis, and reference may be made to the description of other embodiments for parts that are not described or illustrated in any embodiment.

The technical features of the technical solution of the present application may be arbitrarily combined, and for brevity of description, all possible combinations of the technical features in the embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, the scope of the present application should be considered as being described in the present application.

Through the description of the foregoing embodiments, it is clear to those skilled in the art that the method of the foregoing embodiments may be implemented by software plus a necessary general hardware platform, and certainly may also be implemented by hardware, but in many cases, the former is a better implementation. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, a controlled terminal, or a network device) to execute the method of each embodiment of the present application.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. The procedures or functions according to the embodiments of the present application are all or partially generated when the computer program instructions are loaded and executed on a computer. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored on a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (e.g., coaxial cable, fiber optic, digital subscriber line) or wirelessly (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, memory Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.

The above description is only a preferred embodiment of the present application, and not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application, or which are directly or indirectly applied to other related technical fields, are included in the scope of the present application.

Claims

1. The double-card testing device is characterized by comprising a host, a control chip and a testing board, wherein the testing board comprises a testing mother card and a testing daughter card; the control chip comprises a comparison circuit;

2. The dual-card testing device of claim 1, wherein the reading the data from the test mother card and the test daughter card and inputting the data into the comparison circuit for comparison to obtain the test result of the test daughter card comprises:

3. The dual-card testing device of claim 2, wherein the comparison circuit comprises a plurality of sets of byte exclusive-or circuits connected in series, each set of byte exclusive-or circuits comprising two nor gates and an and gate.

4. The dual-card testing device of claim 2, wherein the comparing and analyzing the accumulated results of the exclusive or operation to obtain the testing results corresponding to the test daughter card comprises:

5. The dual card test apparatus of claim 4, further comprising, after said determining that at least one of said test mother card and said test daughter card is a failing card:

6. The dual-card testing device of claim 1, further comprising, before writing the same test data to the test mother card and the test daughter card of the test board, respectively:

7. A double-card test method is characterized in that the method is executed in a double-card test device, the double-card test device comprises a host, a control chip and a test board, and the control chip comprises a comparison circuit; the double-card test method comprises the following steps:

8. The dual-card testing method of claim 7, wherein the reading the data from the test mother card and the test daughter card and inputting the data into the comparison circuit for comparison to obtain the test result of the test daughter card comprises:

9. The method according to claim 8, wherein the comparison circuit comprises a plurality of sets of byte exclusive-or operation logic circuits connected in series, each set of byte exclusive-or operation logic circuit comprising two nor gates and an and gate.

10. The dual-card testing method according to claim 8, wherein the comparing and analyzing according to the accumulated result of the exclusive or operation to obtain a testing result corresponding to the test daughter card comprises:

11. The dual card test method of claim 10, after said determining at least one of said test mother card and said test daughter card is a failing card, said method further comprising:

12. The dual card testing method of claim 7, wherein before said writing the same test data to the test mother card and the test daughter card of the test board, respectively, the method further comprises:

13. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor, when executing the computer program, implements the steps of the dual card testing method of any one of claims 7 to 12.

14. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the dual card testing method according to any one of claims 7 to 12.