CN114443347A

CN114443347A - Configurable CRC code calculation method

Info

Publication number: CN114443347A
Application number: CN202111587754.8A
Authority: CN
Inventors: 伍彬山; 周毅; 杨唤荣; 万江华
Original assignee: Hunan Guliang Microelectronics Co ltd
Current assignee: Hunan Guliang Microelectronics Co ltd
Priority date: 2021-12-23
Filing date: 2021-12-23
Publication date: 2022-05-06
Anticipated expiration: 2041-12-23
Also published as: CN114443347B

Abstract

The invention discloses a configurable CRC code calculation method, which comprises the following steps: step S1: configuring CRC parameters; configuring a CRC configuration variable according to a required CRC parameter model, and clearing a CRC result variable; step S2: preprocessing parameters; preprocessing a polynomial GPOLY of a CRC model and an initial value INIT, and aligning a most significant bit (GW bit) of a parameter to a DW bit of the most significant bit of a parameter variable or the most significant bit of data; step S3: preprocessing data; step S4: calculating a CRC check code; carrying out bitwise XOR operation on the shifted initial value INIT _ PRE and the shifted input DATA DATA _ PRE to obtain INIT _ OR _ DATA; and according to the setting of FlipOUT, carrying out the turnover operation on the CRC calculation result CRCOUT to obtain CRCOUT _ Flip. The invention has the advantages of simple principle, simple and convenient operation, good flexibility and the like.

Description

Configurable CRC code calculation method

Technical Field

The invention mainly relates to the technical field of data communication and data storage, in particular to a configurable CRC code calculation method.

Background

CRC (Cyclic Redundancy Check) is one of the most commonly used error checking codes in the field of data communication and data storage. CRC has the characteristic of strong error detection capability. According to statistics, the error probability that the CRC check code cannot be found is less than 0.0047%. Meanwhile, CRC has a special point of low overhead, is easy to realize by using an encoder and a detection circuit, and is far superior to parity check, arithmetic, check and other modes.

CRC algorithmBased on binary galois field GF (2) polynomial arithmetic. The GF (2) polynomial has only one variable x, the coefficients of which are only 0 and 1. The CRC algorithm maps a message of length k bits to a GF (2) polynomial M. The sending end and the receiving end agree on a GF (2) polynomial P with the number of times r, which is called a generator polynomial. The addition of r 0 polynomials to the message is M ', obviously M' ═ Mx^r. Dividing M' by P will obtain a remainder polynomial R with degree equal to or less than R-1, and the corresponding R-bit value is CRC check code. The transmitting end transmits the k bit message together with the R bit check code (namely M' + R), and the receiving end divides the polynomial corresponding to all the received k + R bit data by a polynomial P to judge whether the remainder is 0. If 0, no error occurs, otherwise an error occurs.

A complete CRC calculation model should contain the following information:

g: a 16-ary representation of the polynomial P is generated. For example: the contract polynomial for CRC-32 is 0x04C11DB7 (ignoring the most significant "1", the complete generator is 0x104C11DB 7).

GW: the polynomial width, i.e., the CRC bit number, is generated, and GW ═ r. Such as CRC-8, the generated CRC is 8 bits.

INIT: CRC initial value, consistent with GW bit width

FlipiN: whether each byte of the data to be tested is bit-reversed, True or False. Such as raw data 34₁₆(0011 0100₂) If FlipIN is True, after flipping, it is 2C₁₆(00101100₂)。

FlipOUT: after calculation, before the exclusive-or output, whether the entire data is bit-inverted, True or False. If the calculated CRC value is 97₁₆(10010111₂) If FlipOUT is True, the result E9 is obtained after the flipping₁₆(11101001₂)。

XOROUT: and XOR-processing the calculation result and the parameter to obtain a final CRC value which is consistent with the GW bit width.

The choice of generator polynomial P affects the checking effect of the CRC. Through theoretical derivation and long-term practical verification, dozens of different standard CRC models are formed. Different fields may use different CRC check codes. For example, in the field of electronic communications, chip DS2401/DS18B20 of American trusted (MAXIM), uses the CRC-8/MAXIM model; the SD card or MMC uses a CRC-7/MMC model; the Modbus communication uses a CRC-16/MODBUS parameter model; CRC-5/USB and CRC-16/USB models used in the USB protocol; the hardware CRC calculation module carried by STM32 uses the CRC-32 model, and the like.

The following table lists three standard CRC calculation models:

in addition, the completion of the CRC calculation requires specifying the following two processing objects:

DW: the data bit width. In an actual hardware system, the minimum data granularity bit width that the hardware can provide is R, but the granularity of the data stream that may need to be processed is less than R, so one data bit width must be provided in order to handle this situation.

DATA: the effective width of the data to be processed, i.e. the object to be verified, is DW.

In view of the bit-wise computation nature of CRC, parallel CRC computations are typically done in hardware. However, parallel fast CRC calculation can only be performed on a certain generator polynomial and cannot be configurable. However, in a general system, different CRC models are often required to be switched to adapt to different application scenarios. Therefore, the parameter configuration supporting the CRC model can effectively improve the utilization rate of the hardware and increase the audience range of the hardware.

In the parallel CRC, in the conventional art, some patent applications are proposed by practitioners, including:

CN202110442600.3 parallel CRC calculation method, device and application thereof;

CN201611254479.7 'A CRC implementation method, apparatus and network device';

CN201910028840.1 "A method for implementing parallel CRC by a multistage pipeline Circuit";

CN201910927889.0 CRC check method and apparatus;

CN201910042371.9 polar code encoding method and apparatus for concatenated CRC codes;

CN201811295059.2 CRC parallel computing method and System;

the disclosures of the above prior patent documents are directed to parallelization implementations of deterministic polynomials.

In addition, a patent application cn202011335136.x "a method and a system for implementing a polynomial-configurable CRC digital circuit" is proposed by a practitioner, and in the technical scheme thereof, a method and a system for implementing a polynomial-configurable CRC digital circuit are disclosed.

The technical scheme of the patent application has some disadvantages:

1. the technical scheme only aims at CRC calculation of the data stream with the data granularity of bytes. Although this disclosure refers to generalized N, there is no method provided how to generalize the granularity of data from itself (8 bits) to N, and this is not a straightforward process. Therefore, the method in the technical scheme can only be applied to a plurality of 8-bit byte data streams.

2. The technical scheme only mentions the configurable polynomial and does not provide details on how to realize the configurable polynomial to participate in operation in subsequent calculation. When different polynomials are run on fixed hardware, direct participation in the calculation will bring wrong calculation results.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: aiming at the technical problems in the prior art, the invention provides a configurable CRC code calculation method which is simple in principle, simple and convenient to operate and good in flexibility.

In order to solve the technical problems, the invention adopts the following technical scheme:

a configurable CRC code calculation method, comprising the steps of:

step S1: configuring CRC parameters; configuring a CRC configuration variable according to a required CRC parameter model, and clearing a CRC result variable;

step S2: preprocessing parameters; preprocessing a polynomial GPOLY of a CRC model and an initial value INIT, and aligning a most significant bit (GW bit) of a parameter to a DW bit of the most significant bit of a parameter variable or the most significant bit of data;

step S3: preprocessing data;

step S4: calculating a CRC check code; carrying out bitwise XOR operation on the shifted initial value INIT _ PRE and the shifted input DATA DATA _ PRE to obtain INIT _ OR _ DATA; and according to the setting of FlipOUT, carrying out the turnover operation on the CRC calculation result CRCOUT to obtain CRCOUT _ Flip.

As a further improvement of the process of the invention: the step S2 includes:

step S201: generating a polynomial GPOLY left shift (R-GW) bit to obtain GPOLY _ PRE;

step S202: the initial value INIT is shifted left (R-GW) to get INIT _ PRE.

As a further improvement of the process of the invention: the step S2 includes:

step S201: clearing the high R-GW bit of GPOLY and INIT;

step S202: if GW < DW, generating polynomial GPOLY left shift (DW-GW) bit to obtain GPOLY _ PRE; moving the INIT left (DW-GW) position to obtain INIT _ PRE;

step S203: otherwise, GPOLY and INIT remain unchanged.

As a further improvement of the process of the invention: the step S3 includes:

step S301: acquiring input data;

step S302: if the FlipIN is equal to 1, carrying out overturning operation on the input DATA DATA to obtain DATA _ flip, wherein the overturned DATA are still aligned to the right; otherwise, DATA _ flip ═ DATA;

step S303: the input DATA DATA _ flip is shifted left (R-DW) by a bit, resulting in DATA _ PRE.

As a further improvement of the process of the invention: the step S3 includes:

step S301: acquiring input data;

step S302: if the FlipIN is equal to 1, carrying out overturning operation on the input DATA DATA to obtain DATA _ flip, wherein the overturned DATA are still aligned to the right; otherwise DATA _ flip ═ DATA;

step S303: clearing the high-order R-DW bit of the DATA _ flip;

step S304: if GW is larger than DW, DATA DATA _ flip is shifted to the left by (GW-DW) bit to obtain DATA _ PRE; otherwise DATA _ PRE is DATA _ flip.

As a further improvement of the process of the invention: if the system is a left side high-position alignment system, the step S303 uses G _ CLR to perform calculation; the xor will be performed using XOROUT _ CLR in the step S304.

As a further improvement of the process of the invention: the step S4 includes:

step S401: carrying out bitwise XOR operation on the shifted initial value INIT _ PRE and the shifted input DATA DATA _ PRE to obtain INIT _ OR _ DATA;

step S402: let crc _ iteration [0] ═ INIT _ OR _ DATA, i ═ 0;

step S403: for i ∈ [0, D-1], calculating by utilizing GPOLY _ PRE and crc _ iteration [ i ] to obtain crc _ iteration [ i +1 ]; d results, namely crc _ iteration [1], … and crc _ iteration [ D ], are finally obtained in the calculation process according to the sequence of i from small to large; the calculation formula is as follows:

crc _ iteration [ i ] - (crc _ iteration [ i-1] < <1) ^ ({ R { crc _ iteration [ i-1] [ R ] } }) } } & GPOLY _ PRE); wherein { R { } denotes splicing R times repeatedly into new data;

step S404: selecting crc _ iteration [ DW ] as CRCOUT according to DW;

step S405: and according to the setting of FlipOUT, carrying out the turnover operation on the CRC calculation result CRCOUT to obtain CRCOUT _ Flip.

As a further improvement of the process of the invention: the step S4 includes:

step S402: let crc _ iteration [0] ═ INIT _ OR _ DATA, i ═ 0;

step S403: for i ∈ [0, D-1], calculating crc _ iteration [ i +1] by using GPOLY _ PRE and crc _ iteration [ i ]. The calculation process is carried out according to the sequence of i from small to large, and D results are finally obtained, namely crc _ iteration [1], … and crc _ iteration [ D ]. The calculation formula is as follows:

crc_iteration[i]＝(crc_iteration[i-1]<<1)^({R{crc_iteration[i-1][max(DW,GW)]}}&GPOLY_PRE)。

wherein { R { } denotes splicing R times repeatedly into new data;

step S404: selecting crc _ iteration [ DW ] as CRCOUT according to DW;

As a further improvement of the process of the invention: step S5, post-processing the CRC calculation result; the step S5 includes:

step S501: if there are other data to be processed, let INIT _ PRE be CRCOUT _ Flip, then go to step S3, and continue processing the next data;

step S502: if no other data to be calculated exists currently, right shifting CRCOUT _ Flip by GW to obtain CRC _ RESULT;

step S503: and finally, carrying out exclusive OR on the CRC _ RESULT and XOROUT, and outputting the RESULT.

step S502: if no other data to be calculated exists currently, if DW is larger than GW, the CRCOUT _ Flip is shifted to the right by DW-GW bit to obtain CRC _ RESULT; otherwise, CRC _ RESULT is CRCOUT _ Flip;

step S503: the CRC _ RESULT is xored with xorreut, and the RESULT is output.

Compared with the prior art, the invention has the advantages that:

1. the configurable CRC code calculation method has the advantages of simple principle, simple and convenient operation and good flexibility, almost all parameters of a CRC model can be flexibly configured, a solution method is provided for processing small-granularity data by a large-data bit width system, and the flexibility is greatly improved. Meanwhile, the method provided by the invention is more beneficial to hardware implementation, and the right alignment method can effectively reduce the logic complexity.

2. The invention discloses a configurable CRC code calculation method, mainly discloses a CRC calculation method of a data stream with general width and details thereof, and discloses details of how to finish effective CRC calculation under the conditions of different polynomials and different polynomial widths and also discloses the configurable details of other aspects of a CRC model.

Drawings

FIG. 1 is a schematic flow diagram of the process of the present invention.

Detailed Description

The invention will be described in further detail below with reference to the drawings and specific examples.

In order to facilitate understanding of the technical scheme of the invention, the invention firstly explains some symbols in the technical scheme:

r: the system parameter width is R, and in a typical system, R may be 32.

GPOLY: generating 2-system data corresponding to the polynomial, wherein the width of the data type is R.

INIT: the CRC calculates an initial value, the data type being of width R.

RESULT: the width of the data type is R as a result of the CRC calculation.

XOROUT: the CRC results in an exclusive or value and the data type is R wide. And after the calculation is finished, carrying out exclusive OR on the result and XOROUT to obtain a final result.

FlipIN/FlipOUT: respectively, whether to bit flip the input data/computation result. 1-indicates inversion, and 0-indicates no inversion.

GW: the width of the CRC, e.g., the GW value for CRC-8, is 8.

D/DW: d denotes a system minimum data bit width, and DW denotes a CRC calculation effective data width. For example, the minimum granularity of the system data is 8 bits, but the CRC calculation valid data bit width DW may be 7 bits, i.e., D > ═ DW. This facilitates flexible processing of small granularity data by large data bit width systems.

DATA: the data is input, the data type bit width is D, and the effective data width is DW.

As shown in fig. 1, the configurable CRC code calculation method of the present invention includes the steps of:

step S1: configuring CRC parameters;

and configuring CRC configuration variables according to the currently required CRC parameter model. The CRC result variable is cleared.

Step S2: preprocessing parameters;

suppose the system uses the mode of right alignment of the lower bits of data and the highest bit is on the left (in fact, the general system is right aligned; for the systems of other alignment modes, the result can be obtained through simple corresponding change).

And preprocessing a polynomial GPOLY of the CRC model and an initial value INIT according to the current configuration parameters, and aligning the most significant bit of the parameter, namely the GW bit, to the highest R bit of the parameter variable. Obviously, for the case that the most significant bit of the parameter is already aligned to the R bit, only the low-order invalid data needs to be cleared.

In a specific application example, the step S2 may include:

step S201: the generator polynomial GPOLY is left shifted (R-GW) by a bit to get GPOLY _ PRE.

Step S202: the initial value INIT is shifted left (R-GW) by a bit to obtain INIT _ PRE.

In another specific application example, in step S2, the polynomial GPOLY of the CRC model and the initial value INIT may also be preprocessed according to the current configuration parameters, and the most significant bit of the parameter, i.e., the GW bit, is aligned with the most significant bit of the data, i.e., the DW bit. Therefore, the step S2 may also include:

step S201: clearing the high R-GW bit of GPOLY and INIT;

step S203: otherwise, GPOLY and INIT remain unchanged.

Step S3: preprocessing data;

in a specific application example, the step S3 may include:

step S301: acquiring input data;

In another specific application example, the step S3 may also include:

step S301: acquiring input data;

step S302: if FlipIN is equal to 1, the input DATA DATA is flipped to obtain DATA _ flip. The flipped data is still right aligned; otherwise DATA _ flip ═ DATA;

step S303: clearing the high-order R-DW bit of the DATA _ flip;

In a specific application, if the system is a left side high alignment system, then in step S303, G _ CLR is used for calculation; xoring will be performed using xorcout _ CLR in step S304.

Step S4: calculating a CRC check code;

in a specific application example, the step S4 may include:

step S401: the shifted initial value INIT _ PRE is bitwise xored with the shifted input DATA _ PRE to obtain INIT _ OR _ DATA (the width of which is still R bits).

Step S402: let crc _ iteration [0] ═ INIT _ OR _ DATA, i ═ 0;

step S403: for i ∈ [0, D-1], calculating crc _ iteration [ i +1] by using GPOLY _ PRE and crc _ iteration [ i ]. The calculation process is carried out according to the sequence of i from small to large, and D results, namely crc _ iteration [1], … and crc _ iteration [ D ] are finally obtained. The calculation formula is as follows:

crc_iteration[i]＝(crc_iteration[i-1]<<1)^

({ R { crc _ iteration [ i-1] [ R ] } } & GPOLY _ PRE). Where { R { } denotes splicing R times repeatedly into new data.

Step S404: according to DW, crc _ iteration [ DW ] is selected as CRCOUT.

In another specific application example, step S403 in step S4 may also be:

where { R { } denotes splicing R times repeatedly into new data.

Step S5: post-processing a CRC calculation result;

in a specific application example, the step S5 may include:

step S501: if there is any other data to be processed, let INIT _ PRE be CRCOUT _ Flip, and then go to step S3 to continue processing the next data.

Step S502: if no other data to be calculated exists currently, the CRCOUT _ Flip is shifted to the right by GW bits to obtain CRC _ RESULT.

In another specific application example, the step S5 may also include:

Step S502: if no other data to be calculated exists currently, if DW is larger than GW, the CRCOUT _ Flip is shifted to the right by DW-GW bit to obtain CRC _ RESULT; otherwise CRC _ RESULT is CRCOUT _ Flip.

Step S503: the CRC _ RESULT is xored with xorreut, and the RESULT is output.

In a particular application, CRC calculations are often performed on a series of data. Then, by combining the above technical solutions of the present invention, it can be known that after each data has been calculated with the CRC check code, it is necessary to determine whether there are other data to be processed to determine whether to jump to the beginning to continue processing new data. There is no need to perform post-processing on the result of the CRC calculation before the jump, so that processing of consecutive data does not require re-preprocessing of INIT.

If the different embodiment environments are considered, in case of a hardware implementation system, adding an additional selector is not actually beneficial to the circuit timing, so that the process may return to step S2 after the post-processing in step S5 is completed, and a more regular flow may be executed. As shown by the dashed path in fig. 1.

The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may be made by those skilled in the art without departing from the principle of the invention.

Claims

1. A configurable CRC code calculation method, comprising the steps of:

step S3: preprocessing data;

2. The method for calculating a configurable CRC code according to claim 1, wherein said step S2 comprises:

3. The method for calculating a configurable CRC code according to claim 1, wherein said step S2 comprises:

step S201: clearing the high R-GW bit of GPOLY and INIT;

step S203: otherwise, GPOLY and INIT remain unchanged.

4. The method for calculating a configurable CRC code according to claim 1, wherein said step S3 comprises:

step S301: acquiring input data;

5. The method for calculating a configurable CRC code according to claim 1, wherein said step S3 comprises:

step S301: acquiring input data;

step S303: clearing the high-order R-DW bit of the DATA _ flip;

6. The method for calculating the configurable CRC code according to claim 5, wherein if it is a left-side high-order alignment system, the step S303 uses G _ CLR for calculation; the xor will be performed using XOROUT _ CLR in the step S304.

7. The method for calculating the configurable CRC code according to any one of claims 1 to 5, wherein the step S4 comprises:

step S402: let crc _ iteration [0] ═ INIT _ OR _ DATA, i ═ 0;

step S404: selecting crc _ iteration [ DW ] as CRCOUT according to DW;

8. The method for calculating the configurable CRC code according to any one of claims 1 to 5, wherein the step S4 comprises:

step S401: performing bitwise XOR operation on the shifted initial value INIT _ PRE and the shifted input DATA DATA _ PRE to obtain INIT _ OR _ DATA;

step S402: let crc _ iteration [0] ═ INIT _ OR _ DATA, i ═ 0;

wherein { R { } denotes splicing R times repeatedly into new data;

step S404: selecting crc _ iteration [ DW ] as CRCOUT according to DW;

9. The method for calculating the configurable CRC code according to any one of claims 1 to 5, further comprising a step S5 of post-processing a CRC calculation result; the step S5 includes:

10. The method for calculating the configurable CRC code according to any one of claims 1 to 5, further comprising a step S5 of post-processing a CRC calculation result; the step S5 includes:

step S502: if no other data to be calculated exists currently, if DW > GW, the CRCOUT _ Flip is shifted to the right by DW-GW bit to obtain CRC _ RESULT; otherwise, CRC _ RESULT is CRCOUT _ Flip;

step S503: the CRC _ RESULT is xored with xorreut, and the RESULT is output.